2D GRAPHENE AND GRAPHENE NANORIBBON FIELD EFFECT TRANSISTORS. A Dissertation. Submitted to the Graduate School. of the University of Notre Dame

Transcription

1 2D GRAPHENE AND GRAPHENE NANORIBBON FIELD EFFECT TRANSISTORS A Dissertation Submitted to the Graduate School of the University of Notre Dame in Partial Fulfillment of the Requirements of the Degree of Doctor of Philosophy by Kristóf Tahy Debdeep Jena, Director Graduate Program in Electrical Engineering Notre Dame, Indiana April 2012

2 2D GRAPHENE AND GRAPHENE NANORIBBON FIELD EFFECT TRANSISTORS Abstract by Kristóf Tahy The impressive properties of graphene such as the linear energy dispersion relation, room-temperature mobility as high as cm 2 /V. s, and current densities in excess of 2 A/mm range or even 10 A/mm for nanoribbons make it an attractive candidate for electronic devices of the future. This work explores whether graphene fulfills the promises raised by the extraordinary material properties. First, realistic expectations of large area and nanoscale graphene devices are examined. Fabrication and electrical measurements of 2D graphene devices lead to the verification of the predicted T 2 dependence of the intrinsic carrier concentration in graphene. A suitable model allows the extraction of the mobility of carriers at the Dirac point, a quantity of great ambiguity in the literature. The opening of bandgaps in graphene nanoribbons by quantum confinement holds promise for digital electronic device applications. The fabrication, device performance, and modeling of low bandgap GNR FETs are presented. For substantial current modulation at room-temperature, sub-10 nm GNR widths are required and is challenging. Process limitations lead to the utilization of a new e-beam lithography resist

3 Kristóf Tahy (HSQ) and to the switch to epitaxial graphene on SiC substrates. The measurements of the GNR FETs confirm larger than ~0.1 ev bandgap in ~10 nm wide ribbons. These results have been replicated on FETs formed from CVD grown graphene.

4 TABLE OF CONTENTS Table of Figures... iv Acknowledgments... xi Chapter 1: Introduction Motivation Background Production of graphene State of the art in graphene FET performance Aim of this work...8 Chapter 2: Properties of 2D graphene Electronic structure of the graphene lattice Carrier statistics and mobility in graphene Experimental data and device model Mobility in graphene Minimum conductivity in graphene The Dirac point mobility...36 Chapter 3: Device applications of 2D graphene D graphene FETs Epitaxial graphene RF FETs on SiC for analog applications Wafer-scale 2D graphene FETs Long channel graphene FET model...51 Chapter 4: Graphene nanoribbons: fundamental properties D quantum confinement in graphene nanoribbons GNR fabrication and carrier transport Exfoliated GNR FETs with lateral p-n junction...68 Chapter 5: Wafer-scale fabrication and characterization of GNR FETs Epitaxial GNR FETs on SiC CVD grown GNR FETs...87 Chapter 6: p-n junction formation in graphene Double gated GNR Side gate control Gate oxide induced doping E-beam exposure of HSQ as a tool for doping ii

5 Chapter 7: Comparison of graphene FETs Chapter 8: Summary and further work References iii

6 TABLE OF FIGURES Figure 1.1: The role of graphene in future electronic circuits as interconnect or even as active element. All 2D semiconducting MoS 2 and insulating BN with GNRs can be used in a transparent few atomic layer transistor....3 Figure 1.2: (left) Example of an exfoliated graphene flake. There is a monolayer flake on the middle, double layer flake on the left and a multilayer flake on the right. (right) AFM micrograph of the epitaxially grown graphene surface on SiC. The graphene is atomically smooth; the steps are of the substrate. The image is 10 x 10 m, gray scale range: 20 nm....5 Figure 2.1: Lattice of graphene. The primitive lattice vectors a 1,2 are defining the unit cell. There are two carbon atoms per unit-cell, denoted by A and B. Also shown are the vectors to the first nearest neighbors of an A atom 1,2,3 used in the LCAO calculation Figure 2.2: Energy bands of graphene. (left) Energy spectrum in units of 0 = 2.8 ev (nearest neighbor hopping energy) as a function of momentum k i. (right) Zoomed portion of the linear energy band near the Dirac point. Plot was made using Matlab Figure 2.3: Scattering rates 1/τ vs energy in 2D graphene: T = 300 K, n imp = cm 2. The bar shows the relative rates at an energy of 0.6 ev [57] Figure 2.4: (a) AFM micrograph of an epitaxial graphene sample. The area is carefully selected to show parts without graphene. Complete graphene coverage is usual as shown in Figure 1.2 (b). The slice denoted in (a) is the cross section in (b), which shows 0.4 nm steps corresponding to a single layer of graphene. (c) Raman spectrum of the epitaxial graphene Figure 2.5: TEM micrograph of epitaxial graphene on SiC. The lattice constant of 6H- SiC is used as a calibration for the scale of the image. 0 th and 1 st graphene layers are identified. The interlayer distance is extended for several more periods to increase accuracy / 5 = 3.27 Å is the lattice constant c Figure 2.6: (top) Optical image of a typical top-gated epitaxial graphene FET on SiC substrate. (bottom) Schematic cross section of the device along with the considered parasitic resistances besides the intrinsic resistance of the graphene channel R CH...24 iv

7 Figure 2.7: (a) The statistical distribution of the sheet resistance R sh and (b) the contact resistance R C. The middle line is the average; the squares contain 75% of all measurement and all the data lies in between the top and bottom marks Figure 2.8: (a) The relation of the quantum capacitance C Q on 300 K and the oxide capacitance C OX of a graphene FET with 15 nm Al 2 O 3 gate. The total capacitance C T has little deviation from C OX. (b) The effect of C Q on the carrier concentration as a function of gate bias Figure 2.9: Calculated mobilities as a function of the carrier concentration of a back gated graphene FET. There is a significant deviation around n = 0 cm -2, but above n = cm -2 the difference is acceptable and the trend is similar...29 Figure 2.10: (a) Source-drain current I DS as a function of the gate bias V G and temperature for a top-gated 2D graphene FET. (b) Comparison of the channel resistance R CH before (extrinsic) and after (intrinsic) the parasitic resistances were subtracted...30 Figure 2.11: The intrinsic channel resistance R CH as a function of temperature. At the Dirac point the tendency is very pronounced Figure 2.12: The measured J D for various devices shows similar trend in some cases to the calculated current based on the expected (Eq. (2.24)) intrinsic carrier concentration n i (assuming = 1000 cm 2 /Vs). On the other hand the data for some devices significantly deviate from the trend Figure 2.13: The temperature dependence of the mobility (a) at n = cm -2 carrier concentration based on the transfer characteristics and Eq. (2.35) and (b) based on the Hall measurement of the SiC/graphene/HSQ system. The different symbols in (a) means different devices, while in (b) it denotes consecutive measurements...33 Figure 2.14: The calculated minimum carrier concentration based on the measurement compared to the intrinsic carrier concentration n i as a function of T 2. The measurements are separated into two graphs to help inspection. The interception of the fitting with the y axis provides the impurity concentration n 0, while from the slope the Dirac point mobility Dirac can be determined Figure 2.15: The intrinsic carrier concentration n i as a function of the temperature T in linear scale with second order polynomial fitting Figure 2.16: The Dirac point mobility as a function of temperature. The values are approximately an order of magnitude higher than the mobility at n = cm Figure 2.17: The discrepancy of FE and CON at the Dirac point - solved. The Dirac point mobility Dirac is closer to CON, but finite. The dashed line is guide to the eye of the possible mobility at low carrier concentration Figure 3.1: Schematic of a back gated 2D graphene FET fabrication: (a) (c) back gate fabrication, (d) (f) contact metallization, (g) (h) channel etch v

8 Figure 3.2: (a) I DS as a function of V G at V DS = 20 mv for short-channel (0.5 μm) and long-channel (8 μm) back-gated graphene FETs. Inset (a) Raman spectrum of single layer graphene. Inset (b) Low field I-V curves of long-channel FETs with V G = -35 V, V G = +10 V. (b) I-V curves of a long-channel FETs. Inset is a SEM image of this FET. The scale bar is 1.5 μm Figure 3.3: Current density as a function of drain biases for FETs with different channel lengths varied from 0.5 μm to 8 μm. Clear loss of gate modulation is observed with the shrinking of the graphene channel length. V G = -38 V, V G = +9.5 V. The effective field is simply calculated by F=V DS /L Figure 3.4: Consecutive breakdown of a naturally multi-ribbon device. The breakdown occurs at >20 kv/cm acceleration field following saturation at >1.0 A/mm current density. Inset (a) SEM image of the multi-ribbon device. The scale bar is 6 μm. Inset (b) the breakdown process without scaling the currents by the actual width.45 Figure 3.5: Output characteristics of a saturating large area graphene transistor (a) and the graphene transistor (b), which RF characteristic is shown in Figure 3.6. (c) Transconductance as a function of gate voltage at V DS = 20 mv Figure 3.6: (a) Current gain as function of frequency for a graphene FET with 2 μm long gate. (b) f T and f max of a graphene transistor with 0.5 μm long ebeam-defined gate.48 Figure 3.7: Representative transfer (a) and output (b) characteristics of 2D epitaxial graphene FETs Figure 3.8: (a) Raman map of the 2D peak intensity across a region of the transferred graphene, showing uniform intensity over large area. (b) Transfer characteristic of a 2D graphene FET transferred to Si/SiO 2 substrate. The device exhibit relatively high and symmetric mobility and 5 times modulation. The calculated impurity concentration is cm -2. (c) High-field family I-V curves showing both sub-linear and super-linear behavior, characteristic of a zero bandgap single layer graphene Figure 3.9: Schematic of the modeled device. The graphene channel is capacitively controlled by the gates. R C is assumed to be gate voltage independent Figure 3.10: Schematic band diagram of a graphene channel between the source and the drain at small positive gate bias for the case of (a) low V DS and (b) high V DS. E F is the Fermi level and E 0 (=E C =E V ) is the charge neutrality point Figure 3.11: Family I-V of a GNR FET compared with (a) long channel Si MOSFET model and (b) self-consistent GNR FET model. The long-channel traditional model is not capturing the ambipolar transport regime but predicts saturation instead vi

9 Figure 4.1: The carrier concentration of GNRs with various widths as a function of the channel potential at room temperature in logarithmic (left) and in linear (right) scale...59 Figure 4.2: Band gap versus GNR width: theory and available experimental data compared. As a reference the bandgap of a semiconducting carbon nanotube (CNT) E G ~ 0.9 ev/ d (nm) [91] is included Figure 4.3: (a) SEM image of an Al strip (top) and a GNR (bottom) formed using the Al strip as etching mask. (b) Device structure and layout Figure 4.4: (a) Temperature-dependent transfer characteristics at 20 mv drain bias. (b) Typical transfer curve measured at 30 K showing conductance plateaus Figure 4.5: (a) Fitting of the experimental data using Landauer formula. (b) Simulated gate capacitance using COMSOL Figure 4.6: (a) High field family I-Vs measured at 77 K and 4.2 K (inset). (b) Sketch of sub-band filling at the current saturation regime Figure 4.7: (a) SEM micrograph of GNR FETs. Half of the channels are top-gated, while the whole device is back-gated. The channel length is 2 m, the gate width is 1 m. The width of the GNR is 30 nm. (b) Device schematics and wiring diagram of the device model showing the critical resistances and the influence of the gates on the two parts of the channel Figure 4.8: (a) Conductance steps at 4.2 K at low source-drain voltage (linear scale); (b) At higher bias (V DS = 1 V) the modulation is smaller. This high bias conductance is not influenced by the temperature; room temperature measurement yields the same result Figure 4.9: Comparison of the transfer characteristics (a) before and (b) after the top gate oxide deposition. The initially p-doped device shifted to n-doped. The I ON /I OFF ratio decreased by several orders of magnitude. (a) shows the temperature dependence of I DS, which served as the basis of the bandgap extraction...71 Figure 4.10: Measured room temperature I DS versus V DS at -70 V (a), 0 V (b) and +70 V (c) back gate bias Figure 4.11: Simulated device characteristic at the same bias conditions as the device shown in Figure I DS versus V DS at -70 V (a), 0 V (b) and +70 V (c) back gate bias Figure 4.12: (a) Simulated intrinsic energy level E 0 along the graphene channel in case of three representative bias conditions. (b) I-V characteristic of the tunnel junction. Figures adopted from [88] vii

10 Figure 5.1: Schematic of the epitaxial sub-10 nm GNR FET fabrication: (a) (c) graphene patterning with HSQ and O 2 plasma, (d) (e) metallization, (f) oxide seeding and ALD, (g) (h) top gate metal deposition Figure 5.2: (a) HSQ line width as a function of electron-beam line dose in 20 nm of HSQ resist at two different developer temperatures. (b) HSQ gratings with line width of 12 nm and spacing of 10 nm exposed in 20 nm of HSQ on graphene Figure 5.3: (a) SEM micrograph of a GNR FET showing the 10 nm HSQ mask and the source/drain electrodes. (b) The 10 nm graphene channel after the removal of the HSQ mask. (c) Optical microscope images of the wafer-scale GNR FETs Figure 5.4: Scaling behavior of the GNR FETs. (a) The transfer characteristic of FETs with increasing width. (b) I D -V D at V GS = V Dirac shows increasing barrier as the width is decreasing Figure 5.5: (a) Transfer characteristic of a 10 nm GNR FET at room temperature and at 4 K. (b) Differential conductance di D /dv DS as a function of V DS and V GS. The color bar is the exponent, log 10 (di DS /dv DS ) in -1. Transport gap of ~ 0.15 ev is observed. (c) Low temperature family I-V of the same device showing good on/off ratio Figure 5.6: Schematic band diagram of the low-bias operation of the GNR SBFET. (a) OFF state with barrier of E G /2. Thermionic emission is possible only at room temperature. (b) In the ON state the barrier height is the same, but tunneling in possible at any T...82 Figure 5.7: Comparison of the experimental ((a) & (b)) and modeling ((c) & (d)) results of the differential conductance for a 10 nm and a 17 nm GNR FET as a function of V DS and V GS at 4 K. The black color represents low conductance as indicated by the color bar Figure 5.8: Cross sectional TEM of the parallel GNR array. 2-3 graphene layers were found with less than ~ 10 nm widths. The periodicity of GNRs is exactly 30 nm, as designed Figure 5.9: (a) Gate dependence of I DS in a FET with 30 parallel 13 nm GNR channel with a 30 nm pitch. Despite the possible width variations, an on/off ratio of 10 4 is achieved at low temperature. (b) Output characteristics of the 30 GNR array-fet at 4 K. (c) The current drive of the 30 GNR array-fet is approximately 30 times of the current of a single GNR FET Figure 5.10: (a) Differential conductance di D /dv DS as a function of V DS and V GS. The color bar is the exponent, log 10 (di DS /dv DS ) in -1. Transport gap of ~ 0.5 ev is observed. (b) and (c) Low temperature family I-V of the same device at different scales showing good on/off ratio and strong rectification viii

11 Figure 5.11: (a) Schematic device structure and layout of the back-gated GNR FET. (b) SEM image of the GNR with an inset showing a magnified view of the nanoribbon Figure 5.12: Transport properties of back-gated CVD GNR FET of width 12 nm. (a) Drain current vs. back-gate voltage and temperature. (b) Common-source transistor characteristics at 4 K Figure 5.13: (a) Differential conductance map of a 12 nm GNR FET as a function of V DS and V BG at 4 K. (b) Differential conductance and absolute drain current vs. drainto-source voltage at a back-gate bias of 50.5 V Figure 5.14: (a) Differential conductance di D /dv DS of a sub-10 nm GNR FET as a function of V DS and V GS at 4 K. The color bar is the exponent, log 10 (di DS /dv DS ) in -1. Transport gap of ~ 0.2 ev is observed. (b) Transfer characteristic of the same device as a function of temperature Figure 6.1: Doping effect of the high- top gate dielectric deposition in case of an exfoliated graphene FET on SiO 2. The FET has heavy p-type doping before high- deposition, the Dirac point is higher than +50 V. After 20 nm ALD Al 2 O 3 deposition the position of the Dirac point decreased by more than 100 V. It corresponds to more than cm -2 change in the carrier concentration at a given bias Figure 6.2: Ways to achieve p and n doping in the graphene channel. Remote charges can be either present in the oxide or induced by electric field Figure 6.3: Expected characteristics of a graphene p-n junction. (a) Band alignment of the n-side (left) and p-side (right) of the junction. E 0 is the intrinsic level. (b) Transfer characteristics as a function of a global gate V G. The cross sections are highlighting the following channel dopings: A: n+/n, B: n/i, C: n/p, D: i/p, E: p/p Figure 6.4: (a) Transfer characteristics of a double gated p-n junction GNR FET. (b) is the slice at constant V TG = -8.5 V. Although more detailed data is available for this device as a proof of the p-n channel the double minimum is highlighted. p/i/n denotes the current doping of the channel Figure 6.5: (a) Transfer characteristic of a side gated GNR FET at 0 V and +/- 5 V applied bias on the side gate. The applied bias dopes half of the channel which introduces a (hard to notice) 2 nd minimum. (b) SEM and (c) schematic of the device ix

12 Figure 6.6: Change of the carrier concentration in case of different oxide stacks. The dashed line shows the initial doping of the sample. None of them provide lower n-type doping concentration than the original doping of the sample. Further high- oxide deposition added extra doping. The table shows the data in detail corresponding to the different oxide stacks Figure 6.7: Change of the carrier concentration in case of HSQ+high- oxide stacks and the effect of RTA. The dashed line shows the initial doping of the sample. (a) HSQ+Al 2 O 3 oxide stack. The RTA continuously increases the doping. (b) HSQ+HfO 2 oxide stack. The highly polar HfO 2 heavily increases the n-type doping but the RTA continuously decreases it. The tables are showing the details of the process Figure 6.8: (a) Schematic of a p-n junction GNR FET which has HSQ on one half and SiO 2 on the other half of the channel. (b) The characteristic double minima can be clearly observed on the transfer curve. p/i/n denotes the current doping of the channel Figure 6.9: (a) Threshold voltage (V Dirac point ) shift as a function of e-beam dose. (b) Multiple minima exist in the transfer characteristics as a result of different doping in the two sides of the channel Figure 7.1: Summary of graphene properties obtained by various methods. * At moderate field; devices were not driven close to burn-down. Mobility calculated assuming 2D capacitor model for C ox and without subtracting R C Figure 7.2: Comparison of the spatial distribution of the carrier momentum in 2D and 1D graphene. In both cases carriers move with the Fermi velocity F, but the average velocity sat can be much higher in the 1D case Figure 7.3: The noise amplitude A N as a function of carrier density n for four types of graphene samples: (1) exfoliated graphene on SiO 2, (2) CVD graphene on SiO 2, (3) epitaxial graphene on SiC with HSQ/SiN top gate oxide and (4) epitaxial graphene on SiC with Al 2 O 3 top gate oxide Figure 8.1: (a) Schematic structure of the GNR TFET. (b) Band diagram showing both the OFF and the ON state. (c) Simulated transfer characteristics exhibiting sub-60 mv/decade subthreshold slope Figure 8.2: SEM micrograph of (a) a GNR heterojunction, (b) a graphene quantum dot and (c) a quantum dot chain x

13 ACKNOWLEDGMENTS I thank God first for the grace he gave me along the way towards this thesis. It is my great pleasure to express my gratitude to all those who supported me during my pursuit of a Ph.D. degree. I give my deepest gratitude to my advisor Dr. Debdeep Jena and my almost co-advisor Dr. Grace Xing, for their guidance, inspiration, and encouragement through the course of this research project. I also give my appreciation to the other two committee members - Dr. Wolfgang Porod and Dr. Gregory Snider. They gave me advice and instruction on this project, they treated me like one of their own students. I would like to thank Dr. Árpád Csurgay, his professional research attitude influenced me throughout my whole graduate study and his advises will guide me on the rest of my life. Also I thank Xiangning Luo, Chuanxin Lian and Wan Sik Hwang for working with me enthusiastically on this project. I thank Michelle Kelly, Nan Sun, Vladimir Protasenko, Tian Fang, Aniruddha Konar, Jai Verma, Guowang Li and Pei Zhao, for their cooperation on this project. I thank Keith Darr, Mike Young, Mark Richmond and Michael Thomas for their training on various equipments and keeping the lab running. Finally, I would like to give my appreciation to three most important people in my life, my wife, Zsófi, and my sons, Samu and Dani. Their patience, encouragement, and xi

14 love have continuously given me the courage to face the many challenges that arose in pursuit of my Ph.D. degree. This work was supported by the Semiconductor Research Corporation Nanoelectronics Research Initiative and the National Institute of Standards and Technology through the Midwest Institute for Nanoelectronics Discovery (MIND). xii

15 CHAPTER 1: INTRODUCTION 1.1 Motivation The 2010 Nobel Prize in Physics honored Andre K. Geim and Konstantin S. Novoselov, who succeeded in producing, isolating, identifying, and characterizing graphene [1]. Since the discovery in 2004 [2], graphene has become one of the most investigated materials amongst the scientific community and it is not by coincidence. The linear energy dispersion relation at low energies is a unique property among all known materials and it is an attractive one because it makes electron motion mimic the properties of photons. The practical consequence of this fact is the very high charge carrier mobility [3,4,5]. Infinitely large sheets of graphene are inherently two dimensional (2D) with zero bandgap. When patterned into nanoscale ribbons, a bandgap opens due to the lateral quantum confinement. The magnitude of the bandgap is inversely proportional to the ribbon width, thus the band gap becomes a lithographically designable parameter [6]. This even offers advantage over carbon nanotubes, which might have even higher mobility [7] and high saturation current density (4 A/mm, [8]) but chirality control and positioning are unresolved drawback for a decade. The high mobility, the high current carrying capacity [9,10,11], the 2D or 1D atomic structure and the compatibility with planar technology makes graphene an exciting and promising addition to silicon-based CMOS. The novel band structure holds 1

16 promise for as-yet unrealized devices that exploit the massless Dirac-fermion like linear energy dispersion of electrons in the material. The potential applications of graphene extend far beyond electronic devices. It is being touted as a material that will literally change our lives in the 21st century, like plastics did hundred years ago. Not only is graphene the thinnest (and lightest) possible material that is feasible, but it's also ~200 times stronger than steel and conducts both heat and electricity better than any material known to man at room temperature. Potential applications for the material include replacing carbon fibers in composite materials, to eventually aiding the production of lighter aircrafts and satellites or stronger wind turbines; embedding the material in plastics to enable them to conduct electricity or just to make them stiffer, stronger, lighter or leak-tight; increasing the efficiency of electric batteries or supercapacitors by use of graphene powder; graphene based optoelectronic components promise closing the terahertz gap [12]; transparent conductive coatings for solar cells and (touch-enabled) displays; stronger medical implants; better sports equipment; artificial membranes for separating liquids; or nanogaps in graphene sheets may potentially provide a new technique for rapid DNA sequencing. Since graphene is so light, it holds a high potential in nanoelectromechanical (NEMs) systems and components and can usher in vast improvements in the speed of, for example, NEMs RF resonators to GHz frequencies. Graphene can be a part of future meta-materials built from stacks of other 2D materials such as BN or MoS 2 [13,14]. Although digital electronic devices based on just graphene are definitely possible, as it is the topic of this thesis, but more probably graphene will only be one of the materials of the future transistor. The low bandgap and high current density in graphene 2

17 might make it more suitable for interconnects, while MoS 2 (E G = 1.7 ev) shows excellent transistor performance and BN (E G = 6 ev) could be the ultimate gate material (Figure 1.1). Figure 1.1: The role of graphene in future electronic circuits as interconnect or even as active element. All 2D semiconducting MoS 2 and insulating BN with GNRs can be used in a transparent few atomic layer transistor. These 2D materials have the inherent advantage of single layer nature with atomic smoothness, no dangling bonds or surface defects, high transparency and the possibility of easily controllable layer-by-layer growth. Such a device including back insulation, channel, gate oxide and interconnects is not thicker than about 5 nm. Besides, there are no clear obstacles for the sub-10 nm lateral scaling either. The future of graphene holds limitless possibilities into literally every corner of industry and manufacturing, and in the coming years it will likely become a commonplace substance, the way plastics are today. 1.2 Background Graphene is a single atomic layer of graphite. Its structure has been studied long ago and it was concluded that graphene is not thermodynamically stable in single layer form [15]. It is still true, but Novoselov et al. [2] found out that graphene can be stable when placed on a suitable substrate. Since its discovery, researchers have rapidly 3

18 developed methods to produce single-layer graphene on various substrates both conducting, and to a less extent, insulating. The linear energy dispersion relationship of graphene was well-known because the hexagonal carbon lattice structure is the building block of 0D (fullerenes), 1D (carbon nanotubes) and the 3D graphite lattice. The major paradigm shift since 2004 is that the massless Dirac-fermions predicted from the band structure are experimentally observable in table-top experiments at room temperature [16]. The lateral confinement of the 2D lattice into nearly 1D ribbons causes band gap opening, which opens the possibilities to exploit the electronic properties of graphene in semiconductor device applications. In addition to 1D patterning, bandgap opening is possible by applying a vertical electric field to break the symmetry in bilayer graphene [17]. Various types of graphene based field effect transistors have been demonstrated showing respectable modulation, high current drive, and high mobility [2,5,11] Production of graphene Single-layer graphene was first produced by a mechanical exfoliation technique. Starting with highly oriented pyrolytic graphite (HOPG), a sticky scotch -tape was used to peel-off a few layers of graphene. Since the graphite is sliced into two parts, each part has to be thinner than the original one. Repeating it several times produces thin flakes, which can be transferred to a (silicon) substrate. Single layer flakes can be identified by optical microscopy (Figure 1.2 (left)) [18] and can be verified by Raman measurements [19] or by atomic force microscope (AFM). A more scalable method to produce graphene is to grow it on a suitable planar surface using chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or by 4

19 the reduction of SiC [20,21,22]. These methods can now produce both multilayer and single-layer graphene on large-area substrates [Figure 1.2 (right)]. The clear advantage is that one can cover an entire wafer with graphene by such growth methods. The CVD technique is often performed on metal substrates (Cu, Ni, Ru) due to the underlying hexagonal symmetry of the lattice, which initiates graphene formation. The low solid solubility of carbon results in limited, few-layer growth [23]. These as-grown thin films on metal cannot be used in ordinary electronic applications due to the direct (electrical) contact with the underlying metal. However, it is possible to transfer the graphene from them to insulating substrates like silicon or quartz by etching the metal substrate away. Epitaxial growth on insulating SiC substrates is also possible. At high temperatures, the surface Si-C atoms start to dissociate, and Si is pumped away, leaving excess carbon on the surface, which reconstruct as a graphene layer [21,24]. It has now established that such epitaxial-graphene layers are identical to graphene obtained by other methods. multilayer graphene graphene SiO 2 /Si substrate SiC substrate Figure 1.2: (left) Example of an exfoliated graphene flake. There is a monolayer flake on the middle, double layer flake on the left and a multilayer flake on the right. (right) AFM micrograph of the epitaxially grown graphene surface on SiC. The graphene is atomically smooth; the steps are of the substrate. The image is 10 x 10 m, gray scale range: 20 nm. 5

20 There exist a few chemical methods to produce graphene as well, such as hydrazine reduction of graphite oxide [25], or by unzipping carbon nanotubes to produce graphene nanoribbons directly [26,27]. These methods do not have a clear technological benefit over the exfoliation technique or the other growth techniques described above State of the art in graphene FET performance When Novoselov et al. [2] first showed the existence of single layer graphene, they already extensively investigated the field effect behavior besides mobility and magnetoresistance. They fabricated back-gated Hall-bar structures, which were actually the first FETs demonstrated with graphene. Subsequent studies rapidly addressed issues central to FETs in the field of fabrication techniques [28,29], and modeling [30,31]. The most important first steps were the investigation of the visibility of graphene on SiO 2 [18] and the experimental verification of band gap engineering of graphene nanoribbons [6]. Field-effect transistors on epitaxially grown graphene have been demonstrated later, which showed low modulation due to the multilayer nature of such graphene at that time [32,33]. The quality of epitaxial graphene is rapidly improving and the realization of wafer-size monolayer graphene growth has already been achieved [21,24,34]. Graphene nanoribbon based FETs are opening the possibility for digital applications. The band gap in these devices allows turning the current off effectively. In an early report on the performance of GNR FETs, I ON /I OFF ratios of a few orders of magnitude were observed at low temperature [35]. The width dependence of the bandgap was confirmed by experiments too [6]. In case of chemically derived ultrathin ribbons, high on/off current ratio was achieved even at room temperature [36]. For 6

21 lithographically fabricated ribbons there are no reports of sub-15 nm ribbon widths [37,38,39], and none of them are top-gated devices. High-field transport characteristics of graphene based devices are surprisingly not well studied yet. Early simulations [40,41] predicted very clear drain current saturation at source-drain voltages as low as 0.1 V (~3 kv/cm). Experimentalists however had a difficult time to drive their 2D graphene FETs to clear saturation before breakdown and the necessary source-drain field was found to be kv/cm [10,11,42]. The lack of bandgap restricts the on/off ratios to about 10x and prohibits saturation. Even though a graphene FET can be operated in the pinch-off regime, increasing the source-drain voltage results in an ambipolar turn-on. The low modulation might be a bottleneck for digital applications, but is sufficient for certain high-speed analog applications. The first report of the small signal radio frequency (RF) performance of graphene FETs is very promising. A cutoff frequency of f T = 26 GHz was observed on exfoliated graphene for a L G = 150 nm device [43,44]. Comparable values were reported [45] and measured [46] for few layer epitaxial graphene FETs. Since then the continuous development resulted devices with intrinsic cutoff frequencies as high as 300 GHz [47] giving intrinsic f. T L G above 40 GHz. m, where L G is the gate length. Even extrinsic performance of the devices is in the 25 GHz. m range [48]. These values are more than four times higher than the same figure of merit for Si CMOS and even approach the bestreported values for InP HEMTs [49]. There is one more form of graphene which is interesting for device applications, and it is its bilayer. Two layers of AB stacked graphene does not behave as two single layer graphene on each other (like in case of direct AA stacking [50]), but it couples and 7

22 forms the so called bilayer graphene, which loses the property of linear dispersion relation near the Dirac point. However it has a very interesting new property, namely by applying a vertical electric field to the bilayer graphene the opening of a bandgap is induced due to the breaking of the symmetry [51]. Band gaps up to ~150 mev have been demonstrated in this way [17,52], but very high fields were necessary (E G 1.2 mev/v. V G (V)), which makes this method challenging for electronic applications in itself. However, it is likely the first time a field-tunable energy gap has ever been observed unambiguously in a crystal, and can possibly enable new functionalities in electronic and optical devices. 1.3 Aim of this work The aim of this chapter is to guide the reader on the recently explored ways of graphene based device fabrication and modeling through its challenges and accomplishments, and to identify some open problems and challenges. In the rest of the document, the work performed towards addressing the problems and challenges are described. The starting point is to describe the basic physics of an infinite two dimensional graphene sheet concentrating on device related properties (Chapter 2). Fabricating devices out of graphene involves patterning it to micron sized portions, but we can safely assume that it conserves the 2D nature above 100 nm due to the negligible bandgap at that width compared to the room temperature thermal energy of carriers. Besides the size, the materials in contact with graphene like the substrate, the contacts or the gate insulator strongly influence the properties of graphene itself. In Chapters 2 and 3, the 8

23 field effect, current drive, mobility, and the intrinsic carrier concentration of 2D graphene FETs are analyzed in detail by combining experiment with modeling. In Chapter 4, the quantum confinement effect in graphene nanoribbons is discussed. GNRs are very different in many aspects from 2D graphene, but most importantly they can have a substantial bandgap. Several device designs are explored and pursued experimentally to make ultrathin GNRs, and such GNRs with bandgaps are then explored as the channel of FETs. First, nm GNR FETs with ohmic contacts and sub-50 mev bandgap is discussed. According to the applied model used to explain the device operation 2D nature is still prominent in these devices, although they exhibit many orders of magnitude current modulation at cryogenic temperatures indicating the opening of bandgap. Improved fabrication processes allowed us to pattern sub-10 nm graphene channels exhibiting bandgap exceeding ev (Chapter 5). Even with the bandgap, the ambipolar ohmic contacts formed to 2D zero-gap regions results in Schottky-barrier (SB) contacts to the GNR channels, leading to SBFETs with low roomtemperature modulation due to unwanted thermionic emission. Various ways to dope graphene are explored and described in Chapter 6. Formation of p-n junctions is demonstrated using each technique. 2D graphene and GNR FETs were fabricated from exfoliated, epitaxial and CVD graphene. As a summary, the last Chapter compares the characteristics of similar devices based on differently produced graphene. The main goals of this work are to a) demonstrate wafer-scale production of GNR FETs with substantial bandgap, b) achieve doping and junction formation in the graphene channel, and finally 9

24 c) to fabricate tunneling field effect transistors (TFETs) based on graphene nanoribbons [53]. In this document the progress towards these goals along with the underlying theory and models are described. We demonstrate the fabrication and the measurements of gated sub-10 nm GNR FETs and p-n junctions, which exhibit tunneling-based operation at certain bias conditions. 10

25 CHAPTER 2: PROPERTIES OF 2D GRAPHENE 2.1 Electronic structure of the graphene lattice Graphene is a hexagonal lattice of carbon atoms in sp 2 hybridization. For any given carbon atom, there are three nearest neighbors, as shown in Figure 2.1. For a single, flat graphene sheet, symmetry forbids coupling of bands to bands that are well below and well above the Fermi energy. The bands are well represented as linear combinations of p z orbitals of the carbon atoms, where z is perpendicular to the plane. Two bands of p z states emerge due to the fact that graphene has two atoms per unit cell. There are two inequivalent sublattices, shown in Figure 2.1 labeled A and B, with the environments of the corresponding atoms being mirror images of one another [15]. It is convenient to choose a Bravais lattice with primitive lattice vectors a 1, a 2 given as a a a a1 3, 3, 2 3, 3, (2.1) 2 2 where a 1.42 Å is the nearest-neighbor C-C spacing. For an A-sublattice atom the three nearest neighbor vectors in real space are given by a a a 1 1, 3, 2 1, 3, 3 1, 0. (2.2) 2 2 The reciprocal lattice vectors b 1, b 2 defined by the condition a i. b j = 2 ij are then 11

26 b 4 4 b1 1, 3, 2 1, 3. (2.3) 3a 3a It is clear that the six points at the corners of the first Brillouin zone (Figure 2.2) fall into two groups of three which are equivalent, so we need to consider only two equivalent corners that we denote as K and K. Figure 2.1: Lattice of graphene. The primitive lattice vectors a 1,2 are defining the unit cell. There are two carbon atoms per unitcell, denoted by A and B. Also shown are the vectors to the first nearest neighbors of an A atom 1,2,3 used in the LCAO calculation. After defining the lattice structure we use a tight binding (TB) or linear combination of atomic orbitals (LCAO) method for calculating the energy bandstructure, which stands as the basis of all electronic (and optical) properties of graphene. A common approximation is to neglect the on-site overlap (p z ground state energy) and the overlap between wave functions centered at different atoms (i.e. the skeleton). The electrons populating the p z orbitals in the periodic lattice of carbon atoms can be described with the following wave function 12

27 ( r) C ( r r ), k kj j j (2.4) in which (r) is the wave function for free electron moving in the electric field of isolated atom and C kj are the Fourier coefficients. To construct periodic Bloch functions, let kj 1/ 2 ikrj C N e, where N is the number of atoms in the system. Thus, 1 ( ) ikr j k r e ( r rj). (2.5) N m The band structure is calculated by evaluating the eigenvalues of the Hamiltonian matrix for the k values. The Hamiltonian of the system is in the form Hˆ ( k ) ( r ) ( k ) ( r ), (2.6) k k where Hk ˆ ( ) is H ( k) H ( k) H21( k) H22( k) ˆ ( ) Hk (2.7) The diagonal matrix elements represent the p z orbital ground state energy and can be chosen as the reference point of the energy i.e. to zero. The off-diagonals are given by 1 ik ( rj rm) k H k e m H j, (2.8) N jm, where ( r r ). Using m rm rj connects the matrix element to m m k k e dv r H r e (2.9) ik m * ik m H ( m ) ( ) 0, m m and 13

28 * 0 dv ( r m) H ( r), (2.10) is the hopping parameter for the nearest neighbor. Its value for graphene is γ 0 ~2.8 ev. Plugging the coordinates of the nearest neighbors (Eq. (2.2)) into the expression yields a 3a a 3a ikxa ik ( ) x ik y ik x ik H k y 0 e e e, (2.11) or 3 H k e e k a 2 a ik x xa ik 2 12( ) cos y. (2.12) The eigenenergy of H(k) is specified by the secular equation ( k) H ( k) ˆ ( ) 12 ( k ) * 0. H12( k) ( k) H k (2.13) Eventually we get the energy dispersion (or bandstucture) of 2D graphene to be a a 3a (2.14) ( k) H12( k) 0 1 4cos ky 4cos ky cos kx. This relation (plotted in Figure 2.2) looks linear for low energies near the six corners (K or Dirac-points) of the two-dimensional hexagonal Brillouin zone. Let s call k = K + dk and examine this linearity by expanding the expression for H 12 (k) (Eq. (2.12)) around K (0,4 /3) 14

29 ik 3 xa 1 2 ka y H12( k) 0 1 ikxa 1 2 sin a 0 ikxa kya ( ikx k y ) (2.15) The Fermi velocity F, is defined as 3 a F m/s (2.16) If we had expanded around K we would have obtained the complex conjugate of Eq.(2.15). To determine the energy relation near the K point we can write the Hamiltonian in the form 0 kx iky Hˆ ˆ F F p, kx iky 0 (2.17) and the E-k relationship comes out in the form (2.18) 2 2 ( k) F k F kx ky. Due to this linear dispersion relation at low energies, electrons and holes near these six points behave like relativistic particles described by the Dirac equation for spin 1/2 particles. That is why the electrons and holes are called Dirac fermions, and the six corners of the Brillouin zone are called the Dirac points. The linear energy dispersion relation makes graphene quite different from most conventional three-dimensional semiconductors, which exhibit parabolic bands (energy is proportional to the square of the momentum) and a band gap. Intrinsic graphene can be thought of as a semi-metal, or a zero-gap semiconductor. 15

30 E(k) k y k x Figure 2.2: Energy bands of graphene. (left) Energy spectrum in units of 0 = 2.8 ev (nearest neighbor hopping energy) as a function of momentum k i. (right) Zoomed portion of the linear energy band near the Dirac point. Plot was made using Matlab. 2.2 Carrier statistics and mobility in graphene Experimental results from transport measurements show that exfoliated graphene has remarkably high electron mobility at room temperature, with reported values in excess of ~ cm 2 /V. s at n = cm -2 carrier concentration [3]. Scattering by acoustic phonons in graphene limits the low field room temperature to cm 2 /Vs at a carrier density of n ~ cm 2, which was experimentally achieved in suspended graphene [4]. However, for graphene in contact with oxides or dielectrics, scattering of electrons by optical phonons of the substrate dominates at room temperature. The intrinsic optical phonon energy in graphene is ħ op 160 mev, thus emission is not possible in the case of low energy transport. It has been shown that the surface optical (SO) phonon energy of common dielectrics is lower, in the mev range [54]. 16

31 Impurity scattering can be an important factor too, depending on the impurity concentration of the substrates. High-κ dielectics have lower energy SO modes thus the mobility has a lower limit. On the other hand the higher dielectric constant screens the impurity charges more effectively. The two competing effects renders the maximum achievable mobility to ~ cm 2 /Vs at room temperature and is more or less independent of the choice of the dielectric at n imp ~ cm -2 impurity concentration and at n ~ cm -2 charge density [54]. An exception to this trend is found when sp 2 -bounded boron-nitride (BN) is used as a substrate. Since BN has a very high phonon energy and cannot incorporate impurity charges due to the lack of out-of-plane bonds, the μ is generally higher, up to cm 2 /Vs [55]. The relation between the scattering rate 1/τ and mobility in semiconductors is μ = τ. q/m *, where q is the electron charge and m * is the effective mass. For graphene it is [56] q F, (2.19) n / n where ν F is the Fermi velocity and n is the carrier concentration, so μ is inversely proportional to 1/τ. Figure 2.3 shows the principal scattering mechanisms and their relative importance as a function of electron energy with respect to the Dirac point. At low energy either impurity scattering - or in case of a clean sample - SO phonon scattering are the most significant. If the accelerating field is high, electrons occupy higher energy states, and optical phonon emission is dominant in limiting mobility. 17

32 Figure 2.3: Scattering rates 1/τ vs energy in 2D graphene: T = 300 K, n imp = cm 2. The bar shows the relative rates at an energy of 0.6 ev [57]. For transport in graphene nanoribbons (GNRs), one more perturbation has to be taken into account, namely line edge roughness (LER) scattering [30]. Its importance is inferior compared to charged impurity scattering at room temperature. Assuming no impurities, LER scattering is more severe than acoustic phonon scattering only below GNR width of 4 nm to be a mobility limiting factor. Eq. (2.19) turns the attention towards an interesting fact, namely that the mobility is highly dependent on the carrier concentration in graphene, which is examined in detail in the following. Using the energy dispersion relation of graphene, which is conical at low energies (Eq. (2.18)) to determine the 2D density of states ( ( E) kd k /, DOS) it can be written as 18

33 gg v s ( E) E, (2.20) 2 F where g v = 2 is the valley degeneracy and g s = 2 is the spin degeneracy and F is the Fermi-velocity. Only some of these states are populated by carriers and it is defined by the Fermi-Dirac distribution at a given Fermi level E F : 1 f( E). (2.21) E E / F 1 e kt To find the electron density, the product of the Fermi-Dirac distribution and the DOS has to be integrated over the whole energy range n ( E) f ( E) de. (2.22) 0 The integral can be evaluated [31] if we introduce u = E/kT and = E F /kt 2 kt nor p 1 ( ), F 2 (2.23) j u where j ( ) 1/ ( j 1) duu /(1 e ) is the Fermi-Dirac integral with j = 1, Γ( ) 0 is the gamma function and the sign on is + for electrons and for holes. In the special case when the Fermi level is at 0 ev Eq. (2.23) simplifies to n i kt 6 F 2, (2.24) where n i is called the intrinsic carrier concentration. Unlike in case of materials with bandgaps, the intrinsic carrier concentration in graphene does not depend exponentially on temperature, but quadratically. This is a very interesting and unique 19

34 phenomena but it has not yet been observed because it requires samples with very low residual impurity concentration. Small or negligible temperature dependence of the Dirac point resistivity was observed in several cases [58,59,60], but probably because of the above mentioned reason this very little change was not carefully analyzed. To significantly decrease the impurity concentration, Farmer et al. [61] fabricated graphene devices on self-assembled monolayer (SAM) and they found the Dirac point current to be relatively constant over a wide range of temperatures. Wang et al. [62] fabricated graphene FETs on SAM layers also while Dean et al. [55] on BN both group observed the temperature dependent change of the Dirac point resistance indeed but they left the problem for further analysis. Another way to get rid of the effect of impurities is to suspend graphene. Multiple groups [63,64] made such devices and observed significant change in the Dirac point current. Although the data for different devices is not very consistent none of them concluded that the devices exhibit the expected n i T 2 dependence. Graphene grown on SiC offers an inherently clean substrate-graphene interface. This does not mean that the intrinsic properties can be easily benchmarked because some n-type doping is present usually due to dangling bonds in the underlying layers, and due to effective modulation doping of graphene from donors/acceptors in the underlying substrate. Jobst et al. [65] deposited thermally evaporated tetrafluoro-tetracyanoquinodimethane (F4-TCNQ) molecules to achieve minimal doping. They have observed a superlinear temperature dependence of the (close to) intrinsic carrier concentration n i but since they had only one such device careful analysis was not possible. 20

35 Our approach was to make devices with top gates thus the intrinsic carrier concentration could be examined if the devices are biased appropriately. Measurements of a similar device made by Tanabe et al. [66] were reported recently. Their experimental results are consistent with our measurements but their report lacks any investigation of the possible reasons for the observed phenomenon. To establish the connection between the measured device characteristics and the intrinsic parameters we have to understand and model the parasitic resistances and the capacitive control in detail, as reviewed later in this chapter. A key point in the argument the temperature dependence of the mobility has been investigated by independent measurements and models. We first describe the experimental procedure for the fabrication of 2D graphene FETs. 2.3 Experimental data and device model Field effect transistors were fabricated with epitaxial graphene channels. The epitaxial graphene was grown by our collaborators at the Naval Research Laboratories (NRL) [24]. The starting substrates were chemical-mechanical polished (CMP ed) semiinsulating Si-face 6H-SiC wafers obtained from II-VI Inc. The wafers were diced and chemical cleaning was performed on them prior to loading into an Aixtron hot-wall CVD reactor. The samples were hydrogen-etched at a 100 mbar pressure in hydrogen for 5-20 minutes at a temperature of 1600 C in order to remove polishing damage from the surface. At high vacuum conditions (10-5 mbar), the epitaxial graphene is formed in the temperature range of 1225 to 1700 C. AFM measurements confirmed graphene growth by the observation of 0.4 nm steps at the edge of the graphene layer, where the coverage was not perfect (Figure 2.4 (a) and (b)). Depending on the sample, Hall measurements 21

36 Intensity (a.u.) resulted in measured mobility in the cm 2 /Vs range while the carrier concentration was ~ cm -2. Raman measurements indicated predominantly single or double layer graphene coverage [19,67] based on the ratio of the 2D and G peaks (Figure 2.4 (c)). (a) Atomically smooth graphene (b) Atomically smooth graphene NO graphene NO graphene (c) G peak 2D peak Raman shift (cm -1 ) Figure 2.4: (a) AFM micrograph of an epitaxial graphene sample. The area is carefully selected to show parts without graphene. Complete graphene coverage is usual as shown in Figure 1.2 (b). The slice denoted in (a) is the cross section in (b), which shows 0.4 nm steps corresponding to a single layer of graphene. (c) Raman spectrum of the epitaxial graphene. An unprocessed epitaxial graphene sample on SiC was prepared by a focused ion beam (FIB) system for investigation with transmission electron microscope (TEM) to further clarify the structure of the as-grown samples. The TEM micrograph revealed mostly single layer graphene coverage along the 10 m specimen. Double layer coverage was observed at the step edges of the SiC. Based on the known lattice constant of the 6H-SiC (15.11 Å) the interlayer distance between the 0 th graphene layer (i.e. 22

37 surface reconstruction or buffer layer [68]) and the 1 st graphene layer was measured to be 3.27 Å, 2.5% less than expected, but within measurement accuracy. Figure 2.5: TEM micrograph of epitaxial graphene on SiC. The lattice constant of 6H-SiC is used as a calibration for the scale of the image. 0 th and 1 st graphene layers are identified. The interlayer distance is extended for several more periods to increase accuracy / 5 = 3.27 Å is the lattice constant c. The graphene was patterned by e-beam lithography and etched in O 2 plasma. Hydrogen silsesquioxane (HSQ), a negative-tone electron-beam resist, was used to form the conductive graphene channels. A 30 nm thick PECVD SiN film was used as the topgate insulator. E-beam evaporated Cr/Au source/drain contacts were then deposited to form FETs (Figure 2.6). 23

38 S graphene L SD L G G oxide D V D R TOTAL = R C + R A + R CH + R A + R C SiC Figure 2.6: (top) Optical image of a typical top-gated epitaxial graphene FET on SiC substrate. (bottom) Schematic cross section of the device along with the considered parasitic resistances besides the intrinsic resistance of the graphene channel R CH. To be able to examine the properties of graphene the parasitic resistances of the graphene FET has to be determined and properly extracted from the measurements. Beside FETs, transfer length measurement (TLM) patterns were fabricated to determine the contact resistance (R C ) and resistance of the access regions (R A ) based on the sheet resistance (R sh ) measurement. W = 10 m and 80 m wide patterns were on each of the 16 chips of the sample. The measurements of R C resulted in values spread over a broad range, but 75% of all measurements lay in the Ohm.mm range (Figure 2.7). The median is around R C ~ 1.25 Ohm.mm. R sh had a lower spread and its median is R sh ~ 900 Ohm/sq. These median values were used for device analysis. Based on [69], the contact resistance can be directly extracted from the transport measurements assuming a constant mobility model. This fitting method gives good agreement with the values acquired by TLM measurement. 24

39 Sheet resistance (ohm/sq) Contact resistance (ohm.mm) Sheet resistance of graphene (a) Epitaxial graphene on Si-face SiC Contact resistance 5 4 (b) 10um 80um Epitaxial graphene on Si-face SiC um 80um um Width 80um 0 10um Width 80um Figure 2.7: (a) The statistical distribution of the sheet resistance R sh and (b) the contact resistance R C. The middle line is the average; the squares contain 75% of all measurement and all the data lies in between the top and bottom marks. We use the model shown in Figure 2.6 to de-embed the effect of the parasitic resistances and extract the intrinsic graphene channel properties. A more involved device model will be discussed in Section 3.3 but at this point we keep the focus on other aspects by not going into the details more than necessary. In case of micron size devices and 300 nm or thinner oxide stacks, a 2D parallelplate model of the gate capacitance is a good approximation. The gate capacitance per unit area can be calculated based on the deposited oxide (or insulator) thickness and the dielectric constant of the material, C OX = OX /t OX and was verified by C-V measurement. Graphene is not a metal thus the charge accumulation in it can be limited in some cases by the available density of states, which is much lower than in the case of a metal. This is especially important when the Fermi level in graphene is near the Dirac point, where the DOS is the lowest (zero). The charge in the channel depends on the potential in the channel (V ch ), which is related to the gate voltage (V G ) through the relation 25

40 C ox Vch VG C ox C Q, (2.25) where C Q is the quantum capacitance [31] C Q q n p 2qkT qvch ln 2 2cosh. V kt ch 2 F (2.26) In Figure 2.8 the comparison of C Q and C OX is shown for the oxide stack with the highest capacitance (t ox = 15 nm Al 2 O 3 ) used in this work. The total capacitance of the gate C T is given by C T C C ox ox C Q C Q. (2.27) C Q C Q neglected C Q included (a) C ox C T t ox =15 nm Al 2 O 3 (b) t ox =15 nm Al 2 O 3 Figure 2.8: (a) The relation of the quantum capacitance C Q on 300 K and the oxide capacitance C OX of a graphene FET with 15 nm Al 2 O 3 gate. The total capacitance C T has little deviation from C OX. (b) The effect of C Q on the carrier concentration as a function of gate bias. One can observe that considering the C Q slightly lowers the total capacitance at high gate voltages, and near V G = 0 V (or the Dirac point), it has a greater effect. 26

41 Although at the Dirac point the deviation of C T from C ox is significant, it does not result in a high difference in the carrier concentration of the channel (see Figure 2.8 (right) at V G = 0 V). Neglecting C Q causes ~10% difference in the carrier concentration in case of 15 nm Al 2 O 3, 5% for 30 nm SiN x and 1.5% for 300 nm SiO Mobility in graphene It is well known that mobility is a function of carrier concentration in graphene and very high mobility values can be obtained only at very low carrier concentrations. Another source of confusion in the field is the method of mobility extraction from measurements. Here, we investigate the limitations and reliability of widely used experimental mobility evaluation methods. To do so, we compare the experimentally extracted mobilities by using different methods, and highlight the limitations of the various methods. This study also helps us obtain a reliable method to extract the carrier mobility at very low carrier concentrations, all the way to the Dirac point. We start with the equation for the drift current of a graphene FET J en F, (2.28) where n is the 2D carrier concentration, and F is the electric field along the channel. The conductivity is σ=j/f, and one can extract the mobility specifically for a 2D graphene field effect transistor geometry: ID LG 1 ID LG 1 CON, en V W en V W C ( V V ) DS DS OX GS 0 (2.29) where e is the electron charge, n is the 2D carrier concentration, L G is the gate length, W is the channel width, V DS is the source-drain bias, V GS is the gate bias and V 0 is 27

42 the threshold- or Dirac-point voltage. This definition of the mobility is inversely proportional to carrier concentration therefore it gives extremely high mobility values for low carrier concentrations. This can be called conductance based mobility ( CON ). We can also define a field-effect mobility ( FE ) as the change in the sheet conductivity of graphene due to carrier density modulation n as ne. (2.30) The expression can be modified to the form: FE LG gm e n W C V OX DS, (2.31) where g m = di D / dv GS is the transconductance. As opposed to CON the fieldeffect mobility FE goes to zero at the lowest carrier concentrations at the Dirac point, since the drain current reaches a minimum when the gate bias equals the Dirac point, and by definition g m = di D / dv GS = 0. By comparing the result of the two calculation methods (Figure 2.9) for the same FET transfer measurement, we can conclude that the two versions of mobility are close for carrier densities n > cm -2. However, by analyzing many devices, we see that CON is usually about twice as much as FE even at high carrier densities. It can be shown [70] that the two methods would give equivalent results in the limiting case when the source-drain current varies linearly with the gate voltage, i.e. if the mobility is not a function of the carrier concentration, which is true for graphene [31] only within a window of carrier concentrations [71]. 28

43 Exfoliated graphene on SiO 2/Si Figure 2.9: Calculated mobilities as a function of the carrier concentration of a back gated graphene FET. There is a significant deviation around n = 0 cm -2, but above n = cm -2 the difference is acceptable and the trend is similar. Now that we have a deep understanding on the resistive and capacitive components superimposed on the graphene channel, analyzing the intrinsic graphene properties becomes possible. First let s turn our attention to the observed discrepancy of the mobility. The key parameter for the problem is the intrinsic carrier concentration n i and its predicted temperature dependence (Eq. (2.24)), which will allow us to determine the mobility at the Dirac point Minimum conductivity in graphene The differentiating property of semiconductors compared to metals and insulators is the possibility to tune the conductance of the material by an external electric field via capacitive (gate-) coupling. In the experimentally realized FET structures the direct measurement of source-drain current I DS is possible as a function of the gate bias V G (Figure 2.10 (a)). 29

44 Epitaxial graphene on SiC T (a) T (b) Figure 2.10: (a) Source-drain current I DS as a function of the gate bias V G and temperature for a top-gated 2D graphene FET. (b) Comparison of the channel resistance R CH before (extrinsic) and after (intrinsic) the parasitic resistances were subtracted. Based on the model for parasitic resistances (Figure 2.6), we can extract the conductance of the graphene channel. In case of back-gated devices the access regions and even the contact regions are gated thus R A and R C are bias-dependent. In the case of top gated devices, R A and R C can be safely assumed to be constant. The intrinsic resistance compared to the extrinsic resistance of an epitaxial graphene FET at 77 K is shown in Figure 2.10 (b). The extrinsic on/off ratio of ~10x increases to ~30x for the intrinsic channel. Figure 2.11 shows the temperature dependence of the extracted intrinsic channel resistances. Two trends can be observed: first, the channel resistance increases with increasing temperature at the Dirac point. At high carrier concentrations, this trend is reversed. 30

45 T Figure 2.11: The intrinsic channel resistance R CH as a function of temperature. At the Dirac point the tendency is very pronounced. The temperature-dependence of the channel resistance at high carrier concentration is widely observed and studied in detail [72,73,74]. The reversal of the dependence of conductivity as a function of temperature observed here has been seen before, but no explanation exists [59,62]. Recently characteristics of an essentially equivalent device were published [66] further supporting the validity of our observations. In the following, we focus on the maximum resistance or in other words, the Diracpoint conductance of the graphene channel. As derived earlier, we expect the intrinsic carrier concentration n i in graphene to depend only on physical constants and on the square of the temperature (Eq. (2.24)). In order to determine n i from the measured resistance, we use the drift current equation for mobile carriers JD ne F, (2.32) 31

46 where n is the carrier concentration, e is the electron charge, is the carrier mobility and F = V DS /L G is the applied accelerating field and finally J D ID VDS. (2.33) W R W CH Epitaxial graphene on SiC Figure 2.12: The measured J D for various devices shows similar trend in some cases to the calculated current based on the expected (Eq. (2.24)) intrinsic carrier concentration n i (assuming = 1000 cm 2 /Vs). On the other hand the data for some devices significantly deviate from the trend. The comparison of J D and the Eq. (2.24) plotted against T 2 is shown in Figure For the calculation = 1000 cm 2 /Vs was used. In this plot of J D vs T 2, we expect a linear behavior, and the intrinsic graphene model predicts zero current as T 0. The line clearly does not pass through the origin; therefore, we have to revisit our model and notice that assuming perfectly clean graphene free of impurities is an oversimplification. Therefore, we introduce charged impurities into the model, and write the charge balance equation as 32

47 n n p N (2.34) 0 D, where N + D denotes the net positively charged impurities, and n 0 is the excess mobile carriers attracted by the impurities. Based on the measured transfer characteristic (Figure 2.10 (a)) we can notice that the slope of the current at different temperatures is not the same, which means that the mobility is temperature dependent unlike as we assumed in the model. The temperature and carrier concentration dependence of the field effect mobility FE is calculated by did LG 1 FE, dv W V C (2.35) GS DS ox where C ox = F/cm 2 is measured. The calculated FE is plotted in Figure 2.13 (a). (a) (b) Figure 2.13: The temperature dependence of the mobility (a) at n = cm -2 carrier concentration based on the transfer characteristics and Eq. (2.35) and (b) based on the Hall measurement of the SiC/graphene/HSQ system. The different symbols in (a) means different devices, while in (b) it denotes consecutive measurements. 33

48 To further characterize how the mobility depends on temperature a test sample for temperature dependent Hall measurement was prepared. The 0.5 x 0.5 cm epitaxial graphene sample was covered with HSQ to resemble the gate structure. Ti/Au contacts were also deposited at the corners and below room temperature indium soldering and copper wires were used to mount the sample to the measurement setup. A different probe was used above room temperature, which allowed direct contact of the tungsten pins to the contacts. Due to the change of the measurement system small discontinuity of the data is observable at 300 K (Figure 2.13 (b)). Both methods lead to about the same conclusion: above ~150 K T -1 trend of the mobility is observed, while below it tends to be constant. Now the temperature dependence of the mobility (T) can be handled as an experimental parameter. None of these methods provide the mobility at low carrier concentration, nor do they allow us to extrapolate to that case. Thus we use the high carrier concentration value FE (T), which is clearly different from the Dirac point mobility, but at this point we assume the Dirac point mobility to be the same as FE (T). The important part of this assumption is not the actual value of the mobility, but its temperature dependence. We calculate the intrinsic carrier concentration based on the Dirac-point current and on the measured temperature dependent mobility using I ( ) D,min T LG n p. e ( T) V W (2.36) FE DS 34

49 Figure 2.14: The calculated minimum carrier concentration based on the measurement compared to the intrinsic carrier concentration n i as a function of T 2. The measurements are separated into two graphs to help inspection. The interception of the fitting with the y axis provides the impurity concentration n 0, while from the slope the Dirac point mobility Dirac can be determined. The linear n i T 2 is clearly observable in Figure 2.14 or alternatively the same is shown in linear temperature scale in Figure 2.15, where the n i T 2 dependence shows up as a quadratic function. We can extract two key device parameters from the fitting of the data with the model. First, the intercept is the impurity concentration n 0 of the channel; second, the ratio of the slope to the slope of the model gives how much the measured high carrier concentration mobility FE (T) underestimates the so far unknown Dirac point mobility Dirac. 35

50 Figure 2.15: The intrinsic carrier concentration n i as a function of the temperature T in linear scale with second order polynomial fitting. 2.4 The Dirac point mobility The question raised is the value of mobility at low carrier concentrations, and more importantly, at the Dirac point. The temperature-dependence of the Dirac point current measured in epitaxial graphene as described in the previous section, and based on that the intrinsic carrier concentration n i was determined. Comparing the value of n i based on measurements and theoretical expectations, we determined the impurity concentration n 0 and the Dirac point mobility Dirac of individual devices. The Dirac was found to be around an order of magnitude higher than the mobility at high carrier concentration, where it is relatively constant. The Dirac point mobility Dirac as a function of temperature is shown in Figure 2.16 for various devices. In comparison with Figure 2.13 (a) one can observe a 3x to 20x increase. 36

51 Epitaxial graphene on SiC Figure 2.16: The Dirac point mobility as a function of temperature. The values are approximately an order of magnitude higher than the mobility at n = cm -2. A common practice in the field is to assume a constant mobility at all carrier concentrations [69], even though experimental findings don t support such a picture. Often, high mobility values are quoted at very low carrier concentrations. In suspended graphene devices, where the impurity concentration is very low, relatively constant mobility can be seen in some cases down to carrier concentrations as low as cm -2, but at the Dirac point, a sharp increase was observed [4]. This was attributed to the validity limit of the model used to calculate the mobility. But in light of our new experimental results of temperature-dependent conductivity at the Dirac point, we can provide a more structured picture of the Dirac point mobility. The mobility at the Dirac point is not the same as at other carrier concentrations, and can easily be an order of magnitude higher. Comparing the two mobility extraction methods described earlier, at the Dirac point CON seems to be more valid (see Figure 2.17). Although the mobility close to the Dirac point is not yet calculated but close to linear decrease is expected until 37

52 it merges the known branches of CON. Extending the model to a wider carrier concentration range is subject of proposed work. Epitaxial graphene on SiC Figure 2.17: The discrepancy of FE and CON at the Dirac point - solved. The Dirac point mobility Dirac is closer to CON, but finite. The dashed line is guide to the eye of the possible mobility at low carrier concentration. 38

53 CHAPTER 3: DEVICE APPLICATIONS OF 2D GRAPHENE Due to the ease of fabrication the first graphene transistors made were micron long and wide devices. Transport characteristics of such 2D graphene FETs will be discussed in the following section. The zero bandgap nature of single layer graphene limits the achievable current modulation of the channel; however in some applications it is not crucial. As an example, in Section 3.2 graphene transistors as RF amplifiers are discussed. It is found that the current density in 2D graphene devices is high: current densities in the A/mm range have been measured, comparable to Si-MOSFETs although not exceeding III-V Nitride HEMTs D graphene FETs Graphene offers advantages for interconnects due to high current carrying capacity despite its single layer nature [9,75]. Graphene is also being considered as a possible channel material for transistor technology. So far, graphene has been studied mostly at low biases, but for applications in practical devices, it is essential to investigate the high-field transport properties. High current drives were measured by pushing the devices up to breakdown. The saturation current density for many 2D graphene samples has been measured to be in the A/mm range. Gate modulation of the drain current is found to depend strongly on the channel length. 39

54 (a) (b) PR coating (c) SiO 2 graphene n++ Si n++ Si n++ Si (d) MMA/PMMA (e) Cr/Au (f) Ti/Au S D n++ Si n++ Si n++ Si G (g) cross view PMMA C6 (h) O 2 O 2 (i) top view n++ Si n++ Si S D Figure 3.1: Schematic of a back gated 2D graphene FET fabrication: (a) (c) back gate fabrication, (d) (f) contact metallization, (g) (h) channel etch. We first discuss 2D graphene FETs fabricated from exfoliated graphene and later we compare the results to graphene devices made from epitaxial graphene on SiC. Exfoliated graphene flakes on heavily n-type doped silicon wafers with t ox = 300 nm thick thermal oxide from Graphene Industries were used for the experiments. Single layer graphene flakes were identified by Raman spectroscopy (inset of Figure 3.2 (a)). The wafers were backside-metalized after oxide removal in HF to form back-gate contacts. E-beam evaporated Cr/Au (2/200 nm) was used to define the drain and source contacts, which were patterned by e-beam lithography. The source-drain separations ranged from L = 250 nm 8 μm. After metal deposition and lift-off, the samples were annealed in forming gas at ~650 K for ~2 hours to remove the e-beam resist residue [76]. The graphene flakes were then patterned by O 2 plasma reactive ion etch with PMMA masks to widths ranging from W = 1 10 μm. A summary of the process flow is shown in Figure 3.1. The SEM image (inset of Figure 3.2 (b)) shows a typical FET. High 40

55 current annealing [28] was performed to drive off impurities for some FETs to recover their intrinsic performance. The devices were measured using a semiconductor parameter analyzer in ambient environment and in vacuum, at room temperature and at 77 K. The drain currents of the FETs were first measured at a low bias of V DS = 20 mv, while the gate voltage was varied over a wide range. The gate leakage current was many orders of magnitude lower than the drain current. (a) (b) Figure 3.2: (a) I DS as a function of V G at V DS = 20 mv for shortchannel (0.5 μm) and long-channel (8 μm) back-gated graphene FETs. Inset (a) Raman spectrum of single layer graphene. Inset (b) Low field I-V curves of long-channel FETs with V G = -35 V, V G = +10 V. (b) I-V curves of a long-channel FETs. Inset is a SEM image of this FET. The scale bar is 1.5 μm. Figure 3.2 (a) shows the representative transfer characteristics of a long- and a short-channel FET. Over the same range of gate overdrives, the long channel FET was observed to exhibit higher gate modulation (~8x) than the short-channel FETs (~2x). The field-effect mobilities were calculated to be ~ cm 2 /V. s for long-channel FET and ~200 cm 2 /V. s for short-channel FET respectively. These characteristics remained similar at different pressures, as well as at lower temperature. 41

56 Recently, saturation of drain current at high source-drain biases has been reported, and theory of optical phonon emission limited saturation current has been proposed [10,42]. In particular, back- and top-gated 2D graphene FETs showed saturation current densities in the A/mm range as reported by Meric et al. [10]. In Figure 3.2 (b), the high bias characteristics of a back-gated FET (W/L = 1.75/4 μm) are shown. A saturation current of 1.38 A/mm is measured for this device. Saturation current densities in the A/mm range were measured on a number of devices. This is ~2x higher than the reported saturation current densities for dual-gate devices [42], indicating that the top-gate high-κ oxide lowers the current drive through graphene. The effective 2D carrier densities were in the cm -2 range, as estimated from the effective gate voltage. The ~ A/mm saturation current reported earlier has been attributed to substrate-induced optical phonon scattering. However the ~2x higher current drives measured here on SiO 2 substrates indicate that the lower current drives are due to the top gate high-κ oxide rather than the SiO 2 substrate. This conjecture is discussed in detail in [54]. Such current drives can be obtained in Si MOSFETs and III-V HEMTs, but only with a) high 2DEG densities (>10 13 cm -2 ), and/or b) very short channel lengths taking advantage of ballistic transport. Our measurements show that graphene FETs are able to achieve these high current densities without these criteria, implying that even higher current drives are possible when they are met in the future. For a rough comparison, a carbon nanotube with diameter ~2 nm and a saturation current ~25 μa has an effective current per the circumferential width ~4 A/mm [77], much higher than either graphene or other semiconductors. At high drain biases, the current saturates at more than 1 A/mm, 42

57 but with weak gate modulation. Graphene carries over the high current carrying capacity of carbon nanotubes, but the absence of an energy bandgap hampers the modulation of this high current density. Figure 3.3: Current density as a function of drain biases for FETs with different channel lengths varied from 0.5 μm to 8 μm. Clear loss of gate modulation is observed with the shrinking of the graphene channel length. V G = -38 V, V G = +9.5 V. The effective field is simply calculated by F=V DS /L. The dependence of high bias drain currents and their modulation efficiency with the back-gate is observed to depend strongly on the channel length of graphene. In Figure 3.3, the FET characteristics are shown for four different channel lengths, ranging from 0.5 to 8 m. Two features are observed a) for the same channel length, the gate modulation at higher drain biases is lower, as is expected from the saturation of the current, and b) for the same bias voltages (or fields), the gate modulation efficiency decreases sharply as the channel length reduces. As shown in Figure 3.3, the gate 43

58 modulation reduces from ~7 to ~1.4 as the source-drain separation is scaled from 8 m to 0.5 m. Due to the absence of a bandgap in graphene, charge exchange is expected at the metal-graphene S/D contacts owing to the difference in the work functions. Considering the work function of Cr (W Cr ~4.5 ev), and that of pristine graphene (W Gr ~4.5 ev) one would expect them to form a flat-band (or neutral ) contact without any charge transfer. However, recent calculations have shown that the necessary condition for the formation of a neutral contact with a metal (work function W M ) in intimate contact with graphene is W M -W gr ~0.9 ev [78]. Therefore, we expect that graphene region adjacent to the Cr contact pad is effectively doped with excess carriers. This excess charge region extends over an effective Debye length from each contact, and it results in S/D extension regions. When the S/D separation is smaller than twice the Debye length, the channel conductivity is controlled by the S/D contacts, and the back-gate gradually loses the capability to modulate the current, as is seen in the FET characteristics in Figure 3.3. To further corroborate the high current driving naturally occurring thin parallel strips of graphene were characterized. An SEM image of the device is shown in inset (a) of Figure 3.4. Inset (b) of the same figure shows the consecutive burnout of the strips at high bias conditions after reaching clear current saturation; the saturation current in each strip scaled to the widths is also shown as a function of an effective channel electric field (~V ds /L). Saturation current densities exceeding 1.0 A/mm are measured before burnout of the strips, and the current saturation is observed at effective channel fields of ~15-20 kv/cm [79]. After the burnout, the devices were re-examined, and the reported memory effect was observed (not shown), confirming such behavior [80,81]. 44

59 Figure 3.4: Consecutive breakdown of a naturally multi-ribbon device. The breakdown occurs at >20 kv/cm acceleration field following saturation at >1.0 A/mm current density. Inset (a) SEM image of the multi-ribbon device. The scale bar is 6 μm. Inset (b) the breakdown process without scaling the currents by the actual width. In conclusion, saturation current densities in the A/mm range have been measured in exfoliated 2D graphene FETs, comparable to Si-MOSFETs and III-V Nitride HEMTs. Contact-induced short channel effects cause a strong degradation of the gate modulation of the drain current, which should have implications on the scaling of graphene devices. The high current drives in graphene are achieved at far lower 2D carrier concentrations and longer channel lengths, implying that the current drives in graphene FETs is superior to conventional semiconductors. This can be a clear advantage for a number of applications, including those for RF amplifiers and circuits where the zero bandgap is not of the utmost concern. 45

60 3.2 Epitaxial graphene RF FETs on SiC for analog applications As mentioned before the lack of sufficient modulation is not a hindrance in some applications. The high carrier mobility naturally focuses our attention towards high frequency performance of graphene based devices. Gigahertz operation of exfoliated [43] and epitaxial [45] graphene FETs have been reported. Here we present the high frequency performance of graphene devices based on epitaxially grown graphene on SiC substrates. The measured f. T L G product of 8 GHz. μm and f max of 16 GHz is in very good agreement with previously reported values [45]. Surprisingly, in spite of the much lower electron mobility and transconductance, these FETs demonstrate remarkable small signal performance comparable to the small signal performance of higher mobility exfoliated graphene devices. Recently significant improvement was reported: device with intrinsic f. T L G = 40 GHz. μm [47,82], although extrinsic f T no higher than Ghz was ever achieved [83]. Epitaxial graphene FETs were fabricated on 2-3 layer graphene on Si-face 4H SiC. According to AFM and LEEM characterization and Raman measurements the graphene thickness is 1.9 layers in average over the wafer [21]. Graphene is patterned by optical lithography and etched it in O 2 plasma. Using the same resist-pattern the SiC is etched 100 nm deep in CF 4 plasma to facilitate the sticking of the metal contacts on the surface. Cr/Au source/drain contacts and e-beam evaporated Al 2 O 3 /Ti/Au top gate (t ox = 15 nm) have been deposited to form field effect transistors (FETs). For increased RF performance short gates were fabricated using e-beam lithography. The channel lengths of the devices range from 1-4 μm and the gate length is 1 2 μm in optically defined and nm in e-beam patterned devices. Standard ground-signal-ground 46

61 I D (ma) I D (A/mm) I ds ( A) transconductance g m ( S/mm) probing pads are lithographically realized for the gate and drain. Open structures were used to de-embed the signals of the parasitic pad-capacitance V DS = 1 V V G (V) (a) W = 80 m 1 L = 282 m 0 V G = 4 V V G = -1 V V DS (V) V DS = 20 mv V G (V) (b) L= 4 m W= 25 m L g = 2 m t ox = 15 nm Al 2 O 3 V G = 2 V V G = -1 V V DS (V) L= 4 m W= 25 m L G = 1 m t ox = 15 nm Al 2 O 3 V DS = 20 mv V G (V) (c) Figure 3.5: Output characteristics of a saturating large area graphene transistor (a) and the graphene transistor (b), which RF characteristic is shown in Figure 3.6. (c) Transconductance as a function of gate voltage at V DS = 20 mv. Hall measurements revealed μ ~ cm 2 /V. s throughout the sample showing smooth variation and better performance in the middle of the wafer. The DC output characteristics of the devices were linear up to 5 V and slightly sublinear above 10 V. The drain current had weak gate dependence as we swept the gate voltage between +/- 2.5 V. In the high source-drain bias range the gate modulation decreased indicating a non-reversible degradation mechanism by high electrical field. The transconductance of the devices varied between μs/mm, which is significantly lower than in case of exfoliated devices having the same gate length. For very long gate lengths, reasonable current modulation and current saturation was observed as shown in Figure 3.5 (a). However, with scaling of the gate length, the gate modulation and current saturation properties degraded substantially, indicating the need for improvement of material quality and gate material processing. In spite of the weak gate modulation, it is possible to envision usage of graphene FETs in low-noise amplifiers (LNAs) if RF performance 47

62 improves. In addition, single layers of almost transparent graphene may be transferred to flexible insulating substrates, which can offer low-cost high frequency performance. Small signal performance of devices with gate-lengths between 2 μm and 0.5 μm on epitaxially grown graphene were measured. The used bias-conditions for the FETs are V DS = 10 V and V GS = 2 V. A deembedded current gain cut-off frequency f T of 4.1 GHz for devices with 2 μm long gates was achieved (Figure 3.6 (a)). For a graphene FET with a 0.5 μm long gate an exceptional high power gain cut-off frequency f max of 16 GHz is demonstrated. (Figure 3.6 (b)). These preliminary rgiesults are very encouraging and demonstrate the potential of the epitaxially grown graphene devices for high-frequency applications. Indeed, as the quality of graphene on insulating substrates improved over time cut-off frequency higher than 100 GHz was demonstrated [47,82]. Moving from zero-bandgap single-layer 2D graphene to bilayer graphene or graphene nanostructures can enable controlled bandgaps. We present our efforts to date on the latter approach in the next Chapter. Figure 3.6: (a) Current gain as function of frequency for a graphene FET with 2 μm long gate. (b) f T and f max of a graphene transistor with 0.5 μm long ebeam-defined gate. 48

63 3.3 Wafer-scale 2D graphene FETs The compatibility of graphene with planar fabrication technology is often quoted as an advantage of graphene, even years ago, when only isolated exfoliated graphene flakes were available. As the graphene production technology advanced over the years 4 epitaxial graphene on SiC and 12 CVD graphene on oxidized Si became widely available. Exfoliated graphene is still considered to have superior material quality due to its single-crystal nature contrary to the multigrain structure of the grown graphenes. Moreover the high temperature growth causes ridge formation upon cooldown due to the mismatch in the thermal expansion of graphene and the substrate. (a) (b) Figure 3.7: Representative transfer (a) and output (b) characteristics of 2D epitaxial graphene FETs. Although directional dependence of the transport have been reported along with grain boundary resistance [84,85] major differences in the characteristics of 2D FETs haven t been observed yet. It is possible that the negative effects are balanced by other beneficial differences, or the devices might be smaller than the grain size. The observed 49

64 I DS ( A) I DS (A/mm) on/off ratio and mobility in 2D epitaxial graphene devices are usually smaller than in exfoliated graphene but minimum conductivity in epi-graphene is decreasing at low temperature unlike in exfoliated devices (Figure 3.7 (a)). The current density at high bias is higher for epitaxial graphene due to the better thermal conductance of the substrate (Figure 3.7 (b)). CVD graphene is grown on conductive Cu foils, thus transfer to insulating substrates is necessary before FET fabrication. The non-perfect growth with the transfer process results in micron sized-holes on the graphene, which might continue to peel off during processing. Despite these difficulties large area uniform graphene can be achieved as indicated by the 100x100 m Raman map shown in Figure 3.8 (a). Even though the yield of the good devices is not that high, similar performance to exfoliated graphene can be realized (Figure 3.8 (b) & (c)) (a) (b) (c) ~ 4500 cm 2 /Vs ~ 4000 cm 2 /Vs 5x V G = -30 V V G = 30 V V G = -20 V V G = 20 V V G = -10 V V G = 10 V V G = 0 V L= 8 m W= 2 m V t ox = 300 nm SiO G = 10 V 2 W = 2 m L = 8 m 1 V DS = 20 mv t ox = 300 nm SiO 2 n 0 ~ cm V BG (V) 0.1 pfet nfet V DS (V) Figure 3.8: (a) Raman map of the 2D peak intensity across a region of the transferred graphene, showing uniform intensity over large area. (b) Transfer characteristic of a 2D graphene FET transferred to Si/SiO 2 substrate. The device exhibit relatively high and symmetric mobility and 5 times modulation. The calculated impurity concentration is cm -2. (c) High-field family I-V curves showing both sub-linear and super-linear behavior, characteristic of a zero bandgap single layer graphene. 50

65 Though the substrate-graphene interaction is different and influential in epitaxial graphene compared to exfoliated and CVD graphene, the FET characteristics are similar. Neither the shape, nor the magnitude of the measured conductance are fundamentally different. This allows using models to describe the device operation independent of the origin of the graphene. 3.4 Long channel graphene FET model A model based on the work of Meric et al. [10] has been developed to explain the transistor characteristics of the 2D graphene and p-n channel GNR FETs [86]. Both topand back-gates can be considered based on the actual device parameters. The applied gate and source-drain voltages determine the carrier concentration in the channel according to the relation 2 CTG 0 CBG 0 n( x) n0 ( VTG VTG V ( x)) ( VBG VBG V ( x)), q q 2 (3.1) where x is the distance along the channel, V(x) is the potential in the channel due to the applied source-drain voltage, n 0 is the impurity concentration and V 0 G is the Dirac point shift. The gate length L G is assumed to be equal with the source-drain distance L for simplicity; however the model can be extended easily for arbitrary gate lengths. A schematic of the model is shown in Figure

66 Source Al 2 O 3 Top Gate SiO 2 Si substrate Back Gate GNR Drain C TG R C C BG R CH R C Figure 3.9: Schematic of the modeled device. The graphene channel is capacitively controlled by the gates. R C is assumed to be gate voltage independent. Two transport regimes can be distinguished based on the magnitude of the applied source-drain bias: low field transport and high field transport. In case of low field transport assuming that the carrier concentration is uniform along the channel is a good approximation. Eq. (3.1) simplifies to the form 2 CTG 0 CBG 0 n n0 ( VTG VTG ) ( VBG VBG ), q q 2 (3.2) and the transfer characteristics (I D vs V G ) can be calculated with the drift current equation introduced earlier (Eq. (2.20)). A schematic band diagram of this case is shown in Figure 3.10 (a). The main feature is that the channel is uniploar at low drain biases either n-tpye or p-type. 52

67 E F E 0 (a) E F E 0 (b) Figure 3.10: Schematic band diagram of a graphene channel between the source and the drain at small positive gate bias for the case of (a) low V DS and (b) high V DS. E F is the Fermi level and E 0 (=E C =E V ) is the charge neutrality point. We talk about high bias condition when the approximation of unipolar carrier concentration in the channel is not valid. Due to the zero bandgap in graphene the gate cannot impose a barrier to the conduction; it can only control the carrier concentration of the channel. In this regime the drain may influence the carrier concentration locally by injecting opposite type of carriers into the channel. It can cause partial depletion at the drain side, which shows up in the I D -V DS characteristic as a tendency to saturation [10,87]. If the bias is further increased the saturation is not maintained, but an ambipolar channel forms (Figure 3.10 (b)) and the drain current starts to increase again. The n-p front poses as a zero barrier tunnel junction. Detailed simulation of the characteristics 53

68 of this graphene tunnel junction was carried out in our group and showed that the resistance of the junction is negligible compared to the parasitic- and channel resistance, especially in case of GNRs [88]. The high-field transport in the graphene FET can be captured by a long channel FET model. The current in the channel can be expressed by J( x) qn( x) F( x), (3.3) where is the mobility and F(x) is the electric field along the channel. The I-V characteristics are obtained by forcing current continuity in a self-consistent electrostatic and transport model V DS W I( V ) DS q n( x) dv ( x), L (3.4) 0 where L is the channel length and W is the GNR width. Carrier drift velocity and mobility saturation is considered depending on the carrier concentration based on the work of Dorgan et al. [74] v sat op, (3.5) nx ( ) where op is the optical phonon wavelength of the dominant scattering phonons, which are surface optical phonons of the high- oxide [54]. And 0 V Lv 0 DS 1 sat 2. (3.6) 54

69 Finally the effect of contact resistances was included, which results the following model to be solved self-consistently: DS C D W q 0 n( x)dv(x) L RCID IV ( DS ), 2 1 ( V ( x) 2 R I ) / Lv ( x) 0 V R I DS C D sat (3.7) where n(x) is defined by Eq. (3.1) For simplicity, we assumed equal mobility and saturation velocity to describe both the electrons and holes. The model proved to be useful to describe the operation of back gated 2D graphene FETs [10,87]. It can give a good fit even for GNR transistors as shown in Figure The reason is in the lack of fundamental difference between the 2D graphene and a nm GNR, which has only mev bandgap. Not only the thermal energy of the carriers is in the same range as the bandgap, but compared to the applied source-drain field the current blocking capability of the channel is negligible. The model will be discussed in more detail in Section 4.3, when it is applied to double gated GNR FETs with a p-n junction designed into the channel. 55

70 Figure 3.11: Family I-V of a GNR FET compared with (a) long channel Si MOSFET model and (b) self-consistent GNR FET model. The long-channel traditional model is not capturing the ambipolar transport regime but predicts saturation instead. 56

71 CHAPTER 4: GRAPHENE NANORIBBONS: FUNDAMENTAL PROPERTIES Two-dimensional (2D) graphene sheets are nearly metallic, while ultrathin graphene nanoribbons (GNRs) can show semiconducting properties with the energy bandgap scaling inversely with the ribbon width [6]. The achievable energy bandgap, superior transport properties, and the planar manufacturability establish GNRs as promising cornerstones for the beyond Si CMOS technology [53,75]. Although sub-10 nm GNRs have been demonstrated by chemical approaches [27,36] the ability to form GNRs lithographically is important for the fabrication compatibility with the conventional planar integrated circuit (IC) manufacturing technology. One dimensional nanostructures of graphene such as graphene nanoribbons (GNRs), owing to a finite bandgap, can prove attractive even for digital electronics especially in the form of interband tunneling transistors [53], as they are capable of higher drive currents than other material systems. First we review the physics, which is responsible for the band structure of graphene nanostructures. Then the fabrication of graphene nanoribbons is described and the quantum confinement in nanoscale ribbons is confirmed. Later in this chapter (in Section 4.3) the transport properties of p-n junctions formed in GNR FETs are reported. The observed unique current-voltage characteristic of the double gated GNR FETs with a lateral p-n junction as the channel is explained by a field-effect model. Due to the lack of sufficiently large band-gap in the 30 nm wide GNR the device still cannot be turned off completely at high source-drain bias, but rectification 57

72 is achieved. The results suggest that the fabrication of tunneling FETs made out of graphene is possible and their characteristics may meet the expectations [53] D quantum confinement in graphene nanoribbons The band structure of armchair graphene nanoribbons can be derived if we consider that the electron wave vector in the y direction is quantized by hard-wall boundary conditions to be k y = nπ/3w (n = ±1, ±2, ±4, ±5 ) [89,90] and the energy dispersion relation at low k values (Eq. (2.18)) for the nth sub-band becomes 2 2 n ( kx, n) h F kx, (4.1) 3W indicating that the conduction band (n > 0) and valence band (n < 0) split into a number of 1D sub-bands. The DOS for the nth sub-band is given by GNR 2 F 2 2 n, (4.2) where n F n neg / 2. (4.3) 3W Adding this up for all sub-band leads to the total DOS, which can be used to calculate the carrier concentration (Eq. (2.22)). 2 2 u EF / kt F n / ( / ) 1 n kt u e n kt (4.4) 2kT u du n 58

73 Figure 4.1 is the plot of the 2D carrier concentration (n 2D = n 1D /W) for several ribbon widths on room temperature. The contribution of the individual sub-bands can be observed for the 2 nm ribbon. Though narrow GNRs exhibit large charge modulation due to the existence of a gap, they become similar to 2D graphene sheets when the Fermi level is deep inside the bands. As the width increases the intrinsic carrier concentration quickly increases to the value seen in 2D graphene. It implies that in a 2 nm GNR FET with perfect ohmic contacts many orders of magnitude room temperature current modulation can be achieved [36], but in a 10 nm GNR FET this modulation drops to the around 100x theoretical maximum already. (a) (b) Figure 4.1: The carrier concentration of GNRs with various widths as a function of the channel potential at room temperature in logarithmic (left) and in linear (right) scale. The sub-band separation (Eq. (4.3)) defines the bandgap of a GNR too. Consequently the bandgap as the function of the GNR width is E G 2 h F 3W 1.38 ev. W (nm) (4.5) 59

74 As indicated earlier, to have a lithographically designable parameter (W) with strong influence on the bandgap is very important from a device physics standpoint. It is not only allows us to fabricate graphene based digital switches or offers tremendous potential in optical applications, but also creates a completely new paradigm in bandgap engineering. This in-plane or lateral band-gap engineering means that device parameters such as on/off ratio or switching speed can be tailored within a chip without integrating different materials. FETs, p-n junctions, interconnects, digital- or analog transistors can be fabricated using the same material: 2D graphene or GNRs of different widths. Figure 4.2: Band gap versus GNR width: theory and available experimental data compared. As a reference the bandgap of a semiconducting carbon nanotube (CNT) E G ~ 0.9 ev/ d (nm) [91] is included. A plot of the expected bandgap versus the GNR width is shown in Figure 4.2 along with experimental data for GNRs and the band gap trend of semiconducting carbon nanotubes (CNTs). First we should note that the experimental results align quite well with predictions. Second, the bandgap of a GNR of a given width is 50% higher than the 60

75 bandgap of a CNT with the same diameter. However, while making sub-10 nm GNRs is very challenging, CNTs with the diameter of 1 2 nm is quite common. The quantum confinement in the quasi-1d GNR channel creates discrete sub-band energy levels, which are filled by carriers in sequence as the gate voltage increases. As a result, staircase-like features are expected in the transfer curve. In Eq. (4.3) we practically defined the sub-band separation of the 1D GNR channel ΔE = ΔE n+1 - ΔE n. At zero temperature, only the energy levels below the Fermi level E F populated with electrons in the conduction band, or those above E F populated with holes in the valence band, contribute to the conductance. Each 1D energy level (or mode) has a finite transmission probability. The overall device conductance at a finite temperature is the summation of all the available conducting modes, and is described by the well-known Landauer formula: 2 2e i i f G t ( E) de, h E (4.6) where t i is the transmission probability of the i-th mode and f is the Fermi-Dirac statistics. Sub-band formation in 30 nm wide GNRs has been observed at low electric fields showing the sub-band energy spacing ( E) around 50 mev [92]. A larger E is expected in thinner GNRs. However, a smaller E was found in the 20 nm wide GNRs reported here. A GNR band structure equation is used to explain the observation taking into account the edge roughness, ribbon width fluctuation, and crystal orientation mixture. Besides, the carrier mean free path is estimated from the transmission probability extracted by fitting the experimental data with Landauer formula. At high electric fields, 61

76 the current-carrying capacity of 1D semiconductors is determined by the longitudinal optical (LO) phonon energy in the limit of ultrafast electron-optical phonon interaction and diffusive transport [93]. Owing to the large LO phonon energy (~160 mev), GNRs are expected to be able to exhibit large saturation current while at the same time providing as-designed planar patterning which is currently not achievable with carbon nanotubes (CNTs). Field effect transistors fabricated on the GNRs reported here show current saturation tendency with the maximum current density reaching 2 A/mm at high electric fields (75 kv/cm). 4.2 GNR fabrication and carrier transport Hydrogen silsesquioxane (HSQ) is widely utilized as the etching mask to fabricate GNRs owing to its high resolution in e-beam lithography (EBL) [6,35,94]. HSQ can be removed by buffered hydrofluoric (BHF) acid after the GNR formation. However, the normally used SiO 2 substrate supporting exfoliated graphene is also etched by BHF, resulting in partially suspended or damaged GNRs. This is undesirable for uniform GNR channel modulation by the back-gate through SiO 2. Alternative etch mask technologies should be explored to keep the SiO 2 substrate unaffected. In this part of the work, we present lithographically patterned GNR using ultrathin Al metal line masks, followed by O 2 plasma etching. GNRs as thin as 20 nm have been achieved using this technique. The technique allows scaling down to thinner GNRs in the future by shrinking the Al mask using isotropic (wet) etch. GNRs were fabricated on exfoliated graphene flakes on SiO 2 /Si. The oxide thickness is 300 nm and the Si substrate is heavily doped n-type. Al metal masks were patterned by EBL and e-beam deposition. The exposed graphene was removed by O 2 62

77 plasma etching and the metal masks were removed by Al etchant. GNRs connected to two 2D graphene sheets were thus achieved. Figure 4.3 (a) shows the SEM images of a 29 nm wide Al strip mask (top) and a 20 nm wide GNR (bottom). The fact that the obtained GNR is thinner than the Al mask indicates the effect of lateral etching in O 2 plasma, which suggests that the metal mask etching technique can be potentially used to achieve sub-10 nm GNRs by shrinking the Al line width and modifying the plasma etching parameters. Cr/Au was e-beam deposited as source (drain) contacts on the 2D graphene areas to reduce the contact resistance. Al/Au was used as the back-gate contact. Figure 4.3 (b) shows the device structures. The length of GNRs in this work is 2 µm. Current-voltage (I-V) measurements were performed in vacuum (~10-6 Torr) with the temperature ranging from 4.2 K to 300 K. Figure 4.3: (a) SEM image of an Al strip (top) and a GNR (bottom) formed using the Al strip as etching mask. (b) Device structure and layout. The temperature dependent transfer characteristics of GNRs at V DS = 20 mv are shown in Figure 4.4 (a). It is clearly seen that the minimum current decreases with 63

78 decreasing temperature while the maximum current (due to the hole conduction) remains almost unchanged. As a result, the back-gate modulation increases from ~12 at room temperature to >10 6 at 4.2 K, indicating the formation of energy bandgap. The positive Dirac point indicates the presence of holes, which can be induced by negatively charged impurities, at zero gate bias. It is worth noting that the transfer curve does not show the symmetric V shape, with the hole conduction much stronger than the electron conduction, a phenomenon often seen in GNRs [35,95]. This is often attributed to surface impurities based on the fact that surface passivation by Al 2 O 3 grown by atomic layer deposition (ALD) was found to be able to improve the electron conduction (see Figure 4.9 later). Further investigation pointed towards the role of the contact metal, which turned out to play an important role in the symmetry of the electron- and hole branches. Our simulations showed (Chapter 2.4 in [11]) that depending on the work function of the metal states are induced, which can either enhance conduction by lowering the contact resistance or act as a barrier. Quantized conductance was indeed observed in patterned GNRs. The conductance quantization was seen in different GNR devices and Figure 4.4 (b) shows a typical transfer curve measured at 30 K plotted in the linear scale exhibiting conductance plateaus with roughly equal spacing. For GNRs with W = 20 nm, ΔE is calculated to be ~32 mev. The conductance modulation by the back gate is about 200x at this temperature. The nearly equal spacing of the plateaus shown in Figure 4.4 (b) reveals that each conduction mode should have similar transmission probability. 64

79 (a) (b) Figure 4.4: (a) Temperature-dependent transfer characteristics at 20 mv drain bias. (b) Typical transfer curve measured at 30 K showing conductance plateaus. To analyze the measured conductance quantization (Figure 4.4) using Landauer formula (Eq. (4.6)), the back-gate voltage needs to be correlated with the Fermi energy. The link between them is the carrier density in the channel: C V V E (4.7) G( BG Dirac ) F / F, where C G is effective gate capacitance per area (F/cm 2 ). This relation holds strictly in the limit of a large number of occupied sub-bands. Both sides of the above equation give the carrier sheet density (cm -2 ) in the GNR channel [31]. The experimental data were fitted using Eq. (4.6), with ΔE, t, and C G as adjustable parameters. Excellent agreement was achieved as shown in Figure 4.5 (a). The obtained sub-band energy separation from the fitting is 28 mev. Perfect armchair GNRs should have quantized energy levels separated by πħν F / 3W (Eq. (4.5)), which is 32 mev for W = 20 nm, or two times of that value, depending on the index numbers of the two adjacent sub-bands. As a 65

80 result, ΔE of 34 mev or 68 mev is expected to occur in cycle for armchair GNRs with W = 20 nm. However, Figure 4.5 (a) shows nearly equal energy spacing between two close plateaus and the extracted ΔE is smaller than predicted. The discrepancy could be due to the likely existence of a mixture of both armchair and zigzag orientations in GNRs. The presence of zigzag edges can introduce extra allowed sub-band energies with n = ±3, ±6,, resulting in quasiequally spaced (in energy) conductance plateaus. Besides, the fabricated GNRs have rough edges, as shown in Figure 4.3 (a), causing edge states and width variation which perturb the real band structure from the ideal case. (a) (b) Figure 4.5: (a) Fitting of the experimental data using Landauer formula. (b) Simulated gate capacitance using COMSOL. The extracted C g is μf/cm 2, different from the capacitance of the 300 nm SiO 2 insulating layer (0.012 μf/cm 2 ). This is not surprising since the parallel plate capacitor model does not apply in this case considering the ultra-small GNR width. Figure 4.5 (b) plots the gate capacitance simulated using COMSOL software package. Quantum capacitance was neglected due to the thick oxide layer. The simulated C g for 66

81 W = 20 nm is μf/cm 2, larger than μf/cm 2. In the simulation, the potential was assumed to be uniform along the ribbon width direction. However, the GNR edge states could cause electrostatics perturbation, reducing the effective gate capacitance [96]. The average transmission probability is t ~ 0.02, similar to that reported in [92]. The very small t can be explained by the scattering due to GNR edge/bulk disorder which can severely suppress the conductance causing G much smaller than 2e 2 /h [97]. Since the field in the GNR channel is relatively low (100 V/cm), the carrier mean free path λ can be estimated by t = λ / (λ + L) [98], where L is the GNR channel length, giving λ = 40 nm. Compared with purified CNTs which can have reaching a few microns, lithographically fabricated GNRs suffer from severe scattering by edge/bulk disorder and impurities either at the surface or in the substrate or both. Figure 4.6 (a) shows the high field (corresponding to 30 kv/cm at V DS = 6 V) family I-Vs measured at 77 K. The source and drain electrodes were found to be exchangeable as can be seen from the symmetric I-Vs in the first and third quadrant. This is not unexpected since the back gate controls the whole GNR channel universally. The inset shows I-Vs measured at 4.2 K. The drain current exhibits tendency to saturate at high drain bias and the maximum current density is ~2 A/mm (W = 30 nm) at V DS = 15 V (equivalent electric field: 75 kv/cm), indicating high current drive capability of GNRs. At high electric field, the energy bandwidth of current carrying electrons/holes is limited by the LO phonon energy ħω LO in the limit of ultrafast LO phonon scattering and diffusive transport. The saturation current carried by one sub-band is 2eω LO /2π ~12 μa for GNRs [93]. Therefore, five sub-bands in the valence band contribute to the total saturation current (2 A/mm corresponding to 60 μa for W = 30 nm) as sketched in 67

82 Figure 4.6 (b), where E FR and E FL are Fermi energies for carriers moving right and left respectively. E F0 is the Fermi energy at equilibrium. (a) (b) Figure 4.6: (a) High field family I-Vs measured at 77 K and 4.2 K (inset). (b) Sketch of sub-band filling at the current saturation regime. 4.3 Exfoliated GNR FETs with lateral p-n junction The back gated GNR transistors described above were processed further Al 2 O 3 /Ti/Au as top gate (t ox = 30 nm) was deposited to form double gated FETs. 1 nm e-beam deposited Al was used as seed layer for the ALD deposited Al 2 O 3 [69]. The channel length of the fabricated devices is 2 m and the length of the top gate electrode is about 1 m, covering half of the channel. The SEM image in Figure 4.7 (a) shows a typical GNR FET and a schematic cross section can be seen in Figure 4.7 (b). High current annealing [28] was performed to drive off impurities for some FETs to recover their intrinsic performance. The devices 68

83 were measured using a semiconductor parameter analyzer in ambient environment and in vacuum (5x10-5 Torr), at room temperature at 77 K and at 4 K. (a) Drain (b) Source Top Gate Al 2 O 3 Drain GNR SiO 2 Si substrate Back Gate GNR Gate C TG Source 500 nm R C R CH1 C BG R CH2 C BG R C Figure 4.7: (a) SEM micrograph of GNR FETs. Half of the channels are top-gated, while the whole device is back-gated. The channel length is 2 m, the gate width is 1 m. The width of the GNR is 30 nm. (b) Device schematics and wiring diagram of the device model showing the critical resistances and the influence of the gates on the two parts of the channel. In this section the measurements of a single device with 30 nm GNR width at room temperature and on 4 K is presented. It is found that at high applied source drain voltage the temperature has very little effect on the device performance, namely at cryogenic temperatures the high-field modulation is only ~10% more. Many similar devices were fabricated and similar characteristics are observed in all cases. Figure 4.8 (a) and (b) shows the source-drain conductance at V DS = 20 mv and at V DS = 1 V respectively as a function of the top-gate and the back-gate. The back-gate capacitance is ~11 nf/cm 2 assuming =3.9 and the top gate capacitance is 209 nf/cm 2 calculated based on the measurement of the minimum conductance (Dirac) point as shown in Figure 4.8 (b). The Dirac point is defined by the ratio of the applied voltages on both gates, the slope defining the value of C top /C back is ~19. From either a constant 69

84 0 0 back-gate or constant top-gate slice we can determine V TG = -5V and V BG = -45V, indicating strong n-type doping. While the devices before the top gate deposition were slightly p-type doped we can conclude that the strong n-doping is due to trapped charges in the top gate oxide and other impurities on the graphene oxide interface. A comparison of the transfer characteristics before and after the top gate oxide deposition can be seen in Figure 4.9 (a) and (b). (a) (b) Figure 4.8: (a) Conductance steps at 4.2 K at low source-drain voltage (linear scale); (b) At higher bias (V DS = 1 V) the modulation is smaller. This high bias conductance is not influenced by the temperature; room temperature measurement yields the same result. Temperature dependent measurements of the off state conductance have confirmed band-gap opening of >26 mev depending on GNR widths, and result in 20x and 10 3 x modulation at room temperature and 4 K, respectively, by varying the top gate potential between +/- 5 V (Figure 4.9). The quantized conductance at low temperature also gives us a tool to extract the value of the GNR bandgap [92,99]. Details of these measurements and modeling are detailed in the previous section. 70

85 I DS ( A) I DS ( A) The source and drain contacts are deposited on the large 2D graphene region to ensure low contact resistance. The 2D graphene has no bandgap so the Cr/Au metal can form good ohmic contacts easily. The back-gate may vary the carrier concentration of the graphene at the contacts, but due to its large size it will always have much lower resistance than the GNR channel and will always supply the channel with high number of carriers (R C 10 2 Ω, R channel 10 5 Ω) K (a) 10 T= 4 K (b) K 30 K 15 K 4 k V DS = 20 mv 10-5 V DS = 20 mv 10-6 L = 2 m W = 30 nm 10-6 L = 2 m W = 30 nm t ox = 300 nm SiO 2 t ox = 30 nm Al 2 O V BG (V) V TG (V) Figure 4.9: Comparison of the transfer characteristics (a) before and (b) after the top gate oxide deposition. The initially p-doped device shifted to n-doped. The I ON /I OFF ratio decreased by several orders of magnitude. (a) shows the temperature dependence of I DS, which served as the basis of the bandgap extraction. Figure 4.10 (a), (b) and (c) shows the measured I DS for different top gate voltages at V back = -70 V, 0 V and +70 V respectively. To understand the device operation we have to examine the device structure in detail. 71

86 I DS ( A) I DS ( A) I DS ( A) I DS ( A) I DS ( A) I DS ( A) 20 VBG =-70V V TG =-10V -5 V TG =-7V V TG =-4V -10 V TG =-2V -15 V TG =+1V V TG =+5V V DS (V) 25 V 20 BG =0V V TG =-10V -5 V TG =-7V -10 V TG =-4V -15 V TG =-2V V -20 TG =+1V V TG =+5V V DS (V) 30 V 25 BG =+70V (a) (b) (c) V -5 TG =-10V V TG =-7V -10 V TG =-4V -15 V TG =-2V -20 V TG =+1V -25 V TG =+5V V DS (V) Figure 4.10: Measured room temperature I DS versus V DS at -70 V (a), 0 V (b) and +70 V (c) back gate bias. The channel of the devices can be separated into two distinct regions: one having back-gate only and the other having both top- and back gates. The model introduced in Section 3.3 is used to explain the transistor characteristics of the p-n channel GNR FET. The field effect model was applied to both side of the junction separately. A schematic of the model tailored to this device structure is shown in Figure 4.7 (b). The current continuity in the self-consistent electrostatic and transport model was forced on the two part of the channel in the same time V BG =-70V V BG =0V 25 V BG =+70V (a) (b) (c) 0 0 V TG =-10V V TG =-10V V V TG =-7V -5-5 TG =-10V V TG =-7V V -10 TG =-7V V TG =-4V -10 V TG =-4V V TG =-4V -15 V TG =-1V -15 V TG =-1V V TG =-1V -20 V TG =-+2V V -20 TG =-+2V V TG =-+2V -25 V TG =-+5V V TG =-+5V V TG =-+5V V DS (V) V DS (V) V DS (V) Figure 4.11: Simulated device characteristic at the same bias conditions as the device shown in Figure I DS versus V DS at - 70 V (a), 0 V (b) and +70 V (c) back gate bias. 72

87 The solution not only provides the I-V characteristics of the device but detailed information about the carrier concentration under various bias conditions. Figure 4.10 and Figure 4.11 demonstrate the experimental and modeling data, showing close agreement. As input parameters in the model we used mobility of 300 cm 2 /Vs, a minimum carrier density of cm -2 and source-drain series resistance of 0.5. mm. The saturation of current at high positive bias is caused by depletion of the carriers even in those cases when the gate biases set a high initial carrier concentration. At high negative drain bias on the other hand lack of saturation is observed. This is because the drain bias in this case further increases the carrier concentration instead of depleting. Depending on the gate bias conditions the flattening of the current occurs at different applied source-drain bias. If V BG = -70 V ((a) in Figure 4.10 and Figure 4.11) as V TG increases one can see that plateau of the I DS occurs at higher and higher positive bias. At positive V TG pinch-off occurs at V DS =5 V only. At more positive back gate biases ((b) & (c) in Figure 4.10 and Figure 4.11) the plateauing of the current occurs at highly negative top-gate biases only. At sufficiently large V DS values, the output characteristics for different V TG values may cross, leading to a zero or even negative transconductance, which means that the gate has effectively lost control of the current. Superlinear current increase is caused together by the sharp increase of carrier concentration close to the Dirac point and the increase of the accelerating field. One of our group members (Tian Fang, [88]) performed tight binding simulation on the (zero gap) p-n junction graphene channel allowing tunneling besides thermal currents. The tunneling probability in 2D graphene is calculated by WKB approximation. The observed high tunneling current at reversed bias is the result of the low tunneling 73

88 barrier. It was found that the current density is practically limited by the carrier concentration along the channel and the velocity of carriers. At forward bias thermal emission current is responsible for the exponential increase of the current. In real devices this exponential increase, along with the reverse bias tunnel current, is limited by the contact and channel resistances. The simulation was performed on zero bandgap graphene but shows exceptional agreement with the measurement results at similar bias conditions (Figure 4.10 (c) at V TG = -10 V for example). In case of GNRs with higher bandgap the suppression of the current is expected if V DS < E G /2 as will be shown later. (a) Figure 4.12: (a) Simulated intrinsic energy level E 0 along the graphene channel in case of three representative bias conditions. (b) I-V characteristic of the tunnel junction. Figures adopted from [88]. In conclusion, p-n junction in GNR FETs has been experimentally demonstrated. The analysis of the device operation shows that sublinear and superlinear features observed in the I-V characteristics are part of the expected operation of the graphene p-n junction. The p-n junction channels are practically transparent to interband tunneling of carriers [88] due to the small bandgap and high applied bias but offer an exciting novel 74

89 structure for configuring and designing device characteristics with various functionalities [86]. 75

90 CHAPTER 5: WAFER-SCALE FABRICATION AND CHARACTERIZATION OF GNR FETS Creation of a bandgap, by quantum confinement of the carriers in patterned nanometer size graphene ribbons was demonstrated in the earlier chapter, but continues to be a significant technical challenge. GNRs with width W nm have a bandgap E g ~1.38/W ev (Eq. (4.5)), implying that sub-10 nm wide ribbons can enable room temperature operation of GNRs as traditional semiconductors, but with ultimate vertical scaling, and still take advantage of high current drives [53]. To date, GNRs have been fabricated from exfoliated graphene [100] and operated by back gates, or nanometer scale ribbons produced by explosive methods [36] that are neither controlled nor reproducible. These methods are not suitable for large-area device fabrication. Sub-10 nm graphene nanoribbons fabricated by lithography and operated by top gates on large-area graphene has not been demonstrated yet. In this chapter, we demonstrate the wafer scale process of lithographically patterned GNRs on epitaxial graphene on SiC substrates and CVD graphene on Si/SiO 2. Specifically, we report for the first time GNRs fabricated by top-down methods a) on epi-graphene substrates that exhibit a substantial energy bandgap, b) on CVD graphene, c) having less than 15 nm width and d) more than 100 mev bandgap. 76

91 At the same time respectable carrier mobility ( cm 2 /Vs), current modulation (10:1 at 300 K, >10 6 at 4 K), and high current carrying capacity (0.3 ma/ m at V DS = 1 V) was maintained too. Both single GNR and GNR array devices are discussed. 5.1 Epitaxial GNR FETs on SiC Epitaxial graphene was grown on Si-face 6H-SiC [24]. Raman measurements indicate predominantly single layer graphene coverage. The graphene was patterned by e-beam lithography and etched in O 2 plasma. Hydrogen silsesquioxane (HSQ), a negative-tone electron-beam resist, was used to form sub-10 nm GNRs. A chart of the process flow is shown in Figure 5.1. (a) HSQ (b) O 2 O 2 (c) graphene HSQ removal in BHF SiC SiC SiC (d) PMMA Cr/Au (e) (f) HSQ Al 2 O 3 SiC SiC SiC (g) Cr/Au SiC PMMA (h) S G D SiC (i) top view G S D Figure 5.1: Schematic of the epitaxial sub-10 nm GNR FET fabrication: (a) (c) graphene patterning with HSQ and O 2 plasma, (d) (e) metallization, (f) oxide seeding and ALD, (g) (h) top gate metal deposition. 77

92 Line Width (nm) It was found that at higher developer temperature, the resolution of HSQ patterns increases and the best resolution of 5-7 nm were obtained (Figure 5.2 (a)) [94]. This is attributed to the increase of differential dissolution rate between exposed and unexposed regions at higher developer temperature [101]. In addition, the HSQ line developed at a higher temperature (38 C) shows a better uniformity (a) (b) W LINE =12 20 C for 30 s C for 10 s W SPACING =10 nm Line Dose (nc/cm) 200 nm Figure 5.2: (a) HSQ line width as a function of electron-beam line dose in 20 nm of HSQ resist at two different developer temperatures. (b) HSQ gratings with line width of 12 nm and spacing of 10 nm exposed in 20 nm of HSQ on graphene. Nano-gratings of 12 nm line widths and 10 nm spacings were obtained after optimization of spin coating, soft baking, hard baking, electron beam dose, and development methods (Figure 5.2 (b)). HSQ lines (width ~10 nm) on graphene were fabricated and then the HSQ line patterns were successfully transferred into graphene, leading to GNRs with line width of ~10 nm (Figure 5.3 (a) and (b)), hence no undercutting was observed in this case contrary to the case of the Al mask [99] described in Section

93 (c) 1000 (d) E gap (mev ) 100 (c) W GNR (nm) Figure 5.3: (a) SEM micrograph of a GNR FET showing the 10 nm HSQ mask and the source/drain electrodes. (b) The 10 nm graphene channel after the removal of the HSQ mask. (c) Optical microscope images of the wafer-scale GNR FETs. A 15 nm thick ALD Al 2 O 3 film on spin-coated HSQ was used as the top-gate insulator. The HSQ was used to seed the ALD deposition (see Figure 5.1 for the schematic process flow). Several seed layers were characterized in detail to ensure minimal unintentional doping effect. HSQ and e-beam evaporated SiO 2 were found to be the most suitable [102]. The gate stack was found to result in a small hysteresis in the I-V characteristics; thus the chosen gate stack enables an investigation of the GNR transistor characteristics. E-beam evaporated Cr/Au source/drain contacts were then deposited to form FETs. Optical images of the devices from wafer to device level can be seen in Figure 5.3 (c). 79

94 T=4 K (a) Figure 5.4: Scaling behavior of the GNR FETs. (a) The transfer characteristic of FETs with increasing width. (b) I D -V D at V GS = V Dirac shows increasing barrier as the width is decreasing. 2D graphene (W = 1-20 μm) transistors using the same gate stack show appreciable gate modulation (~3x). Figure 5.4 (a) shows the scaling of the device transfer characteristics as a function of the GNR width. Two trends can be observed: a) the modulation increases with the width and b) the Dirac point is more negative for the 7 nm GNR, but it is constant otherwise. Both trends are attributed to the edge roughness and the related charge accumulation on the edges. Especially the Dirac point shift is caused by that. The decrease in modulation can be an artifact because the measurements are performed close to the gate leakage limits. The increase of the current blocking (i.e. the barrier height) as the width decreases (Figure 5.4 (b)) further supports this statement. 80

95 I D ( A) I D ( A) 10 0 (a) 10 x x T = 4K T = 295K W = 10 nm L = 1.5 m t ox = HSQ+15 nm Al 2 O 3 V DS = 20 mv gate leakage V GS (V) (b) T = 4 K W = 10 nm L = 1.5 m 0.15 ev 4 (c) V G = -2V V G = -2V T = 4 K -2 W = 10 nm L = 1.5 m -3 t ox = HSQ+15 nm Al 2 O V DS (V) Figure 5.5: (a) Transfer characteristic of a 10 nm GNR FET at room temperature and at 4 K. (b) Differential conductance di D /dv DS as a function of V DS and V GS. The color bar is the exponent, log 10 (di DS /dv DS ) in -1. Transport gap of ~ 0.15 ev is observed. (c) Low temperature family I-V of the same device showing good on/off ratio. The device transfer characteristics of top-gated 10 nm wide GNR device are shown in Figure 5.5 (a). Room temperature modulation is ~10x, but the 4 K modulation increases to ~10 6 x, clearly indicating the opening of a bandgap. Measurement of the differential conductance as a function of V DS and V GS at 4 K shows a transport gap exceeding 0.15 ev (Figure 5.5 (b)); similar gaps were measured on multiple devices. The family I-V curves shown in Figure 5.5 (c) indicate that the GNR FETs a) switch off, b) carry ~0.3 ma/ m current density at V DS = 1 V, and c) are yet to saturate. Similar band gap values were extracted from the temperature dependent minimum current measurements. The low (~10x) modulation on room temperature cannot be explained by assuming ohmic contacts. Further analysis pointed towards the Schottky barriers (SB) formed between 2D graphene contacts and the GNR regions. However the source of the barrier in the SB contact is the bandgap. A schematic band diagram shows the ON and OFF state of a SBFET in Figure

96 (a) e - E F OFF (b) ON E G E F E F E F e - V G E G Figure 5.6: Schematic band diagram of the low-bias operation of the GNR SBFET. (a) OFF state with barrier of E G /2. Thermionic emission is possible only at room temperature. (b) In the ON state the barrier height is the same, but tunneling in possible at any T. One of our group members, Pei Zhao, set up a simulation framework to give some insight to the problem. His simulation results are based on an analytical model selfconsistently solved with the 2D Poisson equation at the ballistic limit. WKB approach is used to calculate the tunneling current. A 10-nm GNR with perfect edge shape is assumed as the channel with length of 1 m. The model is based on the assumption that the Schottky barrier height depends on the width of GNR and it is half of the band gap of the GNR, B ~ E G /2. Although the role of metal contact on 2D graphene is not very clear at this moment, it has been measured to be ohmic Schottky barrier contact to the GNR is thus a reasonable assumption, since the I DS vs. V DS family curves show clear SB behavior (Figure 5.4 (b)). Figure 5.7 shows the conductance as a function of V DS and V GS for two representative GNR FETs of 10 nm (a) and 17 nm (b) at T = 4 K. The modeled conductance versus V DS and V GS for 10 nm (c) and 17 nm (d) are also shown as a comparison to the experimental results. The conductivity is represented as the color in logarithmic scale; the black (dark) color indicates the I OFF region in the V DS and V GS planes. I OFF is defined as 3 orders of magnitude lower than I ON. The fact that the model 82

97 correlates well with the experimental results confirms the initial assumptions, namely that the band gap values extracted from the measurements are correct. Figure 5.7: Comparison of the experimental ((a) & (b)) and modeling ((c) & (d)) results of the differential conductance for a 10 nm and a 17 nm GNR FET as a function of V DS and V GS at 4 K. The black color represents low conductance as indicated by the color bar. One way to further increase the net current drive is to use a parallel array of GNRs between the source and the drain. An SEM image of the HSQ mask used to create such parallel ribbons is shown in Figure 5.2 (b). As mentioned before the line width of the GNRs can be different than the line width of the HSQ mask and the SEM imaging of the GNRs are often not conclusive due to rapid charging effects during imaging. For this reason a cross sectional TEM was taken of the parallel GNR channel (Figure 5.8). The TEM allowed us to confirm the existence of the GNRs, while features with 30 nm 83

98 periodicity was found, which is exactly the designed pitch of the GNR array. The individual GNRs consist of 2-3 layers (including the surface reconstruction layer [68]) and the widths seem to be slightly less than the 13 nm expected based on the dimensions of the HSQ mask. The upper section of Figure 5.8 shows 3 GNRs out of the 30 and in the lower part only the magnified GNRs are shown. B C D A Figure 5.8: Cross sectional TEM of the parallel GNR array. 2-3 graphene layers were found with less than ~ 10 nm widths. The periodicity of GNRs is exactly 30 nm, as designed. In Figure 5.9, the characteristics of such a GNR array FET with 30 parallel 13 nm wide GNRs with a 30 nm pitch is shown. The drain current scales with the number of ribbons as expected. The transfer characteristics of individual GNRs are also preserved in the array and it is reproducible over multiple devices. This implies that possible nonuniformities in GNR widths and edge roughnesses have a minimal effect on the measured device characteristics. The maximum high-field current drive measured before breakdown was extremely high approaching ~7.5 A/mm if scaled to the active ribbon width (390 nm). Scaling by the total channel width (30 x 13 nm + 30 x 17 nm gap) would lead to 2.7 A/mm, which is still remarkable. Such high current drives have never been reported in graphene before. This high current carrying capability is attributed to 84

99 I D ( A) I D ( A) I D (ma) the high electrical and thermal conductivity of the 1D graphene channels (due to absence of lateral scattering), coupled with the excellent thermal conductivity of the underlying SiC substrate. The maximum current density observed for 2D devices on the same substrate is 2.8 A/mm, which indicates that the 1D confinement plays a role in the high current drive. On the other hand devices with similar dimensions were fabricated from exfoliated and CVD graphene on SiO 2 show only A/mm maximum current density, emphasizing the importance of the properties of the substrate as well (a) 10 4 x 10 5 (b) V G = - 5V V G = -1V 4 3 (c) T = 4 K V DS = 20 mv t ox = HSQ+15 nm Al 2 O 3 W = 30 x 13 nm L = 5 m V GS (V) 0 2 T = 4 K -5 W = 30 x 13 nm 1 T = 4 K L = 5 m L = 5 m t ox = HSQ+15 nm Al 2 O 3 W = 30 x 13 nm V DS (V) Field (kv/cm) Figure 5.9: (a) Gate dependence of I DS in a FET with 30 parallel 13 nm GNR channel with a 30 nm pitch. Despite the possible width variations, an on/off ratio of 10 4 is achieved at low temperature. (b) Output characteristics of the 30 GNR array-fet at 4 K. (c) The current drive of the 30 GNR array-fet is approximately 30 times of the current of a single GNR FET. At one occasion a (single GNR) device with exceptional characteristics was measured (Figure 5.10). Although it is an isolated and so far not reproduced case it is worth to mention at least to show what to expect if GNR width scaling will continue. The exact origin of the improved properties is unknown, but it is not without precedence [103] that a GNR became thinner at some point, what causes a high bandgap barrier in the channel. The designed width of the device was 13 nm and the gate length is 6 m. 85

100 I DS (na) I DS ( A) W = 13 nm L = 7 m t ox = HSQ+15 nm Al 2 O V G = -2.5V V G = -0.3V V G = -2.5V V G = -0.5V (a) T = 4 K T = 4 K (b) T = 4 K (c) V DS (V) V DS (V) 10 W = 13 nm L = 7 m t ox = HSQ+15 nm Al 2 O 3 Figure 5.10: (a) Differential conductance di D /dv DS as a function of V DS and V GS. The color bar is the exponent, log 10 (di DS /dv DS ) in -1. Transport gap of ~ 0.5 ev is observed. (b) and (c) Low temperature family I-V of the same device at different scales showing good on/off ratio and strong rectification. Both in the differential conductance plot and in the family I-V current blocking up till 0.5 V can be seen. At high positive V DS the close to 1 A/mm current has a strong saturation tendency. At negative bias the believed to be tunneling current [88] reaches 6 A/mm current density, which is 6 times higher than the forward bias current at the same gate bias. The measured characteristics closely resemble the simulated tunneling part of the current shown in Figure The thermal part of the current might be suppressed by the co-occurrence of the high bandgap and the low temperature (4 K). The above results are the first report of top-gated GNR FETs on large-area epitaxial graphene exhibiting exceptionally high drive currents, the opening of a substantial bandgap, and linear scaling of properties with the number of GNRs in parallel arrays. The disadvantages typically attributed to GNRs (such as edge-scattering and resultant degradation of device performance [38].) need to be carefully re-examined in the light of this and other recent reports [104]. 86

101 5.2 CVD grown GNR FETs Another promising approach for large-area graphene production besides the epitaxial growth on SiC described above is chemical vapor deposition (CVD) on suitable metals, followed by a transfer process onto any substrate [23]. Though the latter approach involves a transfer process, it is relatively inexpensive and offers the freedom to transfer the resulting graphene onto suitable substrates. Recently, CVD-grown two dimensional (2D) graphene devices for RF applications have been reported [105] but there are no reports of the properties of graphene nanoribbons formed on large-area grown CVD graphene, which is the subject of this section. Experimental observations of energy gaps have only been reported for GNRs patterned from exfoliated or epitaxial graphene [6,9]. Here [106], we report the fabrication and electronic properties of GNR transistors on CVD-grown large-area graphene. In particular, we observe the opening of a bandgap as large as 0.1 ev in GNR-FETs as measured by a differential conductance method [6]. Figure 5.11: (a) Schematic device structure and layout of the backgated GNR FET. (b) SEM image of the GNR with an inset showing a magnified view of the nanoribbon. 87

102 CVD graphene was grown and transferred onto t OX = 90 nm SiO 2 /p + Si substrates [107]. Hydrogen silsesquioxane (HSQ) diluted with methyl isobutyl ketone (MIBK) was used as an e-beam resist to form GNRs with width W = 12 nm or less. Details of the HSQ process have been discussed before (Chapter 5.1 and [94]). In this case the HSQ mask wasn t removed and back gate was used to control the devices. Source/drain contact metals Cr/Au (5/100 nm) were deposited by electron-beam evaporation. Figure 5.11 (a) shows the schematic device structure and layout in top- and crosssectional views. The GNR is connected to the 2D graphene by a linear lithographic flare from the width of 12 nm to the tens-of-microns scale. The source and drain contact metals sit on top of the 2D graphene regions. The graphene is covered by HSQ as also shown in the cross-section view of Figure 5.11 (a). Figure 5.11 (b) shows a scanning electron microscope (SEM) image of the GNR region in the device. The inset image enlarges the GNR region and reveals that the width of GNR is 12 nm and this is a measure of the HSQ and it is not known exactly how this pattern roughness transfers to the GNRs. From the SEM image, the nanoribbon edge appears relatively smooth. Electrical measurements were performed in vacuum from room temperature (300 K) to 4 K. Figure 5.12 (a) shows the measured drain current I D versus the back-gate voltage V BG for a 12 nm wide GNR-FETs at various temperatures. The gate modulation is approximately 10x at 300 K. The gate modulation increases to nearly 10 6 x at 4 K. The strong temperature dependence of the minimum current indicates the opening of a bandgap. The behavior is quite distinct from 2D graphene FETs where the modulation remains essentially unchanged over similar temperature range due the absence of a bandgap [35,94]. 88

103 Figure 5.12: Transport properties of back-gated CVD GNR FET of width 12 nm. (a) Drain current vs. back-gate voltage and temperature. (b) Common-source transistor characteristics at 4 K. One may estimate the bandgap created by quantum confinement in an armchairedge GNR (Eq. (4.5)). For W = 12 nm, we expect E G 0.1 ev. The GNR is connected to the 2D graphene regions through adiabatic contacts, meaning the bandgap should change continuously from 0 ev in the 2D regions to the bandgap of the GNR at the ribbon. Thus the contacts to the GNR are effectively of the Schottky-barrier kind, with height B ~ E G /2 = 50 mev. The Fermi-tail of carriers at room temperature is substantial, and thus a large off-state leakage current due to thermionic emission is expected. However, as the temperature is lowered, kt << B and thus the off-state current reduces drastically since carriers must now either tunnel through the gap, or hop through defect states. The Schottky-barrier model, which describes the device operation, was discussed in the previous Section. Figure 5.12 (a) also shows the ambipolar behavior. Depending on the V BG, electrons or holes become main conduction carrier type. The window becomes clearer at low temperatures, when the thermionic emission current is 89

104 suppressed. Figure 5.12 (b) shows a family of I D V DS curves for the GNR-FETs at various V BG. Figure 5.12 (a) and (b) clearly shows the substantial modulation at low V DS due to the movement of the Fermi level controlled by the back gate voltage. At V DS substantially larger than the gap, the current modulation is lower, similar to the breakdown behavior in semiconductor FETs. Current densities exceeding 1 A/mm are measured at high drain biases, consistent with recent reports for exfoliated GNRs [108]. Figure 5.13: (a) Differential conductance map of a 12 nm GNR FET as a function of V DS and V BG at 4 K. (b) Differential conductance and absolute drain current vs. drain-to-source voltage at a back-gate bias of 50.5 V. Figure 5.13 (a) shows the differential conductance log(di DS / dv DS ) vs. V DS and V BG for the GNR-FET at 4 K. The differential conductance is represented as a color in logarithmic scale; black indicates low conductance and red indicates high conductance. The vertical extent of the dark diamond shape is indicative of the GNR gap [6]. The extracted GNR bandgap from this method is around 0.1 ev as discussed earlier, consistent with what is expected [6,89]. Though the experimental extraction is close to the model, it is worth discussing recent reports on the extraction of bandgap due to 90

105 I D ( A) transport arising from hopping between quantum-dot like localized regions in GNRs [109,110]. For GNR widths greater than 40 nm, when the band-gap is less than 0.04 ev, extraction of the low bandgap by the conductance method is expected to be strongly affected by background potential disorder, or hopping between localized states. However when the bandgap is substantially larger than the potential disorder, the disorder acts as a weak perturbation, similar to dopants in semiconductors. Since the GNRs fabricated here have smaller width than the previous reports [6,109,110,111], the gap reported is indicative of the modification of the density of states by quantum confinement. Given that the differential conductance at low temperature is proportional to the density of states, an energy gap of ~0.1 ev can be also inferred from Figure 5.13 (b). Sub-10 nm GNRs were also fabricated showing bandgap as high as 0.2 ev and 4 K and current modulation of 10 8 x (Figure 5.14 (a) and (b)). The exceptionally low gate leakage makes the high modulation possible but the sub-10 nm size is responsible for the high bandgap (W = sub-10nm / L=1 m) V DS = 0.02V (a) T = 4 K (b) ~ K 250 K 200 K 150 K 100 K 70 K 40 K 20 K 10 K 4 K V BG (V) Figure 5.14: (a) Differential conductance di D /dv DS of a sub-10 nm GNR FET as a function of V DS and V GS at 4 K. The color bar is the exponent, log 10 (di DS /dv DS ) in -1. Transport gap of ~ 0.2 ev is observed. (b) Transfer characteristic of the same device as a function of temperature. 91

106 A more quantitative theory of the behavior of the GNR-FETs requires knowledge of the precise edge roughness and edge-geometry, which is not available at this point. In spite of this unknown, we showed that GNRs fabricated by lithography from large-area CVD graphene demonstrate a substantial bandgap opening which is similar to that from exfoliated graphene. The large-area graphene will thus allow a systematic study of large numbers of similar GNRs, which is currently underway. Statistical analysis of the properties of GNRs of similar widths is expected to move the field of electronics based on graphene nanostructures forward. The experimental result shown here should be considered a first step towards such goals. 92

107 CHAPTER 6: P-N JUNCTION FORMATION IN GRAPHENE In order to utilize graphene devices as useful electronic components, the electronic properties of graphene must be tailored through a doping process. Typically, silicon-based devices are doped by replacing some of the atoms in a silicon crystal with various dopant atoms or molecules. In graphene, on the other hand, dopants are generally deposited on top of the carbon sheet rather than as substitutional impurities [102,112]. Recently, several groups reported B- and N-doping of graphene in the process of graphene synthesis. Arc discharge method, for example, was used to prepare B- and N- doped graphene by using high-current between graphite electrodes in the presence of B 2 H 6 or NH 3 gas, respectively [113]. Furthermore N-doped graphene was synthesized by chemical vapor deposition (CVD) [114] or through electrothermal reaction with NH 3 [95]. Although doped graphene was successfully synthesized by these methods, the observed mobility is less than 500 cm 2 /Vs, which is lower than in case of mechanically exfoliated graphene. N-doping of graphene by NH 3 annealing after N+-ion irradiation was reported [115], which proved to be successful to maintain mobility (6000 cm 2 /Vs) despite the unavoidable crystal defects. Besides the methods mentioned above, electrostatic field tuning can also be used to control electrical properties of graphene by (reversibly) controlling the carrier concentration and the Fermi level without increasing the level of disorder and defects. 93

108 I DS ( A) We will demonstrate doping by electrostatic tuning first. Although it is both conceptually and fabrication-wise simple it introduces extra electrodes which turn a 3-terminal transistor to a 4 or 5 terminal device, which is impractical. Graphene was found to be sensitive to the environment through unwanted surface absorption that we minimize [99]. Passivation of the exposed graphene surface solves the gas absorption problem but it places another material in contact with graphene: the oxide used for the passivation. Surface states and dipole bonds in the oxide indeed induce doping in graphene, but it is controllable, and can be used as a valuable tool (Figure 6.1). In the latter part of this Chapter we explore the doping effect of various oxides and we utilize them to form p-n junctions in graphene. 5 4 L=2 m W=500 nm t ox =300 nm SiO 2 before high-k deposited after 20 nm ALD Al 2 O n Dirac-point p V G (V) Figure 6.1: Doping effect of the high- top gate dielectric deposition in case of an exfoliated graphene FET on SiO 2. The FET has heavy p-type doping before high- deposition, the Dirac point is higher than +50 V. After 20 nm ALD Al 2 O 3 deposition the position of the Dirac point decreased by more than 100 V. It corresponds to more than cm -2 change in the carrier concentration at a given bias. Figure 6.2 reviews the structures we used to achieve graphene p-n junction. One can see that the main concept is very similar, only the method to place remote charges in 94

109 the vicinity of graphene is different. In Section 6.1 we review the double gated device, which was introduced and discussed in detail in Section 4.3. A side gated device is shown in the following Section, which is conceptually equivalent to the double gated device but planar. After characterizing the doping effect of various oxides we construct devices with split channels, which mean that there is one kind of oxide covering one half of the channel and a different one is deposited on the other side. A special case of this is when the oxide itself is actually the same on both side, but the trap charges in the oxide are engineered by the dose of the applied high energy e-beam irradiation (Section 6.4). Figure 6.2: Ways to achieve p and n doping in the graphene channel. Remote charges can be either present in the oxide or induced by electric field. Measured and simulated transfer- and output-characteristics of the graphene p-n junction is shown in Section 4.3. For better understanding we give a quick review of the expected device operation, especially because it wasn t emphasized earlier in this thesis. Figure 6.3 (a) shows the schematic of the available states of a GNR on the two sides of a junction. The cross sections denoted by capital letters are special bias conditions 95

110 corresponding to Figure 6.3 (b), which is the plot of the expected transfer characteristics. In case A (and E) both side of the junction is n-type (p-type), the thermionic emission dominated conductance is high. In case B (and D) one side of the junction is intrinsic causing high resistance state or no conduction at 0 K for a GNR. Actually only case C is when the channel is biased to be a p-n junction and large portion of the current is due to tunneling, depending on the size of the bandgap and the temperature. This double minimum is the fingerprint of a globally gated p-n junction, what we will look for in the rest of the Chapter as a proof of the achieved goal. Figure 6.3: Expected characteristics of a graphene p-n junction. (a) Band alignment of the n-side (left) and p-side (right) of the junction. E 0 is the intrinsic level. (b) Transfer characteristics as a function of a global gate V G. The cross sections are highlighting the following channel dopings: A: n+/n, B: n/i, C: n/p, D: i/p, E: p/p Double gated GNR One way to achieve p and n doping in the graphene channel is to have two gates, one set at negative bias and the other is at positive. The abruptness of the junction depends on how closely the two gates are spaced. We realized it with a global back-gate 96

111 and a top gate, which covered half of the channel. Compared to the ideal situation (i.e. two top gates) this case is slightly more complicated by non-constant contact resistances due to the global nature of the back gate. However it is just a small perturbation due to the low resistances of the contacts compared to the GNR channel, thus we neglect it now. In Section 4.3 the detailed operation of such a device was analyzed but it wasn t of the utmost importance to point out the double minimum in the transfer characteristics. In Figure 6.4 (a) the transfer characteristics is shown again with a constant top-gate slice highlighted and redrawn on (b). (a) (b) p/p p/n V TG = -8.5 V p/i i/n Figure 6.4: (a) Transfer characteristics of a double gated p-n junction GNR FET. (b) is the slice at constant V TG = -8.5 V. Although more detailed data is available for this device as a proof of the p-n channel the double minimum is highlighted. p/i/n denotes the current doping of the channel. The existence of the back gate is certainly does not make this solution useful besides in proof-of-concept devices. Having two closely spaced top gates can easily be shorted and the altogether 4 contact of the device is a complication. It is reprogrammable on the fly on the other hand, which opens many interesting possibilities. 97

112 6.2 Side gate control Another way to overcome the problem with the back gate, while avoids the fabrication difficulties with the closely spaced top gates is to design side gates. It might avoid the problem with the gates shorting with each other although too closely positioned gates might be directly shorted to the channel. Also, in case of an unpassivated device the side gate oxide is partially air, which has low- value. We have fabricated such devices and demonstrated n and p doping as a proof of concept (Figure 6.5). Similarly as other gating methods it requires a continuous voltage applied on the gates to maintain the doping. In the followings we demonstrate doping with fixed charges. p-doped (b) n-doped (a) (c) Figure 6.5: (a) Transfer characteristic of a side gated GNR FET at 0 V and +/- 5 V applied bias on the side gate. The applied bias dopes half of the channel which introduces a (hard to notice) 2 nd minimum. (b) SEM and (c) schematic of the device. 6.3 Gate oxide induced doping A common trend [45] for top gated epitaxial graphene FETs is the high initial n-type channel doping so switching them off is a difficulty. To mitigate this problem we 98

113 performed a broader study to characterize the effect of the oxides on a simple structure: 1x1 cm samples of epitaxial graphene with metal contacts in the corners were made. Our conjecture was that one component of the high n-type doping have to be the graphene/oxide interface states. To test this we tried several materials (SiO 2, HSQ, Al 2 O 3, HfO 2 ) deposited by different methods (e-beam evaporation, ALD, spin-coat). Another reason for the doping can be the polar nature of the oxide, what we tested by depositing a second layer of highly polar oxide after the surface layer. Figure 6.6: Change of the carrier concentration in case of different oxide stacks. The dashed line shows the initial doping of the sample. None of them provide lower n-type doping concentration than the original doping of the sample. Further high- oxide deposition added extra doping. The table shows the data in detail corresponding to the different oxide stacks. 99

114 We found that all the tested oxides introduce n-type doping (Figure 6.6). The quantity of the doping shows correlation to the dielectric constant of the oxides. By removing the oxide the initial doping can be restored. In case if we deposited a high- oxide on the top of the low-k oxide the n-type doping increased further. High temperature annealing can increase crystallinity of the oxide therefore decrease trapped charge density. We experienced some improvement in case of 600 C rapid thermal annealing (RTA) (Figure 6.7) but the quick thermal expansion introduced cracks in the oxide. Figure 6.7: Change of the carrier concentration in case of HSQ+high- oxide stacks and the effect of RTA. The dashed line shows the initial doping of the sample. (a) HSQ+Al 2 O 3 oxide stack. The RTA continuously increases the doping. (b) HSQ+HfO 2 oxide stack. The highly polar HfO 2 heavily increases the n-type doping but the RTA continuously decreases it. The tables are showing the details of the process. 100

115 Our experiment showed that the unwanted doping effect can be minimized by utilizing certain oxide stacks, but intrinsic or p-type doping was not yet achieved. Based on this study multiple samples were fabricated with HSQ and SiO 2 based gate stacks. Depending on the initial doping of the epitaxial graphene sample and some unknown process condition low p-type doping was achieved in some cases. Devices with SiO 2 covering half of the channel and lightly dosed HSQ covering the other half were fabricated. The two oxides were expected to dope the corresponding part of the channel to varying degrees. The p-n junction formation in the channel was confirmed by the transfer measurement (Figure 6.8). Based on the measurement one can see that both p- and n-doping was achieved not like in some other cases (Figure 6.9 (b)) when the junction was actually n-/n+ only. (a) (b) n/n p/n i/n p/i Figure 6.8: (a) Schematic of a p-n junction GNR FET which has HSQ on one half and SiO 2 on the other half of the channel. (b) The characteristic double minima can be clearly observed on the transfer curve. p/i/n denotes the current doping of the channel. 101

116 6.4 E-beam exposure of HSQ as a tool for doping It is well known that the doping of graphene can be controlled by the e-beam exposure dose of an HSQ layer spun on graphene [116]. The crosslinking of HSQ has been studied previously [117] and is found to be a complex transition from a hydrogenrich structure to a hydrogen-depleted structure. This transition enables the HSQ film to effectively function as both an n-type and p-type dopant. Besides electron beam dose, the crosslinking can be triggered by long annealing at high temperature in air. In our case e-beam exposure is preferable while it enables high spatial control. First the doping strength of e-beam dose was calibrated (Figure 6.9 (a)) then half of the GNR channel was exposed with high dose in FETs. Such way one side of the channel became p-doped, while the other side remained n-doped due to the unexposed HSQ coverage. The transfer characteristics of the devices showed the typical double minimum as expected (Figure 6.9 (b)). Although this method provides an easy and well controllable way to form p-n junction in graphene it has drawbacks. It is not very well known what damages occur in the graphene layer due to the high electron dose. 102

117 n- doped (a) (b) n+ doped Figure 6.9: (a) Threshold voltage (V Dirac point ) shift as a function of e-beam dose. (b) Multiple minima exist in the transfer characteristics as a result of different doping in the two sides of the channel. As the final building block of the GNR TFET, p and n doping was achieved with multiple techniques. The two demonstrated families of methods are control by multiple gates and charge induction by oxide charges, albeit doping by atom substitution is possible too. Even though GNR p-n junction FETs were fabricated and operated at bias conditions when tunneling was the main conduction mechanism we cannot yet say that the goal of the graphene TFET [53] was achieved. The main benefit of the GNR TFET, besides the high current drive, is the sub-60 mv/decade subthreshold slope wasn t accomplished. Towards that goal the gate oxide has to be thinned to a couple nm EOT. The hurdles of the oxide scaling will be discussed amongst the future plans. 103

118 CHAPTER 7: COMPARISON OF GRAPHENE FETS Based on the widespread work done on all kind of graphene devices we are in the unique position to perform a comparison founded on firsthand experimental results. In the beginning all experiments were performed on exfoliated graphene. Later as other forms of graphene became available, the results already demonstrated on exfoliated graphene were replicated on epitaxial- and later on CVD graphene. There is no fundamental difference between exfoliated and CVD graphene. However the quality of CVD graphene is usually lower in the current materials. Epitaxial graphene grown on SiC has been proven to be structurally equivalent. The number, the role, the structure and the importance of the layers between graphene and bulk SiC is still an ongoing debate. In this chapter the differences and advantages of the three main forms of graphene are discussed. In terms of material quality CVD graphene has a clear disadvantage mainly due to the transfer process, which causes rips and holes all over the material. Recently direct growth on oxide was demonstrated, which may solve this problem in the long term [118]. Exfoliated graphene is single-crystal, but only because its small size. The grain size of the CVD or epitaxially grown graphene can be of the same size range but bearing the advantage that the overall graphene size is limited by the size of the substrate only. Substrate effects can be important as oxidized silicon dopes the graphene p-type, while 104

119 SiC dopes it n-type. On SiC there is a carbon rich surface reconstruction layer between the graphene and SiC, which ensures a smooth and clean surface. It is not obvious but achievable for other substrates too. The yield of the FET fabrication process is found to be generally independent of the kind of graphene. In case of exfoliated graphene and especially for CVD graphene peeling off during processing can occur, consequently lowering the yield. The quality of graphene is often benchmarked by the mobility of the FETs produced on it. Mobility in graphene devices is a key parameter due to the high expectations raised by early experiments [4]. It was clear that the intrinsic mobility of graphene is greatly influenced by any material in contact with graphene, may it be the substrate or the gate oxide [54]. Concentrating on the comparison we have to call attention to a few principles about the determination of mobility in graphene. First, the mobility is highly carrier concentration dependent, quoting mobility without indicating the carrier concentration might be meaningless. Moreover, mobility is a derived quantity describing electron motion in an FET, not a material property, so its value might depend on certain assumptions. In case of GNRs the value of the mobility of a device is even more uncertain. Edge roughness scattering is predicted to be a dominant mobility limiting factor[30] and there are reports which seems to experimentally verify the predictions [38]. On the other hand there are reports [119,120] of mobilities in line with the best 2D devices too. The root of this huge discrepancy lies in the caveats of the way mobility is calculated (Eq. (7.1)). 1 LG 1 1 LG / W en R W en ( R R ) C ( V V ) tot C OX GS 0 (7.1) 105

120 Kim et al. [69] gave a simple and elegant way to define mobility for graphene based FETs. Based on this work it became widely accepted to quote intrinsic channel mobility instead of the complete device mobility. It is not a problem in itself, but the calculated intrinsic mobility strongly depends on the value of the contact resistance R C, which is chosen based on curve fitting instead of an independent measurement. Depending on the more-or-less arbitrary choice of R C the calculated intrinsic mobility can be orders of magnitudes higher than the extrinsic mobility. On the other hand the gate oxide capacitance difference between a 2D device and a GNR is mostly ignored. Using 2D parallel plate capacitor model for a nm GNR may lead to 5 20 times underestimation of the mobility [99]. So both overestimation and underestimation by orders of magnitude is easy to achieve. Thus, mobility lost its ability to be a good figure of merit to compare the performance of the devices made by various groups. In Figure 7.1 we calculated the mobility using 2D capacitor model for the gate capacitance and the values are not corrected for the contact resistance. Furthermore we show the average amongst the bests, and not the average or median result. J MAX (A/mm) Mobility (cm 2 /Vs) 2D GNR exfoliated epitaxial CVD exfoliated epitaxial CVD * I ON/OFF RT I ON/OFF 4 K Figure 7.1: Summary of graphene properties obtained by various methods. * At moderate field; devices were not driven close to burn-down. Mobility calculated assuming 2D capacitor model for C ox and without subtracting R C. 106

121 The mobility for exfoliated 2D FETs is clearly higher than for the others, which is possibly due to the lack of grain boundaries. This advantage diminishes for GNRs as those can be on a single grain due to their small size. The GNR mobility seems 2-10 times smaller compared to the 2D, but if we would correct it for 1D capacitance the ratio would turn around. A property of less ambiguity is the 2D current density of a graphene FET. If the channel width can be determined the calculation is accurate. Defining 3D current density for a single layer of material can be a bit more uncertain. Figure 7.1 shows the comparison of the measured maximum current density in graphene devices, usually before breakdown. The maximum achievable current on graphene and in GNRs was found to depend on the thermal conductivity of the substrate [108]. Accordingly on epitaxial graphene both in case of 2D and GNR devices much higher current density was observed. Besides the thermal conductance of SiC the coupling between SiC and the graphene layer can be beneficial as well as the higher surface phonon energies, which allow higher carrier saturation velocity. The highest current density was observed in GNRs. In this case the 1D nature is responsible for the boost, by making lateral carrier momentum impossible, thus increasing the average carrier velocity along the channel as sketched in Figure 7.2. In addition the nanoribbons benefit from more efficient heat spreading compared to 2D devices [108]. Higher than 10 A/mm current density was observed for many devices; this is the highest ever reported value for any material. Even the 1-2 A/mm current density is quite high compared to other materials and together with the high carrier mobility it could enable high speed switching. But pushing 107

122 carriers through the transistor channel is not all that is necessary blocking them at certain cases is also required, which is not the strongest point of gapless graphene. Figure 7.2: Comparison of the spatial distribution of the carrier momentum in 2D and 1D graphene. In both cases carriers move with the Fermi velocity F, but the average velocity sat can be much higher in the 1D case. 2D graphene has zero bandgap, which means that electronic states at any bias are available, although the density of states goes to zero at the Dirac point (recall Figure 2.2). At absolute 0 K it would actually allow good control, but even at 4 K the thermal activation of carriers and impurity concentration due to substrate effects cause substantial minimum conductance and therefore low on/off current ratio (~10x). In that manner there is not much difference between the various forms of graphene only when it comes to temperature dependence. Probably due to the cleaner substrate interface decrease of the minimum conductance can be observed, which eventually increases the on/off ratio. For GNRs due to the bandgap opening higher modulation is expected. It was indeed observed in all cases, especially at low temperature. The difference between the 4 K on/off ratios shown on Figure 7.1 are not important, it is mostly set by the leakage current level. On the other hand, as discussed before (Section 5.1) the room temperature on/off 108

123 ratios are limited by the midgap Schottky barrier contacts. The 40x modulation for the exfoliated GNR is because that device had Ti/Au contact which makes slightly n-type contact. In terms of bandgap all GNR devices were found to follow the same universal trend (Figure 4.2) independently of the type of graphene. As far as the noise level is concerned, the magnitudes of 1/f noise in exfoliated and CVD samples using SiO 2 substrates are larger than that of epitaxial graphene samples on SiC substrates [121]. In addition, at high carrier concentration regimes, epitaxial graphene devices having HSQ/SiN top-gate dielectric reach a noise level about one order of magnitude lower than the ones with ALD-deposited Al 2 O 3. The graphene samples with stronger noise are in direct contact with SiO 2 as the substrate. This observed phenomenon is consistent with the early assumption [122], attributing 1/f noise to the oxide substrate. Also, the carrier concentration dependence of the noise amplitude A N in all of the samples are -shaped. However, in exfoliated graphene the noise peak is offset from the Dirac-point, while in epitaxial graphene the noise peak aligns well with the Dirac-point, despite the Dirac-point voltages are not the same for each sample. The differences also exist in the noise amplitude modulation. The noise follows the Hooge model reasonably well in most cases, but in case of samples with HSQ/SiN gate oxide the Hooge model fails and the noise amplitude varies dramatically in accord to the change of carrier density as shown in Figure 7.3 (a). The noise measurements of our devices were carried out in collaboration with Nan Sun; further details of the analysis can be found in [123]. As the major properties of the graphene devices based on exfoliated, epitaxial and CVD graphene were reviewed one can see that usually little or no difference was found. 109

124 The only major dissimilarity is the high current drive of epitaxial graphene devices, which depends mainly on the good thermal conductivity of the substrate, and partially by the graphene-substrate interface. Figure 7.3: The noise amplitude A N as a function of carrier density n for four types of graphene samples: (1) exfoliated graphene on SiO 2, (2) CVD graphene on SiO 2, (3) epitaxial graphene on SiC with HSQ/SiN top gate oxide and (4) epitaxial graphene on SiC with Al 2 O 3 top gate oxide. 110

125 CHAPTER 8: SUMMARY AND FURTHER WORK In this research we explored the electronic applications of graphene, a recently discovered material, which promises superior material properties compared to commonly used semiconductors and exhibits unique physics. To take advantage of the high carrier mobility but to have control over the channel conductance nanoscale graphene ribbons were used as the channel of FETs. This work reported the first demonstration of the pattering of graphene to sub-10 nm ribbons by lithographic methods and their use in topgated GNR FETs. Compared to our early fabrication possibilities on exfoliated graphene the potential with large area graphene on insulators are broadly expanded. Many device parameters improved or became measureable like the contact resistance or the oxide capacitance. This opens the possibility of the fabrication of improved 2D graphene FETs and allows more careful analysis of their characteristics. An example is the recent determination of the Dirac point mobility. The 2D graphene transistors exhibit poor on/off ratio but promising mobility. The poor saturation characteristics of the 2D graphene FETs led our attention toward the detailed study of the high field transport of graphene. The exfoliated graphene FETs were compared to CVD graphene based devices and were found to have similar performance but offering the advantage of wafer scale size. SiC based epitaxial graphene has the same size advantage along with the exceptional RF characteristics and high 111

126 current density. For further improvement it became clear that band gap has to be opened by 1D confinement, which was experimentally demonstrated. The successful fabrication of p-n junction in GNR FET is a major achievement and an important step toward the realization of the graphene TFET. Since the first demonstration of the p-n junction GNR FET many incremental steps were made, which finally led to wafer-scale sub-10 nm GNRs with bandgaps up to 0.2 ev. p and n doping was demonstrated by various methods too. Sub-10 nm GNRs fabricated on epitaxial and CVD graphene were found to have similar band gap and device characteristics but record high current densities up to 10 A/mm were measured in epitaxial GNRs only. Although it was mentioned many times it is instructional to show the expected characteristics of the GNR TFET (Figure 8.1), which will help to define the future steps towards that goal. So far we were working to get close to the W = 3 nm GNR width, and the channel doping was demonstrated too. But this is not the only critical dimension of the TFET. We are far from the necessary 0.5 nm EOT (currently around 10 nm) and even if the 20 nm gate length seems achievable with our current technology not much effort was made in that direction. The scaling behavior of the contact resistance is not clear either. 112

127 (a) (b) (c) Figure 8.1: (a) Schematic structure of the GNR TFET. (b) Band diagram showing both the OFF and the ON state. (c) Simulated transfer characteristics exhibiting sub-60 mv/decade subthreshold slope. Forming low-resistance ohmic contacts to semi-metallic or low-bandgap graphene channels have never been a problem. But as a consequence of the pioneering work new challenges have arisen the GNRs possessing substantial bandgap turned out to form Schottky contacts that caused room temperature modulation degradation. Instead of chromium, which has equal work function to graphene (W Cr =W Gr = 4.5 ev), gold (W Au = 5.1 ev) and aluminium (W Al = 4.08 ev) contacts were tested with little success. The high (40x) room temperature on/off ratio seen for exfoliated GNRs was achieved with titanium (W Ti = 4.33 ev) contacts. Even though the contacts are often in direct contact with the GNR for contact resistance and yield considerations there is a 2D graphene region below the contact too. Dropping that 2D region completely from the process might be necessary. Currently, the contact resistance of different samples as 113

128 measured lies in the R C = mm range. The effect of dropping the 2D regions is presently unknown, although not expected to decrease R C. Therefore, the contact optimization is a major next step especially in the light of the R C = 50. m goal set by the specifications of the GNR TFET (Figure 8.1 (c)). In terms of the electrical specifications of the TFET we report some success. The required 0.5 A/mm on state current density was easily accomplished at much lower field; the increased current density in nanoribbons compared to 2D graphene is an unexpected result of the project. The accomplishment of the three orders room temperature on/off ratio met unexpected hurdles due to the Schottky barrier formation, which prevent the study of the subthreshold slope of the devices as well. But even the low temperature subthreshold slope suffers from the thickness of the gate oxide. Although the list of unachieved or poorly understood properties seems long, the successful demonstration of the TFET operation and the confirmation of the predicted characteristics are the successes of this work. The inverse width dependence of the bandgap is an interesting property of the GNRs, which is worth exploiting further. Actually this property is not unique to graphene; quantum confinement effect is universal. But it is stronger in graphene since it has zero bandgap in its bulk or 2D form. It gives 10x difference in the bandgap between a 40 nm and a 10 nm GNR, while there is only 10% difference for a 40 & 10 nm Si nanowire. Also, for graphene it is easy to implement abrupt width changes with lithography, while it is not that straightforward to do for nanowires. A single abrupt width change in a GNR channel can be called GNR heterojunction (Figure 8.2 (a)), while structures with multiple (Figure 8.2 (b)), or even periodic changes (Figure 8.2 (c)) could 114

129 act as periodic quantum dots. Such structures can be used for example to further increase rectification in GNR FETs, in resonant tunneling devices or in single electron transistors. 10nm 6nm (a) (b) (c) Figure 8.2: SEM micrograph of (a) a GNR heterojunction, (b) a graphene quantum dot and (c) a quantum dot chain. 115