OSIRIS Optimal SIC substrates for Integrated Microwave and Power CircuitS

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1 . OSIRIS Optimal SIC substrates for Integrated Microwave and Power CircuitS Development of a European isotopic SiC supply chain ECSEL Project 2014 Call Stéphane Piotrowicz on behalf of Sylvain Delage, Coordinator III-V Lab, Palaiseau, France

2 SUMMARY Isotopes and their properties OSIRIS Objectives OSIRIS Project Topics Main results of the T0+24 Conclusion

3 What are isotopes? Isotopes of an element are species which differ by the number of neutrons in their nucleus. Isotopes have the same number of protons in the nucleus and electrons in the outer spheres of the atom. An obvious difference between isotopes of a same element is their respective atomic mass. These small differences can be exploited to separate/enrich one isotope or the other. The tiny mass difference between isotopes induces small variations in physical and chemical behavior e.g. gas diffusion, deviation in gravimetric or centrifugal field, boiling or freezing point, electrochemical potential, molecular vibration energy etc

4 Silicon has 3 natural stable isotopes Natural silicon composition 28Si 92% 29Si 5% 30Si 3% Natural Si Isotopes out of 100 atoms

5 OSIRIS Project Objectives OSIRIS project is proposing to elaborate innovative SiC material using isotopic sources. This material will offer expected thermal conductivity improvement of ~30% which is important for devices dissipating a lot of power, in particular in SiC power electronics and in microwave device using GaN high electron mobility transistors (HEMT) grown on SiC semiinsulating substrates. OSIRIS project will allow reinforcing GaN technology penetration into the market by cost effectiveness of the SiC substrates and circuit performances improvement thanks to better heat spreading close to the dissipative area.

6 Expected OSIRIS Outcomes For microwave GaN/SiC HEMT this isotopic approach could create a complete shift in the currently used substrate / GaN epi-wafer technology it intends to grow high thermal conductivity (+30%) semi-insulating SiC on top of low cost semiconducting SiC substrates (widely used by the power electronics and LED industries). Reduced layer thickness is necessary as only the top 50 to 100µm SiC wafer is really useful as the expensive substrate itself is currently thinned to realise microstrip waveguided microwave circuits. For power electronics this isotopic innovation will be essentially focused on thermal improvement, better electron mobility at a given power dissipation as mobility and drift mobility decrease with temperature and also better carrier transport thanks to lower scattering rates. Schottky and p-i-n diodes will be tested using this material, which however will have to be doped while microwave devices need semiinsulating materials.

7 OSIRIS Quantitative Objectives The improved thermal SiC properties will be obtained by using single isotopic atoms for silicon and carbon, namely 28 Si and 12 C. The SiC wafer size will be targeted to 100mm (4- inches) which is today widely used in industry. Microwave applications Potential cost of processed wafer: decrease of 30% Thermal resistance improvement : 5 C.mm/W for 20 mm total gate development Lifetime: improvement by around 1 order of magnitude (i.e C junction temperature decrease at given power dissipation) Microwave gain: increase of 1dB Electrical efficiency: increase of about 5% for high frequency CW applications (i.e. above 18 GHz) Power electronics applications Planar device: Thermal resistance improvement of 5 C.mm/W for 100 mm gate width. Vertical device: to be determined. TRL progress: from 3 to 5

8 Consortium Public Research, Industrial R&D, SME & Large Group Technology domain Type of organisation Basic materials, substrates Physical measurement Robustness measurements Semiconductor design, growth, processing Devices and circuits Industry: large group UMS Industry: technological SME ISOSI NORSTEL IST ASCT Industrial Research III-V LAB Public Research CIMAP STUBA LIU LIU

9 SUMMARY Isotopes and their properties OSIRIS Objectives OSIRIS Project Topics Main results of the T0+24 Conclusion

10 SUMMARY Isotopes and their properties OSIRIS Objectives OSIRIS Project Topics Main results of the T0+24 Substrate and thermal measurements at substrate level Device processing : Diodes and GaN HEMT Material and device characterization Conclusion

11 SiC Substrate and SiC Epitaxy Example of LiU contribution Promising epitaxial growth of SiC on top of on-axis substrate, Surface quality well controlled, Wafer flatness and bow compatible with microelectronic requirements. AFM of SiC epitaxial layer from LiU after planarization and epi-ready polishing at Norstel Thickness map of a 100 mm 4H-SiC substrate with on-axis epitaxy measured with 3 mm edge exclusion. The TTV is 22 μm and the warp 25 μm.

12 SiC and GaN HEMT Epitaxial Growth Study Example of III-V Lab contribution Comparison of surface morphology of AlGaN/GaN HEMT grown by III-V Lab on NORSTEL SiC substrate and on NORSTEL substrate including a top SiC epitaxial layer realised by the University of Linköping. Excellent clearly defined atomic step with a reduced surface roughness (< 0.2 nm on HEMT grown onto OSIRIS SiC epiwafer). TS919 W1 TS919 W3 AFM analyses of TS919W1 (SiC reference) and TS919W3 (OSIRIS SiC epi)

13 Isotopic Material Purity Example of LiU contribution More than 3 order of magnitude obtained on 28 Si and 12 C selectivity on isotope pure SiC epi-wafers

14 Thermal Measurements Example of LiU contribution Thermal conductivity was measured by Transient Thermo-Reflectance method Non-destructive, optical method Temperature scanning possible Isotope pure samples were undoped (i.e. low n-type doping, ~ cm -3 ) Averaged values

15 Thermal Measurements Example of LiU contribution Doping influence on thermal conductivity Highly doped samples give lower thermal conductivity Vanadium doped samples give lower thermal conductivity So far only measured on natural SiC samples Samples with 28 Si and mixed C isotopes were measured and compared to natural SiC and fully isotope pure SiC. Thermal conductivity (W/m K) Natural SiC 360 Improvement in comparison to Natural SiC (%) 28 Si + nat C % Isotope pure SiC ( 28 Si + 12 C) % Contribution of 12 C improve by 4pts the thermal conductivity in the c-axis

16 Expected MTF Improvement for 20mm GaN HEMT on isotopic SiC Using NXP study regarding their HEMT devices and competition, using isotopic SiC substrate would double MTF at about 200 C by gaining 7.3 C decrease on Tchannel. Additional progresses are expected by optimising GaN epi. MTF(h) GaN competitor 1 GaN competitor 2 GaN competitor 3 GaN competitor 4 NXP Temperature ( o C) o C h 130 NXP courtesy, GaN on natural SiC, September /T s (ev/k)

17 SUMMARY Isotopes and their properties OSIRIS Objectives OSIRIS Project Topics Main results of the T0+24 Substrate and thermal measurements at substrate level Device processing : Diodes and GaN HEMT Material and device characterization Conclusion

18 First batch of 1.2kV class JBS diodes Example of Ascatron contribution Batch D607: 25A/1.2kV JBS diodes Wafer ID Epi0: n+substrate Epi1: n-drift 100µm 11µm N(N) cm-3 Epi ID 07 P HL1036 Isotope Isotope 7.5e15 LiU 08 P HL1006 Natural Natural 9.3e15 Pe1 0485n The first batch of 1.2kV class JBS diodes based on OSIRIS material has been successfully fabricated by ASCT Measurements are underway

19 First batch of 10kV PIN diodes Example of Ascatron contribution Batch D628: 2A/10kV PiN diodes Wafer ID Epi0: n+substrate Epi1: n-drift Epi2: p+/p++ 100µm 100µm Epi ID 2.5µm 01 P HL1023 Isotope Natural Pe1 0516n Natural 02 P HL1022 Isotope Natural Pe1 0529n Natural 03 P HL1011 Natural Natural LiU Natural 04 P HL1009 Natural Natural Pe1 0530n Natural 05 P HL1039 Isotope Isotope LiU Natural The first batch of 10kV class HV-PiN diodes based on OSIRIS material has been successfully fabricated by ASCT

20 First batch of 10kV PIN diodes Example of Ascatron contribution D628W01 Forward IV 0.4 Reverse IV D628W I f (A) I r (µa) V f (V) V r (kv) Row I 4V contour map - D628W I 4V (A) Row V BR map - D628W V BR (kv) Column Column

21 First batch of 10kV PIN diodes Example of Ascatron contribution Cumulative Frequency (%) I 4V cumulative plot - Square diodes W1 W2 W3 W4 W I 4V (A) Cumulative Frequency (%) D628 Breakdown voltage cumulative plot V BR (kv) Wafer level electrical measurements completed: Targeted device specs achieved OSIRIS material is suitable for fabrication of HV devices No influence of isotope pure layers on static I-V (as expected) D628W01 D628W02 D628W03 D628W04 D628W05 Full device characterisation possible after dicing and packaging Devices will be provided to the partners for further characterisation The goal is to investigate the influence of the isotope pure SiC on the device performance

22 GaN HEMT Results : 0.15µm Ka-band technology Example of III-V lab contribution PE-CVD passivation Gate ICP-CVD passivation Source Drain InAlGaN AlN Interlayer GaN Nid 2DEG H 21 ² Vds=10V Vds=20V AlGaN Back-barrier GaN - nid (1.6 µm) MSG/MAG AlN Nucleation OSIRIS SiC LIU SiC N+ TS924 : 2x50x0.15µm² Small signal RF performances shows F T =75 GHz and Fmax=100 Vds=20V MSG 30 GHz = 13dB Similar results are obtained on SI-SiC substrate

23 GaN HEMT Results : 0.15µm Ka-band technology Example of III-V lab contribution Power 30GHz (CW) measured from Vds=15V and up to 38V : Pout ranging from 2W/mm to 2.8W/mm. Very low leakage current < 70µA/mm is achieved Output power suffers from non optimum passivation scheme: Improvement underway (not related to OSIRIS Substrate)

24 SUMMARY Isotopes and their properties OSIRIS Objectives OSIRIS Project Topics Main results of the T0+24 Substrate and thermal measurements at substrate level Device processing : Diodes and GaN HEMT Material and device characterization Conclusion

25 Analysis Method and Tool Adaptation to GaN Devices Example of Intraspec Technologies Contribution Wire soldering Resin potting Flat Polishing External wire soldering Ready to analysis Backside view Device preparation allowing a view of the device during operation from the back side.

26 Device characterization : Example of Intraspec Technologies Contribution Achievement of Lock-in Thermography and Magnetic Microscopy Example of VI23 device (13µm SiC remaining) Magnetic Microscopy (highest resolution) Vgs(ac)= -1V Vgs(dc)= -1.5V Igs(ac)= 960µa pkpk Igs(dc)= -5.3mA Magnetic pixel 0.5µm Freq : 95kHz WD: 0µm (contact with SiC) Lock-in thermography Vgs= -0.5V Igs= 2mA Vd : Floating Freq= 87Hz Emission microscopy imaging Vgs= -1.5V Igs= 5.4mA 50s Recombinations are localized along the gate length of devices Both techniques are complementary to investigate degradation mecanisms

27 Device characterization : Example of CIMAP Contribution ANALYSIS on GaN HEMT devices Localisation of the parasitic emission using IR thermography

28 Device characterization Example of CIMAP Contribution TEM ANALYSIS on GaN HEMT devices (TS837 - AJS 2x50) Gate adhesion problem is identified

29 Device characterization (M15-M36) Example of CIMAP Contribution FIB+HRTEM analysis of GaN/SiC HEMT Accurate localisation along gate length and along gate width and HRSTEM analysis at atomic level. L W Gate along w axis EMMI defects = voids

30 Device characterization : Example of STUBA Contribution Electrical defects characterization Investigation of deep energy levels in AlGaN/GaN HEMT structures by DLTFS (Deep Level Transient Fourier Spectroscopy) method with electrical excitation ln (.V th.n C ) HT4 HT3 HT2 HT1 ET3 ET2 ET1 AlGaN/GaN set trap E T T 02 ET ev 2.1E-15 cm2 04 ET ev 7.0E-15 cm2 05 ET ev 1.6E-15 cm2 06 ET ev 2.3E-15 cm2 07 ET ev 1.4E-15 cm2 06 ET ev 1.7E-15 cm2 06 ET ev 2.9E-16 cm2 02 HT ev 9.3E-17 cm2 03 HT ev 1.3E-16 cm2 05 HT ev 1.3E-16 cm2 03 HT ev 2.5E-17 cm2 03 HT ev 6.0E-15 cm2 07 HT ev 1.4E-14 cm /T (1/K) Parameters of identified deep energy levels with reference data Trap ΔE T (ev) σ T (cm 2 ) Possible origin: ET in undoped non-polar n-gan films with a high density of stacking faults and dislocations ET native donors associated with Ga interstitials ET linear array of defects due to dangling bonds along edge dislocations, N-rich growth conditions HT unknown origin HT unknown origin HT gallium vacancies and residual oxygen donors HT carbon interstitial defect DLTS signal (ff) measured simulate ET ev 2.1E-15 cm2 ET ev 1.7E-15 cm2 ET ev 2.9E-16 cm2 HT ev 9.3E-17 cm2 HT ev 1.3E-16 cm2 HT ev 2.4E-17 cm2 HT ev 1.4E-14 cm2 T W = 1 s, t p = 2 s, U R = -3.1 V, U p = -1 V AlGaN/GaN Temperature (K) DLTS signal (ff) DLTS signal (ff) measured simulate ET ev 2.1E-15 cm2 HT ev 9.3E-17 cm2 HT ev 1.3E-16 cm2 HT ev 2.4E-17 cm2 HT ev 1.4E-14 cm2 T W = 0.2 s, t p = 0.2 s, U R = -3.1 V, U p = V Temperature (K) measured simulate ET ev 2.1E-15 cm2 HT ev 9.3E-17 cm2 HT ev 1.3E-16 cm2 HT ev 2.4E-17 cm2 HT ev 1.4E-14 cm2 T W = 2 s, t p = 2 s, U R = -3.3 V, U p = V AlGaN/GaN Temperature (K) AlGaN/GaN

31 Conclusion OSIRIS project offers to Europe a chance for a disruptive approach to SiC semiconductor material elaboration. It covers the full SiC supply chain from isotope extraction, SiC substrate growth and epitaxy. 4 (100mm) substrates are developed directly to respond to current market. SiC substrate and homoepitaxy are developed to realize high voltage PiN and Schottky diodes. These new substrates are validated also by GaN epitaxies on top of reference and isotopic SiC substrates. GaN HEMT technology will be to use to validate these new substrates for GaN technology suitability. Thermal assessment at SiC substrate level shows improvement of thermal conductivity of 20%. Up to now, similar electrical properties for both diodes and HEMT compared to natural and isotopic SiC were obtained.