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1 Risbud, D., Pedrotti, K., Power, M., Pomeroy, J., & Kuball, M. (2015). Thermal characterization of high voltage an-on-si Schottky Barrier Diodes (SBD) for designing an on-chip thermal shutdown circuit for a power HEMT. In Proceedings of WiPDA Early version, also known as pre-print Link to publication record in Explore Bristol Research PDF-document University of Bristol - Explore Bristol Research eneral rights This document is made available in accordance with publisher policies. Please cite only the published version using the reference above. Full terms of use are available:

2 Thermal characterization of high voltage an-on-si Schottky Barrier Diodes (SBD) for designing an on-chip thermal shutdown circuit for a power HEMT D. M. Risbud, K. Pedrotti Dept. of Electrical Engineering University of California, Santa Cruz Santa Cruz, CA, USA drisbud@soe.ucsc.edu, kdp@soe.ucsc.edu M. Power, J. W. Pomeroy, M. Kuball Dept. of Physics University of Bristol Bristol, UK maire.power@bristol.ac.uk, james.pomeroy@bristol.ac.uk, martin.kuball@bristol.ac.uk Abstract Thermal characterization of large multifinger AlaN/aN Schottky Barrier Diodes (SBDs) fabricated on an-on-si high voltage power substrates is reported. An accurate thermal model was developed for the device structure to estimate the device temperature near the 2-DE in HEMT switches for various power densities. Raman thermography and infrared imaging were used under DC bias conditions for temperature measurement and mapping of heat distribution in the devices. Temperature rise vs. power density, and temperature rise vs. device area are presented. The assumption of uniform temperature distribution throughout the channel holds well for smaller power devices typically used in microwave and RF circuits. However, for the substantially larger high voltage power diodes and HEMTs used in automotive, power conversion and motor drive applications, the temperature distribution is not homogeneous from the center of the die to the outer edge. Detailed knowledge of the temperature distribution across the die is essential for system level thermal management. Thermal simulation, characterization results and the temperature coefficient of the sense SBD are used to design a novel self-protecting thermal shutdown circuit integrated with a discrete 600V power HEMT. Keywords AlaN, an-on-si, power HEMT, Raman thermography, IR imaging, Heat distribution, Electrothermal modelling, Thermal shutdown, Reliability I. INTRODUCTION In recent years, there has been significant progress in developing heterojunction an power transistors on silicon substrates. While an-on-si transistors have several performance advantages over silicon MOSFETs, the selfheating effect under high power dissipation conditions has a serious impact on device performance such as V th shift, higher leakage current, and drain-current collapse. It also increases reliability risk due to material degradation such as nitride or other dielectric breakdown. Instantaneous di/dt and dv/dt transients may cause rapid heating of the power HEMT during switching in applications such as automotive, power conversion and motor drive. Compared to the RF and microwave devices, high voltage power HEMTs ( V) use a large number of gate fingers (or anode and cathode fingers in case of diodes) in the layout to achieve the high voltage and current operation. However, such large designs with compact layout to save die area run the risk of thermal crosstalk between the fingers, and the enhanced selfheating effect may lead to damage or destruction of the device. We propose an on-chip thermal shutdown selfprotection circuit for a high voltage power HEMT. In order to design such a circuit, it is essential to quantify the channel temperature rise and map the thermal gradient across the device during operation. In this work, we report temperature measurements and observations for an diodes on silicon substrates with dimensions much larger than typically found in the literature. This study used large area diodes instead of HEMTs for ease of fabrication and measurement. They were fabricated on same an material as used for power HEMT allowing the measurement of the expected thermal parameters and profiles. Thermal simulations were performed using a model developed for the device under test, and micro-raman thermography was used for experimental measurements to validate simulation results. Infrared imaging was used to obtain thermal mapping of the device for various power dissipation levels. II. SELF-HEATIN IN AN-ON-SI POWER HEMTS Thermal cross-talk (inhomogeneous temperature distribution from finger to finger) studies have been reported over the years [4], [5] for RF and microwave devices, primarily on SiC substrates. an on silicon substrates for high voltage power devices is an emerging technology and such detailed studies are still underway [7]. Several theoretical models for channel temperature estimation have been proposed in the RF an area [2],[3],[11], but their accuracy can be limited by material properties and simplifying assumptions based on empirical results often obtained from single-finger or smaller devices. Until now, thermal analysis and measurements often assumed that the temperature stays uniform throughout the device for a given power dissipation for typical device layouts. Kuball et al. have reported differentiation between the contribution of the fingers at the center of the die and contribution from the fingers away from the center, observing that thermal gradients are larger in larger devices. [1],[5] It has also been reported [8] that the outer fingers of a microwave

3 device are the coolest for device dimensions of L g = 0.25μm, W g = 250μm, gate pitch (s) = 25μm. In that analysis it was assumed that the dissipated power generates a constant heat flux directly under the gate. Furthermore, in Darwish et al., the silicon substrate was assumed to have constant thermal conductivity whereas in reality, is temperature dependent [1],[2]. resistance between the Si wafer and the thermal chuck. For the 8A diode, ΔT was found to be significant across only / /. III. DEVICE STRUCTURE AND SIMULATION The diodes characterized in this work are fabricated using an AlaN/-aN-on-Si Schottky gate process technology. The epitaxial structure is grown on a <111> silicon substrate and consists of a transition layer and a series of AlaN/aN buffer layers forming a superlattice, followed by AlCu layer for the top metal. Ohmic contacts are Ti/Al while Ni is used for Schottky contacts due to its high work function. Two Al metal layers are used for interconnect and for high current routing. The most common device layout is based on a comb like structure with interleaved gate fingers, all identical in length and width. The design methodology is the same for a HEMT (Source, ate, Drain) and a diode (anode and cathode electrodes) since both are designed in Schottky technology. Finite element thermal simulations of the 1A, 2A, 4A and 8A diodes using ANSYS were carried out to compare simulated and experimental middle and edge channel temperatures and temperature distributions of the devices. As shown in Fig.1, the model required only a quarter of the device (A) due to symmetry. It is placed on a 1.5mm x 4mm epilayer structure consisting of a 1.5μm-thick an/3.45μm-thick AlaN/aN superlattice and AlN (B). The 240μm-thick Si substrate (C) spanned the 49cm 2 area of the 1 cm-thick thermal chuck (E) to simulate the fabrication of the devices on a 6 Si wafer. A thin layer (D) was included between the Si substrate layer and thermal chuck to simulate the thermal resistance between the an device and the thermal chuck that occurs in measurement. The thermal conductivity of this layer was chosen by matching the simulated Si temperature at the point 300µm (greater than substrate thickness) away from the device to the experimental data. The thermal conductivity of the metal chuck and fingers modeled as gold, Si substrate and an layer were fixed at 400Wm -1 K -1, 119Wm -1 K -1 [12] and 160Wm -1 K -1 respectively at 25 0 C [1][2]. The thermal conductivity of the an layer and Si substrate were given a temperature dependence of T -1.4 and T -1.3 [3] respectively A thermal conductivity of 30 Wm -1 K -1 with a temperature dependence of T -1.4 was used [13] for the AlaN/aN superlattice employed as a strain relief layer. The largest contribution to the temperature rise comes from the thermal Fig. 1: Thermal model layout of 1A device (A) on epilayer structure; 1.5μm-thick an/3.45μm-thick AlaN/aN superlattice and AlN (B) which rests on a 240μm-thick Si substrate (C). There is a 1 μm-thick layer (D) between the Si substrate and thermal chuck (E), which represents the thermal resistance between these parts. Inset: Device layout showing heat flow equal to power dissipated applied to 2D heaters in an channels between the anode and cathode fingers. the silicon layer while ΔT is insignificant across all layers of the superlattice for the 1A, 2A and 4A diodes. The thermal chuck was set to a temperature of 24 C. To simulate diode power dissipation at the three power densities used experimentally, a heat flow equal to the power dissipated in the device was applied to 2D heaters within the an channels between the anode and cathode fingers shown in Fig. 1 (inset). IV. MEASUREMENTS AND OBSERVATIONS Raman thermography was used to obtain submicron resolution temperature information in the 2-DE at various power levels, and IR imaging was used for thermal mapping across the die [10]. The device was held at a controlled 24 o C on a chuck and biased under DC conditions. The Raman thermography technique was preferred for determining device temperature over electrical methods because the temperatures measured by electrical methods average over the entire active region of the device and thus tend to underestimate the peak temperatures in the channel. Raman Thermography exploits the temperature dependence of phonon frequencies to determine the channel and substrate temperature of the device. It is a noninvasive, non-destructive temperature measurement technique based on the Raman peak shift due to the temperature change. The measurements are highly repeatable and the technique is widely used in modern experimental research. The technique has a temperature accuracy of ±5-10 C and spatial resolution of better than 1μm [3]. Single spot and scanned measurements were performed. IR thermal imaging is suitable for investigating the temperature distribution within an AlaN/aN-on-Si device but has its challenges for accurately

4 measuring the absolute temperatures because the Si substrate is transparent to the IR radiation [5]. The temperature coefficient of an SBD was measured (Fig.2) to be -1.95mV/ 0 C, similar to that of a planar silicon diode. Therefore, SBDs can be used as the temperature sense elements. In the layout floor plan of a HEMT with on-chip thermal protection circuit, it is best to place the temperature sense diodes at a location where the heat rise is the quickest. This is to capture the onset of heat rise as quickly as possible and activate the protection circuit. To identify the ideal location for placement of sense diodes to observe a significant temperature rise, large gate width an diodes with 1A, 2A, 4A and 8A current ratings operating under DC bias conditions well beyond the turn-on voltage were used. Thermal crosstalk between the fingers was investigated by measuring the temperature in the non-active area between the anode and cathode fingers. Fig.3 shows discoloration in the center of the 4A and 2A diodes after operation of the device above the recommended maximum current level. This is heat-induced damage. For the same time scale of 100μs and relatively the same power density, the smaller 1A diode did not show any damage while the metal damage on the large device was observed to progress with time. Temperature difference between the middle and edge channel ΔT vs Device Size and Peak Temperature vs Power Density of the diodes obtained by Raman thermography are shown in Fig.s 4 and 5 respectively. Figs. 6-8 show the simulated and experimental results of temperature difference (between the center and the edge) versus power dissipation and IR images of 1A, and 8A diodes. There is good agreement between measured and simulated values for the 1A, 2A and 4A diodes. A 13 0 C discrepancy was observed at high power density (0.3W/mm) between the simulation and measured values for the 8A diode. This could be due to current redistribution across the large diode, either due to current spreading in the metal, or the temperature dependent electrical resistance in the 2DE channel. However, this agreement is still good within the margin of error. In other words, the larger the device, the larger possible electro-thermal effects may be. Nevertheless, reasonable agreement with the simplified thermal model was obtained. 8A Fig. 3: Thermally induced damage on 8A and 4A diodes ΔT ( C) Fig. 4: ΔT vs Device Size 4A W/mm 0.2 W/mm W/mm 1A 2A 4A 2A 8A Die size (mm) Device size Fig. 5: Peak Temp. vs Power Density Fig. 2: Temperature coefficient of an SBD The experiments on several devices quantitatively confirmed that the central fingers do indeed heat up the most. Measurements indicate that the temperature difference between the center of the die and edge of the die can be as high as 60 0 C at the high power densities considered here. The absolute temperature in the channel was measured at a peak of C, which is substantially higher than the typical

5 commercial rating of C for Si MOSFETs. The high temperature measured is mostly due to the high thermal resistance R th between the wafer and the chuck. With a solder die attach, the temperature would be substantially lower. Even though an-on-si devices are expected to be able to operate at temperatures higher than Si MOSFETs, the peak temperature may be limited by the choice of package. The relationship between the total power dissipation and R th is given by 25 Thermal model (1/4) of device at 0.2 W/mm Fig.7b: 8A Diode thermal model at 0.2W/mm Δ Δ where number of fingers and = power density in each finger. L = Simulation and Experimental results of 1A and 8A Devices IR image (¼ of device) at 0.2 W/mm Thermal model (¼ of device) at 0.2 W/mm J p Temperature ( C) Raman Thermography 0.1 W/mm 0.2 W/mm 0.3 W/mm Simulation 0.1 W/mm 0.2 W/mm 0.3 W/mm Middle channel Edge channel Middle channel Edge channel Fig. 8 Temperature drop from middle to edge channel significant at 0.3W/mm Fig.6: 1A Diode IR Image and thermal model. Temperature uniform from middle to edge channel IR image of ¼ device at 0.2 W/mm Fig.7a: 8A Diode IR Image at 0.2W/mm. Temperature non-uniformity significant Fig.9: Alternative layout concept

6 Source D A T e Drain an SBD PTAT Voltage an Comparator an Level Shifter an Source S ate an integrated circuit Fig. 10: Square-gate layout [14] Experimental results indicate that the device design and layout may need to achieve a more controlled current flow to enable constant temperature over the whole device area. This may be of benefit because the output power of a high voltage HEMT scales with the number of fingers in the layout. By designing the fingers of different widths such that the power dissipated in the central and lateral fingers is less uniform, the localized thermal heating in the center part of the device can be reduced. This concept is illustrated in Fig.9. An alternative is the square gate layout [14] shown in Fig.10. Applied voltage, the number of fingers and the finger pitch determine the maximum temperature rise in a device. It is worth noting that there is a trade-off between area, capacitance and thermal uniformity when optimizing for minimum selfheating. The heat distribution profile obtained from the measurements confirmed that the ideal location for placement of sense diodes is at the center of the die. V. THERMAL SHUTDOWN CIRCUIT Two different circuits for thermal shutdown to be integrated with the power HEMT have been designed as illustrated in Fig. 11 and Fig.12. Both versions have been designed using only depletion modes transistors, SBDs and passives. The version in Fig.11 uses a comparator to generate a threshold temperature flag by comparing a voltage output generated by SBD based PTAT (proportional to absolute temperature) voltage generator to a precision voltage reference. The output voltage of the comparator is then level shifted to an appropriate negative voltage to turn off the gate of a normallyon (depletion mode) an HEMT. An alternative, more complex hybrid circuit is shown in Fig. 13. In this approach, the sense circuit uses SBDs to sense the temperature and generates a square wave using a self-starting oscillator circuit. As the temperature increases, the frequency of the square wave increases. When the temperature reaches a threshold, the corresponding frequency is converted to voltage and level shifted down to shut off the gate of the an Fig.11: HEMT with PTAT based on-chip active thermal shutdown circuit Fig.12: Comparator simulation plot SBD SBD an Bistable an integrated circuit F/V Converter Level Shifter Off-chip components Fig.13: An alternative thermal shutdown circuit HEMT. Only the temperature sense and square wave generator part of the circuit was implemented on-chip, while the frequency-to-voltage converter, level shifter, and an HEMT circuit was off-chip, implemented on a printed circuit board. an

7 D T-Sense Fig.14: Power HEMT floor plan with thermal shutdown The circuit illustrates the concept and is part of future experiments in integration. Fig.14 is the floor plan of the thermal shutdown circuit integrated with the power HEMT in an 8x8 ThinPak package. CONCLUSION Thermal profiles of large geometry an-on-si power diodes are presented. A thermal model was developed based on the device structure to simulate the temperature in the 2- DE for various power densities. The temperature gradient across the die was experimentally measured. The experimental results are in good agreement with simulation for 1A, 2A, 4A and 8A diodes. Temperature measurements confirmed that the ideal location for the temperature sense diodes is at the center of the die where heat rise is the largest. Results from this work were used to design an on-chip active thermal shutdown circuit. Future work is in progress to experimentally demonstrate the operation of the integrated thermal shutdown circuit used to put the power HEMT in both sleep and wakeup modes. ACKNOWLEDMENT This work was supported in part by EC ECSEL (European Commission Electronic Components and Systems for European Leadership) and E 2 coan (Energy Efficient Converters using an Power Devices) projects. The author would like to acknowledge NXP Semiconductors (UK) for their support in device design and fabrication. REFERENCES [1]. Kuball, M., Hayes, J. M., Uren, M. J., Martin, I., Birbeck, J. C. H., Balmer, R. S., & Hughes, B. T. (2002). Measurement of temperature in active high-power AlaN/aN HFETs using Raman spectroscopy. Electron Device Letters, IEEE,23(1), 7-9. [2]. Sarua, A., Bullen, A., Haynes, M., & Kuball, M. (2007). High-resolution Raman temperature measurements in aas p- HEMT multifinger devices. Electron Devices, IEEE Transactions on, 54(8), S S Thermal Shutdown Circuit [3]. Sommet, Raphael, et al. "Thermal modeling and measurements of AlaN/aN HEMTs including thermal boundary resistance." Microelectronics Journal 43.9 (2012): [4]. Manoi, A., Pomeroy, J. W., Lossy, R., Pazirandeh, R., Würfl, J., Uren, M. J.,... & Kuball, M. (2011). Timedependent thermal crosstalk in multifinger AlaN/aN HEMTs and implications on their electrical performance. Solid-State Electronics, 57(1), [5]. Sarua, A., Ji, H., Kuball, M., Uren, M. J., Martin, T., Hilton, K. P., & Balmer, R. S. (2006). Integrated micro- Raman/infrared thermography probe for monitoring of selfheating in AlaN/aN transistor structures. Electron Devices, IEEE Transactions on, 53(10), [6]. Joh, J., del Alamo, J., Chowdhury, U., Chou, T. M., Tserng, H. Q., & Jimenez, J. L. (2009). Measurement of channel temperature in an high-electron mobility transistors. Electron Devices, IEEE Transactions on, 56(12), [7]. Ohno, Y., Akita, M., Kishimoto, S., Maezawa, K., & Mizutani, T. (2002). Temperature distribution measurement in AlaN/aN high-electron-mobility transistors by micro- Raman scattering spectroscopy. Japanese journal of applied physics, 41(4B), L452. [8]. Darwish, A. M., Bayba, A. J., Khorshid, A., Rajaie, A., & Hung, H. A. (2012). Calculation of the nonlinear junction temperature for semiconductor devices using linear temperature values. Electron Devices, IEEE Transactions on,59(8), [9]. Ambacher, O., Smart, J., Shealy, J. R., Weimann, N.., Chu, K., Murphy, M.,... & Hilsenbeck, J. (1999). Twodimensional electron gases induced by spontaneous and piezoelectric polarization charges in N-and a-face AlaN/aN heterostructures. Journal of Applied Physics, 85(6), [10]. Sarua, A., Pomeroy, J., Kuball, M., Falk, A., Albright,., Uren, M. J., & Martin, T. (2008, July). Raman-IR microthermography tool for reliability and failure analysis of electronic devices. In Physical and Failure Analysis of Integrated Circuits, IPFA th International Symposium on the (pp. 1-5). IEEE. [11]. Mimouni, S., Saidane, A., & Feradji, A. (2008). Transmission-line-matrix (TLM) modeling of self-heating in AlaN/aN transistor structures. Microelectronics Journal, 39(10), [12]. lassbrenner, C. J. and. A. Slack, Phys. Rev. 134, 4A (1964) A1058-A1069 [13]. Liu, W., Balandin, A.A. (2004), Temperature dependence of thermal conductivity of Alx1-xN thin films measured by the differential 3ω technique. Applied Physics Letters, 85(22), [14]. Lin, Y. S., Lian, Y. W., Yang, J. M., Lu, H. C., Huang, Y. C., Cheng, C. H., & Hsu, S. S. (2013). Contact engineering of an-on-silicon power devices for breakdown voltage enhancement. Semiconductor Science and Technology, 28(7),