FRACTURE IST Nanoelectronic Devices and Fault-Tolerant Architectures

Transcription

1 FRACTURE IST Nanoelectronic Devices and Fault-Tolerant Architectures DRAFT of Final Report Covering period Report Preparation Date: Classification: Restricted Contract Start Date: Duration: 36 months Project Co-ordinator: IMEL/NCSR Demokritos (GR) Partners: TIMA/UJF (FR), Un of Durham (UK), iroc Technologies (FR) Project funded by the European Community under the Information Society Technologies Programme ( )

2 1. EXECUTIVE SUMMARY The aims of the FRACTURE project are: - To demonstrate the feasibility of a flash type memory device fabricated by a hybrid silicon and molecular technology. - To demonstrate the feasibility of such a device in a 3-D architecture. - To develop fault-tolerant algorithms that can tolerate a great number of defects expected in the above technologies. To enable the development of this technology FRACTURE has been divided in 4 main tasks. Task 1: Development of the fault tolerant algorithms suitable for circuits with high defect densities. Task 2: Development of the necessary silicon infrastructure that will allow the 3-D integration scheme. Task 3: Development of the molecular material technology to be combined with the silicon infrastructure for the deposition of thin organic insulating films including metallic or semiconducting nanoparticles. Task 4: Demonstration of memory devices by combining the above technologies. The main achievements obtained within FRACRURE are: To demonstrate fault-tolerant architectures for non-volatile memory circuits. In order to cope with the defect densities that could be encountered in future nanotechnologies, (up to a few percent of faulty cells) we have developed and explored different approaches for repair principle based on Reconfiguration Functions. The evaluations performed show that these approaches allow to achieve close to 100% yield by means of moderate hardware cost. Thus, these architectures pave the way to new low-cost, low power dissipation and highdensity memory fabrication technologies, that could be affected by very high defect densities. To deposit semiconductive and metallic nanoparticles onto surfaces following different techniques: (a) the Langmuir-Blodgett (LB) technique was used to define nanometre-size II-VI semiconducting CdS particles distributed in a fatty acid matrix. LB of fatty acid salts were first deposited in the normal way. Nanoparticles were then formed by exposing the multilayer film to an H 2 S atmosphere; (b) nanoclusters of Au, Pt and CdS capped with organic ligands were deposited by the LB technique; and (c) gold nanoparticles passivated with organic ligands were self-assembled onto functionalized surfaces To demonstrate a non-volatile memory device using gold nanoparticles room temperature deposited over a conventional silicon device. The nanoparticles were either deposited by chemical processes and surface functionalization of the underlying silicon dioxide layer or by means of the Langmuir-Blodgett technique. To achieve that different technologies had to be efficiently integrated. Using different insulating materials between the nanoparticleslayer 2

3 and the gate charging of the nanoparticles has been achieved either from the gate electrode or the device channel region. To demonstrate a 3-D memory device formed by low temperature wafer bonding technique and pre-formed S/D and channel areas separated after bonding by anisotropic etching. Nanoparticles were deposited using above described technologies. The consortium consists of IMEL/NCSR Demokritos that focuses on the silicon technology aspects and the integration concept, Un. of Durham that brings in its expertise on molecular materials, iroc a start-up company and TIMA laboratory that both specialize on fault-tolerant IC design. 2. PROJECT OBJECTIVES The evolution of microelectronics the major enabling technology of the information revolution is threatened by not only technical issues that may limit the further miniaturization of ICs but also from the increased fabrication cost that accompanies shrinking of feature sizes below 100 nm. To overcome these limitations a worldwide research effort aiming at devices that go beyond conventional device architectures is underway. A major issue related with the new types of devices is their relatively poor fabrication yield resulting from problems such as the influence of background charge, difficulties to make reliable contacts to these devices and lithographic inaccuracies when it comes to the nanometer level. Although it is expected that some solutions to the above problems could be found through research it seems intuitively difficult to find such solutions at the device level without an increase of the fabrication complexity and thus of the cost. A reasonable consequence of the above is that the search for an alternative to the expensive but very robust conventional MOS technology in the form of a much less expensive but less robust technology should be accompanied by fault-tolerant schemes, permitting the functionality of the chips even if some of the devices are not even operational. A good example of such an approach has recently seen the light of publicity. It is about the Teramac computer that it was designed and fabricated at a macroscale level by HP in USA [HEA98]. This system is based on a high redundancy of interconnecting wires that connect unreliable switching devices -made up from 6 transistor configurationso that even if some of the paths contain non operational devices there is always one functional path. Our direction within the project will be the exploitation of fault tolerant techniques in memory arrays. Memories represent by far the largest part of electronic systems. It is today very common to have ASICs where the memory represents more than 50% of the of the total area and more than 80% of the total transistor number (memories in Pentium chips occupy more that 70% of the area). The memory to logic ratio increases drastically if one considers the whole system. Also because memories are designed to be as tight on the technology as is permitted by the physical limits of the technology they are more prone to failures than standard logic. Memories therefore collect the larger amount of defects of an IC and become the main cause of both quality reduction (high defect level) and yield losses. This problem will worsen dramatically in nanometer technologies. Due to the high complexity of memory parts 3

4 and the poor fabrication yield of the target technologies, reliability issues will block the introduction of new technologies if not addressed properly. Fault tolerance is therefore mandatory. In FRACTURE we propose a strategy to implement memory devices that can be fabricated at a lower cost than current CMOS technology. For their fabrication we combine silicon nanofabrication techniques that are realized by optical lithography - avoiding e-beam lithography or other serial lithographic techniques- and molecular electronic devices. The principle of our memory device is similar to floating-gate flash memories. Since memory cells are accompanied by read out electronics and logic units we propose that these circuits be fabricated on a substrate wafer together with the interconnects that address the memory devices. The memory devices are personalized on a thin Si film after bonding and removal by selective etching of a Silicon-On- Insulator wafer on top of the prefabricated CMOS circuit using 'cold' processes that will not affect the underlying materials. The proposed process offers the flexibility of high alignement capability since it allows a mask-to-mask alignement between the prefabricated circuits on the substrate wafer and the hybrid Si-molecular devices on the thin Si film. In addition the process respects compatibility between CMOS and molecular device technology since the molecules could not withstand neither CMOS metallization steps nor annealing conditions to strengthen the bonding ( C). The proposed technology for building the memory devices is prone to a high defect density. Fault-tolerant approaches use redundant resources to ensure correct operation when the regular resources are affected by a fault. Traditional fault-tolerant approaches address situations where a few faults affect the circuit under consideration. In particular, it is supposed that faults cannot affect both regular and redundant resources. For high defect densities both functional and redundant parts will be affected by defects. Thus, using only redundant parts to replace defected functional parts, as in traditional memory repair architectures, may become unfeasible. To cope with this problem, new approaches will be investigated. Repairing a very large number of defects will require a significant area for implementing the reconfiguration circuitry. This circuitry can be implemented into a mainstream CMOS process. The implementation of this circuitry may increase the size of the die. One of the advantages of the proposed 3-D approach is the availability of the substrate providing a large silicon area for implementing various functions. This area can be used to implement, the reconfiguration circuitry, the peripheral circuits of the memory (decoders, multiplexers, amplifiers, read/write logic), as well as complex processing systems such as processor cores, CACHEs and peripherals, resulting on complex Systems-on-a-Chip, with very large nonvolatile memory capacities. Summarizing the initial major objectives of FRACTURE were: 1. Develop a new inexpensive technology for the fabrication of non-volatile memories based on hybrid silicon and molecular nanotechnology and combine 4

5 it with mainstream CMOS using wafer bonding at low temperature to make 3- D stacks. 2. Develop fault-tolerant architectures suitable for low yield non-volatile memory device fabrication processes. 3. Develop high throughput nanofabrication techniques using optical lithography and self limited etching techniques for Si nanostructure fabrication. 4. Investigate molecules used as room temperature charge storage elements and integrate them on top of a Si channel to demonstrate a non-volatile nano-flash memory device. 5. Demonstrate a molecular channel nano-flash memory device. 3. METHODOLOGIES TO ACHIEVE PROJECT OBJECTIVES New fault-tolerant architectures (objective 2) Memory repair is usually performed by using fuses programmed by external means such as laser beam, electron beam, or by electrical programming performed by the memory tester. These means allow disconnecting a faulty regular unit (usually a column) and connecting at its place a spare unit. The external repair approach has several drawbacks that are magnified in the case of large embedded memories, which are very common in modern chips such as the SOCs. Some of these drawbacks are: - the cost of the repair phase that needs some specific equipment, - the large area occupied by the fuses, which becomes critical if we need to repair a significant number of faults, - the cost of the test phase, since it requires a memory tester in addition to the logic tester in case we need to test a SOC, - the difficulty for localizing the faults in embedded memories, due to their limited access (controllability and observability), - the limitation of the approach to the repair fabrication defects but not faults occurring in the field. - The high area occupied by the fuses or antifuses, which make the approach impractical if we have to repair a large number of faults. Built-in self-test (BIST) is becoming today the dominant memory test approach, especially for embedded memories. The next step on this trend consists to integrate the repair mechanisms in the chip resulting on a built-in self-repair (BISR) scheme. This approach will allow eliminating the cost of the external equipment, simplifying the fault localization (since a BISR mechanism will have direct access to the embedded memory), eliminating the fuses, and repairing both fabrication faults and field faults (since the BISR can be activated at any time during the circuit life). Due to these advantages and considering that the large area of a fuse is not acceptable in the case of a large number of faults, it becomes obvious that external repair is not adequate for solving the problems addressed in this project. Therefore, in this project the main work was oriented towards a BISR approach. Built In Self Repair can be used to repair defects affecting memory cells, decoders, read and write amplifiers, column multiplexes, and data input and output 5

6 latches. Various BIST approaches are possible. Row (or word) BISR uses spare rows (or words) to replace defected regular rows (or words). Column (or data bit) BISR uses spare columns (or sets of columns generating a spare data bit) to replace defected regular columns (or sets of columns generating a regular data bits). Data repair can repair faulty cells as well as faulty column-muxes, faulty read or write amplifiers, and faulty data input/output registers. Repairing read amplifiers may improve yield significantly, since sense amplifiers are very sensitive circuits and can be faulty more frequently than other memory parts. On the other hand, row repair cannot repair the above-mentioned faults, and performs repair poorly for faults affecting the address decoders. In fact, row repair approach can repair some row decoder faults, but has limited efficiency for such faults. The majority of row decoder faults can activate or deactivate a large number of word lines, requiring a large amount of spare rows for repairing just a decoder faults. Also, even if a fault, like a stuck-at, activates a single word line, the activation can be permanent. Thus, using row repair for repairing such a fault will require replacing all the memory rows by spares. Row/word repair is the simplest BISR approach, so, the majority of the work done in BISR considers this scheme, although column repair was used predominantly by the industry due to the described advantages. Word repair was early proposed by K. Sawada et al [SAW99]. The characteristics of this work are the following: it uses a content addressable memory storing the data and addresses of the faulty locations and considers low numbers of faults. Also, faults in the spare parts are not taking into account. Subsequent work on row BISR [TAN92] [BHA94], [BEN00] consider implementation aspects of the approach, but they do not bring any innovative ideas. They consider a low number of faults (e.g. two faults in [BHA94]), and no faults in the spare units. Work on row/data BISR is more recent due to the difficulty for elaborating the reconfiguration functions. I. Kim et al [KIM98] propose a scheme where the reconfiguration information is generated by a controller and stored in a memory. To master the complexity of the reconfiguration process, the scheme repairs a single fault per test phase. That is, the memory is tested until the first fault is found and repaired. Then, the memory is tested again until a second fault is found and repaired, and so on. This process simplifies the work of the BISR control unit, but the test and repair time becomes unacceptable when the number of faults increases. The approach does not consider faults in the spare parts (the repair fails if a spare unit is faulty), it repairs a small number of faults (e.g. 2 faulty columns out-of 128 regular columns, and results on high hardware cost (15 times more storage cells in the reconfiguration circuitry than the approach we developed in work package 1, in the first year of the FRACTURE Project). A more recent work [KYU00] considers only a particular way for connecting the MUXes used in column repair. The generation of the signals controlling these MUXes is not addressed. A last paper [KIM99] considers the combination of column and row repair. The goal is to develop an algorithm that allocates efficiently the spare rows and columns in order to repair multiple faulty cells that may affect a few columns and rows. The algorithm for such an allocation makes the BISR controller more complex than in other BISR approaches. This complexity will result on excessive cost when the number of faults is increasing. The efficiency of the method is evaluated only for fault distributions that can be repaired if the spare columns and rows are corrected allocated. But such fault distributions represent a small percentage in the space of possible fault distributions. So, the yield improvement will be insignificant with 6

7 respect to a less efficient spare row/column allocation, or with respect to a row-only or column-only repair scheme. In the first and second years of FRACTURE project we proposed and developed several BISR solutions to cope with high defect densities (see Periodic Progress report No.1 and No.2). With respect to early BISR approaches mentioned above, they represent a serious innovation in this domain because: they consider high defect densities they consider faults affecting both the regular and spare elements. they perform multiple faults repair per test and repair pass they propose BISR circuitry for performing the memory reconfiguration. Some of the BISR techniques developed during the FRACTURE project are summarized below and detailed in the next section: 1. One of the approaches consider a dynamic repair approach that increases the multiplicity of repaired faults by using a single spare unit for repairing faults affecting several regular units (Periodic Progress Report No.1). 2. A diversified approach is also proposed that combine dynamic data repair scheme with block repair scheme (Periodic Progress Report No.1). 3. Another approach combines faulty units to provide a repaired unit, instead of replacing a faulty unit by a fault free one. This approach should work better for very high densities, since for these densities it becomes difficult to dispose of fault-free units. The combination it is based on the fact that in the majority of situations the faulty cells will not affect the same positions in two different units. Thanks to these principles, these techniques can handle large fault multiplicities and are suitable for memories affected by high defect densities (Periodic Progress Report No.2). 4. Another diversified approach mixes ECC codes that repair the majority of the faulty memory words with a word repair scheme that repair the words left un-repaired because they include a large number of faults (Periodic Progress Report No.2). 5. A cell level fault tolerant technique is developed. The technique exploits eventual disparities between the probabilities of faults having different error polarities, to develop fault tolerant memory cells based having a cost equal to duplication (100% extra area), instead of the standard fault tolerant solution requiring to triplicate the cell and add a voter (200% extra area). The cells can be combined with one of the techniques proposed during the previous years (e.g. combination of ECC and word repair) to achieve fault tolerance for defect densities as high as 10-1 (Periodic Progress Report No.3). 6. An architecture for memories using sequential addressing is proposed. The architecture is selected in order to allow easy repair. A word repair scheme is developed, resulting on lower cost than any other word repair scheme. The scheme is combined with error correcting codes to achieve repair for very high defect densities, at lower cost than the schemes developed during the previous years. (Periodic Progress Report No.3). Thanks to these principles, these techniques can handle large fault multiplicities and are suitable for memories affected by high defect densities. However, evaluation were performed to determine the comparative merit of these techniques with respect to memories affected by high defect densities. Evaluations have been performed by 7

8 means of statistical fault injections, and we determine the best approach for various memory sizes and defect densities (Periodic Progress Report No.1, No.2 and No.3). To achieve objectives 1,3 and 4 we have proposed and developed the following methodologies: 1. Use a silicon FET infrastructure and deposit on top of the gate oxide metallic or semiconducting nanoparticles at room temperature. Demonstrate a non volatile memory effect. This approach is a critical step to demonstrate the possibility to create room temperature deposited charge storage elements that constitute the memory nodes. 2. Develop techniques based either on chemical formation of nanoparticles and their subsequent deposition on a functionalised gate oxide surface or on nanoparticles by the Langmuir-Blodgett technique. Previous research on nanoparticles has demonstrated their ability to store charge. But most of the research effort has focused on nanoparticle formation following high temperature processes. Major efforts include silicon or germanium nanoparticle formation within an insulating matrix following techniques like ion beam synthesis [TIW96, NORM98, KAPET02] or high temperature deposition like LPCVD or MBE [SALV02, KANJ02]. More recently templated self-assembly has been demonstrated for the formation of more uniform size and density nanoparticle array [GUAR03]. I is worth mentioning that IMEL has pioneered the formation of nanoparticles by low energy ion implantation technique [NORM98]. But a denser integration scheme would most likely has to follow a 3-D approach for memory array realization. In such a scheme nanoparticles deposited at low temperatures that can control the channel of a FET device had to be proven. The room temperature nanoparticle deposition and their use as charge storage elements fills this gap compared with prior art based on the formation of nanoparticles at high temperature. Within FRACTURE the Durham group has used a wide range of thin film techniques to deposit semiconductive and metallic nanoparticles onto surfaces: the Langmuir- Blodgett (LB) method, self-assembly and layer-by-layer electrostatic deposition. During the course of the work, links were established with Professor Stephen Evans (Leeds University) and Dr Mark Green (Oxonica Ltd., Oxford) for the provision of new nanoparticulate materials. Structural information on the nanoparticle films was obtained using atomic force and electron microscopy, ellipsometry, X-ray diffraction and UV/visible spectroscopy. High quality films were incorporated in metal-insulatorsemiconductor (MIS) structures for electrical studies at Durham. Samples were also deposited onto special field effect transistor (FET) substrates produced by the Demokritos group and sent to Athens for measurements. Molecular channels were fabricated by the evaporation of pentacene at reduced pressure. Here, collaboration was formed with Cornell University to improve the quality of the FETs. It worths also reporting on other worldwide used methodologies to achieve denser memories. Researchers are investigating new materials deposited at room temperature that exhibit some type of memory behaviour and have the potential to be integrated as electronic memory arrays. It appears that there are basically two schools of approach. One is looking for a resistive bistable device and the other one on flash type 8

9 memories. Resistive memory devices have been reported by HP researchers who are investigating rotaxane molecules to be used as switches between two conducting electrodes [CHE03]. These molecules show initially a high ratio between two resistive states but this ratio degrades fastly to one state (after 95 repetitions). A similar approach using an organic/metal-nanocluster/organic sandwich placed between two metal electrodes [MA02] have also resulted to a bistable non-volatile operation that is explained by the authors by charge trapping into the metal-nanoclusters [MA03]. There are not definitive results on long term stability of the device. More recently a write-once-read-many-times device has appeared in the literature [MOL03] using a polymer that shows a fuse-like behaviour data storage as well as porphyrin molecules have been shown to keep information for some minutes have fast write erase times and good endurance characteristics [LIU03]. On the other hand carbon nanotubes have been used as FET devices on top of an oxidized silicon wafer and information has been written in the insulator layer very similarly with flash type memories [FUH02, RAD02]. A device combining carbon nanotubes with nanoparticles as charge storage elements has not been demonstrated yet. Although all these efforts are different from each other one can start identifying common elements with work developed within FRACTURE in some of them like f.e nanotubes combined with nanoparticles as charge storage or resistivity change in hybrid organic/metal-nanocluster/organic structures due to charge stored in the nanoclusters. To allow for a 3-D integration scheme we have used the following methodologies within FRACTURE: 3. Develop a low temperature wafer bonding technique to form a thin silicon layer on top of a substrate silicon wafer. 4. Develop silicon anisotropic etching techniques that allow separation of S/D areas from the channel and formation of a silicon FET infrastructure at low temperature. 5. Use methodologies 1-4 to demonstrate a 3-D memory device. The necessity for higher memory densities in future chips is actually recognized worldwide [IWFIP03] and 3-D integration of memories remains an important but difficult to achieve alternative for higher integration densities. During the duration of the project we have identified one major effort related with 3-D memory structures. This is in development in US by a company from Stanford namely Matrix Semiconductors. The technology is based on one-time-programmable memory which uses a transistorless two-terminal cell. Cells are fabricated in poly-silicon and stacked vertically in 8 layers over a CMOS substrate [JOHN03]. The raised up today funding by this company is about 100 million USD. To achieve objective 5 Molecular channels were fabricated by the evaporation of pentacene at reduced pressure. Here, collaboration was formed with Cornell University to improve the quality of the FETs. While good progress has been made on the key materials and their device processing, we have yet to achieve one objective that of demonstrating 9

10 a memory device based on an organic semiconductor. However, a number of designs have now been developed in which evaporated pentacene forms the semiconductive channel while the gate and gate insulator are provided by silicon and silicon dioxide, respectively. The nanoparticles will be deposited by both the LB method and the selfassembly technique. One further development could be to replace the silicon dioxide gate insulator with an organic (e.g. polymer) material. This work will be progressed outside the FRACTURE project. 4. PROJECT RESULTS AND ACHIEVEMENTS FAULT TOLERANCE ARCHITECTURES (WP1-2) One of the original objective of FRACTURE project concerns the developing of new fault tolerant approaches using redundant resources to ensure correct operation when the regular resources are affected by faults. Traditional fault tolerant approaches address situations where few faults affect the circuit under consideration. In particular, it is supposed that faults cannot affect both regular and redundant resources. For high defect densities both functional and redundant parts will be affected by defects. Thus, using only redundant parts to replace defected functional parts, as in traditional memory repair architectures, may become unfeasible. To cope with this problem, novel techniques are to be investigated: Built In Self Repair using reconfiguration algorithms able to cope with faults of increased multiplicity Reconfiguration functions able to combine faulty functional and spare modules to create correct ones Addressing modification able to replace large number of faulty functional modules by spare ones, using low interconnection complexity Cell level fault tolerance reducing the probability of faults affecting both functional and spare modules. With respect to these original objectives, in the following we present a description of the techniques developed within the duration of the project. Notice that all the techniques presented below have been detailed in Periodic Progress Report No.1, No.2 and No.3. These BISR architectures and the evaluation of their yield improvement and area overhead have also been submitted, accepted for presentation and therefore published in six IEEE conference proceedings so far. Reference of these papers will be given at the end of the final report. A. Static and Dynamic Built In Self Repair A BISR scheme uses spare units and means for locating the defected regular units and replacing them by spares. The regular and spare unit on which the repair is based will be named replaceable unit. A replaceable unit is a block of memory cells connected to a single input/output. The size of the replaceable unit, the complexity of the reconfiguration logic and of the routing network, and the efficiency of the repair algorithm will determine the overall efficiency of a repair scheme. A large replaceable unit requires high cost for the spare units. Also, a large replaceable unit 10

11 results on lower probability for repair success, since it has a high probability to be defective. On the other hand, a small replaceable unit will result on a high complexity for the reconfiguration logic and the routing network. Therefore, the replaceable unit must not be very large to avoid a large cost for the spare units, neither very small, to avoid a high cost for the reconfiguration logic and the interconnections. Thus, to repair a large number of faults, the BISR must comply the following requirements: 1. the BISR must be able to cope with faults affecting both the regular and the spare units, 2. the replaceable units must be as small as possible, 3. the use of small replaceable units, should not lead to a very complex reconfiguration logic and routing network. 4. reconfiguration logic must be external to the memory block, and eventually being implemented in a different technology than the cell array, if nanotechnology is addressed 5. the time duration for performing repair must not be excessive, even for thousands of faults. The last condition concerns approaches that restart the whole test and repair process, for each fault detection. In this case of very high defect densities, the test and the repair cycle will be performed hundreds or thousands of times, resulting in unacceptable repair duration. To agree with point 5, the BISR schemes should perform repair of all faults in a single test and repair pass. The fourth condition is required because one of the assumptions in the FRACTURE project is that the memory can be designed using nanotechnologies, different than the CMOS surrounding logic. In the project we consider that the memory chip implemented in nanotechnologies is placed on the top of the CMOS logic chip by means of a low temperature bonding technology. To conform points 2 and 3 we can use a dynamic approach, described further. A.1. Local Repair The first technique presented concerns data level repair. Data repair localize the faulty bit position and replaces the memory parts generating this bit position by spare parts. Thus, the replaceable unit will be the block of the memory cells connected to a single input/output. To repair k faults, we will add k such spare blocks (spare units). We consider that we dispose a set of latches to store the information of the faulty bit positions (FBI latches Faulty Bit Indications). The FBI latch of position i contains a 0 if the data bit di is fault free, or a 1 if it is faulty. One way that we can compute the contents of latches FBI is shown in figure 1. Reset FBI FBI FBI n+k-1 n+k-2 n-1 FBI 0 Xn+k-1... Xn Xn-1... BIST Comparator X0 Error Indication Figure 1: Generation of the state of the FBI latches 11

12 The BIST comparator used to compare the read data against the expected data during the test session, is also used to provide the signals Xi. These signals determine the states of the FBIi latch. An OR gate receives the outputs of all XOR gates to generate a unique error indication signal. An OR gate combines the signal Xi with the output of the latch FBIi to generate the input of the latch FBIi. Thus, if at any cycle of the test session a 1 is generated on Xi (detection of an error on the bit position di), this value is memorized in the FBIi latch for the rest of the time, indicated a fault in the bit position di. To perform repair we use a set of MUXes that replaces the faulty units by the spare ones. A logic bloc implementing the reconfiguration functions will receive at its inputs the outputs of the FBI latches, and will compute the signals driving these MUXes. The reconfiguration is done in a local manner. In this case, the faulty unit is isolated at its right side (resp. left side) and is replaced by the closest fault-free unit (see figure 2). The reconfiguration functions for local repair are detailed in Periodic Progress Report No.1 and in conference paper [NIC03a]. To keep the replaceable units as small as possible by maintaining a low complexity for the reconfiguration logic and the routing network (thus, to conform points 2 and 3 from above), we use the a dynamic approach. Spare Units : k =3 Functional Units : n = 4 U 6 U 5 U 4 U 3 U 2 U 1 U 0 MUX M 0 0 M 0 1 M 0 2 M 0 3 MUX MUX MUX M 0 0 M 0 1 M 0 2 M 0 3 d3 d2 d1 d0 Figure 2: The local repair scheme. A.2. Dynamic Data Input Output Repair The dynamic approach configures the memory inputs/outputs in a dynamic manner. Instead of shifting permanently a data input/output to a fixed position, we shift dynamically to various positions, only a part of a block containing a faulty cell being selected by the memory addresses. For doing that, we use r address bits to dynamically modify the memory configuration. The address bits divide by R=2 r the size of the repairable units, while maintaining the same routing network and the same reconfiguration functions as in the static approach. For instance, we can consider a subset of the address bits, let's say bits A 1, A 2,, A r, and allocate one block of n+k FBI latches to each value of these bits. Thus, the block 0 of FBI latches will store the location information of all faulty cells accessed by the value A 1, A 2,, A r = 00. 0, the block 1 of FBI latches will store the location information of all faulty cells accessed by the value A 1, A 2,, A r = 10.0, the block R-1 of FBI latches will store the location information of all faulty cells accessed by the value A 1, A 2,, A r = We have in this case R = 2 r, and we have divided the block of cells connected to a data input/output into R sub-blocks, each corresponding to a repairable unit. The figure 3 shows how we store the faulty 12

13 location information into different blocks of FBI latches. As explained in figure 1, the signals Xi generated by the BIST comparator are entering the block of FBI latches. In figure 3 the new scheme uses R blocks of FBI latches. At each cycle of the test phase, the signals Xi enter to the block of FBI latches corresponding to the value of the address bits A 1, A 2,, A r. This is done by means of a MUX controlled by these address bits. During the regular operation of the system, the address bits A 1, A 2,, A r, are calculated to determine which block of faulty location storage cells will be selected to drive the reconfiguration of the memory during each memory access cycle. Thus, a fault free part of one block of the memory can be selected at a cycle to replace a faulty part of a second memory block, and another non faulty part of the former block can be selected at another cycle to replace a faulty block of a third memory block. Thus for repairing a fault we will use only a part of a memory block instead of using the whole block. n+k FBI Latches 0 n+k FBI Latches 1 n+k FBI Latches R-1 A1 Ar n n MUX n n BIST Comparator Figure 3: Selection of the block of FBI latches during test Using the dynamic reconfiguration scheme we can increase the efficiency of BISR scheme since the size of the repairable unit is divided by R. Thus, the size of the repairable units can become arbitrarily small. In a whole, the cost of the spare units decrease, but the cost of the reconfiguration circuitry will increase as we increase r. A. 3. Diversified Fault Tolerance The diversified approach distributes the spare resources between several repair schemes. Consider a memory composed of several parts and a scheme repairing each of these parts. For a given defect density, the distribution of the faults within the different parts will result on a few parts with a number of faults much larger than the majority of the parts. These parts correspond to the right side of the defect distribution curve (see figure 4), where a small number of parts may concentrate a number of faults much higher than the majority of the parts. The situation is becoming worst if we have many parts, since it increases the probability to have few parts with a much larger number of faults than the majority of them. In this case it will be more efficient to use within each part an amount of redundancy able to repair the moderate number of faults affecting the majority of parts, and add some extra (spare) parts, to replace the few ones that include a larger number of faults. #parts Majority of parts ( Q) few parts #defects/part 13

14 Figure 4: Defect distribution A.3.1. Diversified Repair Combining Data-bit and Block Repair The static and dynamic repair schemes considered in paragraphs 3.1 and 3.2 act at the data-bit level. The dynamic repair, divides dynamically the memory into 2 r parts composed of 2 m-r words of n bits, and performs a bit-level repair at each of these parts using k-spare bits. If, for some value of these r address bits, the corresponding memory part can not be repaired, for the reasons illustrated in figure 4, then, we can replace this part by a spare memory block of the same size as the above memory parts. The block-level repair scheme used for this repair is illustrated in figure 5 and has been detailed in Periodic Progress Report No.1 and paper [NIC03b]. In this figure, we use q spare blocks. Each of these blocks includes 2 m-r memory words. We use m-r address bits of the main memory as address bits for each block. We also use a CAM including q words of r bits. To perform the repair, we activate a first test phase for the main memory, and if necessary, we perform the dynamic databit repair. Then, we perform a second test pass for the main memory. The detection of a fault in this memory will write in a CAM word the value of the remaining r address bits of the memory (i.e. those not used as address bits for the spare blocks). When memory access is performed during the normal system operation, the value of the r address bits is compared in parallel with the content of all the CAM words. If the comparison matches with one of these words, a select signal is activated. This signal selects one of the q spare memory blocks, and disables the access to the main memory. Thus, the current read or write is performed over the selected spare block, and more specifically, over the word of this block selected by the current value of the m-r address bits. CAM with q=2 r bits/word CW 00 CW 1 0 m- r Spare bloc Spare bloc Select 1 Select 2 Disable regular memory Figure 5: Local block-level repair Due to the high defect densities, each spare bloc will include some faults. To repair the spare blocks before using them for repairing the memory, we employ the static bit-level repair scheme with the same number k of spare bits as for the main memory. We perform a first test and repair pass for the spare blocks. However, similarly to the memory parts, this repair may leave some spare blocks unrepaired. To cope with, we add a flag cell to each CAM word (fault indication flag). All the flag cells are initialized to 0 before starting the repair. Then, after the first test and repair pass for the spare blocks, we perform a second test pass for these blocks. If a spare block is discovered to be faulty during this test pass, we set the flag cell of the corresponding CAM word to 1. This value, disables using the faulty spare block during the block-level test and repair pass of the main memory. This scheme covers also faults affecting CAM words that are tested in a supplementary CAM test phase. B. Data BISR based on Error Polarities 14

15 A second set of BISR schemes are based on the principle of combining two defected units to create a fault-free unit. For details on the development of this technique see Periodic Progress Report No. 2 and conference article [NIC03c]. For making this combination possible, the idea is to analyze polarities of the errors produced by memory faulty units, and to combine those units producing the same error polarities. The combination has to be done by means of functions that mask the errors of a particular polarity. A faulty cell produces errors of a given polarity for the majority of the faults: stuck-at 0 or 1 faults, transition faults (a cell can not undergo the 0 1 or the 1 0 transition), coupling faults (the state or the transition of a cell modifies the value of another cell from 0 to 1 or from 1 to 0), static, dynamic, active and passive pattern sensitive faults (the state of a set of cells combined or not combined with the transition of another cell modifies the state of the aggressed cell from 1 to 0 or from 0 to 1, or prevent it for undergoing the 0 1 or the 1 0 transition). We can partition the spare and the regular units in four categories: The 01 category include units that generates both the 0 1 and the 1 0 types of errors. The 0 category generates only 1 0 errors. The 1 category generates only 0 1 errors. The fault-free category does not generate errors. It corresponds to the case where all the cells of a unit are fault-free. Based on this classification we will use faulty spare parts of the 0 category to repair faulty regular parts of the 0 category and faulty spare parts of the 1 category to repair faulty regular parts of the 1 category. For doing so, instead of replacing a faulty regular part by a fault-free spare part, we will use an OR function to combine the outputs of two faulty parts of category 0. This will repair the combined parts as far as they do not include faulty cells at the same position. In this case, the OR function will combine either two correct values, or a correct 1 value and an erroneous 0 value. So it will always give a correct output. Similarly, we will use an AND function to combine the outputs of two faulty parts of the category 1. Finally, the regular parts of the 01 category will be repaired by using fault-free spare parts. If, for some regular parts of the 0 category or of the 1 category, there are not enough spare unit parts of their category to repair them, then, we can use fault-free spare unit parts to repair them. For doing so, we can first test the memory and repair the parts of the 0 and of the 1 categories and then repeat the test of the memory for a second time. During this test, all the unit parts not repaired during the first repair phase will be declared in the 01 category. Thus, this test will convert to the 01 category the regular parts of the 0 or of the 1 category, that were not repaired during the first repair phase because there were not enough spare parts belonging to the same category. It will also convert to the 01 category the regular parts of the 0 or of the 1 category, that were not repaired during the first repair phase because they have faulty cells at the same position with the spare cells used to repair them. The converted parts will be repaired during a second repair phase by using fault-free spare parts, if the number of available fault-free parts is sufficient. The repair approach based on error polarities was used to implement a static repair scheme, and this scheme was extended to a dynamic repair scheme implementation. The details can be found in paper [NIC03c]. 15

16 C. Diversified Repair Based on ECC codes. To repair defects affecting a memory array we will use ECC codes to repair the majority of the faulty memory words, and a word repair scheme to repair the words left un-repaired as they include a large number of faults. Error correcting codes are used to correct non-permanent faults, such as softerrors induced when ionising particles strike a memory. Such errors cannot be corrected by repair techniques, since particles can strike randomly at any memory cell, so the affected bit cannot be fixed by reconfiguring the memory in an a priori repair approach. On the other hand, when the memory is affected by a few fabrication faults, using a repair scheme will require a lower area cost than an error correcting code (ECC). In addition, the speed penalty of the ECC is significantly higher. Thus, error correcting codes are used for transient faults, while repair is preferred for fabrication faults. When the defect density increases, the hardware cost of the repair approaches also increases and at a certain level of defect densities it becomes higher than the cost of the ECC codes. Thus, ECC codes can become more efficient than repair schemes. However, ECC codes can correct a few errors within a memory word. They become quickly impractical in terms of area cost, coding and decoding circuit complexity and speed penalty, as we increase the number of correctable errors. For instance, to use a double error correcting code, we have to pay twice more code bits and a significant speed penalty. Beyond these error correction capabilities (i.e. triple or higher error correction) ECC becomes very impractical. Due to this complexity and also because the probability that transient faults create multi-bit errors in a memory word, in nowadays applications memories are protected by single-error detecting codes (like the Hamming code). In a context of memories affected by high defect densities, repairing by means of error correcting codes becomes inefficient, due to the limitation of these codes to correct a small number of errors in each memory word. In fact, for high defect densities, several words may include many errors. Thus, using an error correcting code will leave these words un-repaired, and the memory will be rejected. However, if the majority of memory words includes a small number of errors, the ECC will correct these errors. It is therefore clear that error-correcting codes are good candidates for applying the approach illustrated in figure 4, which requires a scheme able to repair the majority of the memory parts (here the ECC code), and a second scheme able to repair the remaining parts. Since this second scheme must be able to repair words including multiple faulty cells, a word repair scheme is the best suited for this purpose. However, for high defect densities, some spare words will be affected by faults. Thus, the word-repair scheme must also cope with these faults otherwise the repair will fail. C.1. Word Repair Considering Faulty Spare Words Word repair is a well-known scheme introduced in [SAW 99]. This scheme uses a content addressable memory (CAM) with k locations. Each location is composed of an address field and a data field. The address field of each location 16

17 disposes a comparator. This enables comparing in parallel the current address applied on the memory against the address field of all the CAM locations. During the test and repair mode, a counter is used to select a CAM location. When a fault is detected, the current memory address is stored in the selected CAM location and the counter is incremented. During a read or a write operation of the functional mode, the current memory address is compared in parallel against the address field of all the CAM locations. A hit of the current memory address with the address field of a CAM location enables reading from or writing in the data field of the hit CAM location. At the same time, the address-hit signal controls a multiplexer that connects on the read data bus the data coming from the CAM. Otherwise (i.e. if address miss), the multiplexer connects on the read data bus the data coming from the memory. Because a memory test algorithm may address the same memory word several times, it may detect a faulty memory word at several instances. This will lead on storing the same memory address at several CAM locations, wasting the spare resources. To improve this scheme, we activate the address comparison mechanism also during the test and repair phase. Thus, if a fault is detected but at the same time the hit signal is activated, no address is written in the CAM. Details of implementation can be found in Periodic Progress report No.2 and in paper [ANG04]. It is interesting to note that the proposed diversified repair approach allows a good fabrication yield by adding a 16.3% area overhead to the 18.7% area overhead already added for Hamming code. This extra area is less than the 19% extra area required to pass from the Hamming code to a double- error correcting code, although the yield obtained by means of this code is still 0 (0.996 probability for a word to be fault-free or corrected by the 2-error correcting code, resulting to a yield of 1.15x10-57 : the probability that all the memory words are fault-free or corrected by the code). This illustrates the efficiency of this new approach which employs a first repair scheme for repairing the majority of the defective parts, and a second repair scheme that targets specifically the fault distributions for which the first scheme is inefficient. These numerical results suppose that each faulty CAM location is deselected by means of the fault indication flag bit. However, if a CAM location contains a fault in the address field or in the data field and a fault in the flag bit, such that the flag bit is not able to invalidate the CAM location, the repair may fail. The probability of this situation is computed by combining the probability to have a faulty CAM location (found earlier to be 0.46) and the probability to have an error in the flag cell or in the transistor driven by this cell (0.0116). This will give a probability equal to for the combined fault to affect a CAM location. Thus, the probability that no CAM location is affected by such a combined fault is equal to 7.68x10-6, bringing to 0 the yield. To achieve a reasonable yield we can use two flag bits F1, F2, to disable the output of the comparator of the address field of each CAM location, as shown in figure 6. Comparator Address field F F Data field Figure 6. Using a flag bit to invalidate the comparator of the address field of a CAM This will result on a probability 0.87 to have an un-repaired memory due to this problem. This probability becomes if we triplicate the flag bit. This allows 17

18 guarantying that combined faults affecting a CAM location and its fault indication flag bits do not affect dramatically the yield. D. Diversified approach combining fault tolerant cells with ECC and word repair The goal is to develop a low cost fault tolerant memory cell. Since the information that has to be preserved is a single-bit, from a theoretical point of view the only way to protect a single bit against failures is to triplicate each memory cell and use a voter to correct errors. Thus, the cell-level fault-tolerance approach seems to lead on a transistor count increase of 400% for SRAM cells, since in addition to the 18 transistors for the triplicated cell we need 12 transistors for the cell-voter. But we can get around this limitation in a process where imperfect fabrication of the devices results in the majority of cases on the degradation of the one of the two possible states of the device. In this case, the defect density is distributed asymmetrically over the two defective states, resulting on a much higher density for defects creating one error polarity. Then, we can implement a cell that tolerates these defects at low cost. For instance, if the dominant error polarity is 0 1, the fault tolerant memory cell can be built by using two memory cells and an AND gate, as shown in figure 7a. Similarly, if only 1 0 faults can occur, the fault tolerant cell can be built by using two memory cells and an OR gate (figure 7b). cell cell cell cell (a) (b) Figure 7. Fault tolerant memory cell for a) faults of 0 1 polarity, and b) faults of 1 0 polarity. The cost of this solution can be further reduced by observing that the information stored in each particular memory cell is used only when the cell is read. Thus, it is possible to remove the AND gate (OR gate) from each individual cell and place it on the outputs of the memory. Since a two-input gate per memory output represents a negligible overhead, we have an area overhead for the fault tolerant cell equal to 100%. Because of this overhead, the fault tolerant cell has a limited interest for defect densities up to 10-2, since the results obtained during the first 2 year shown that for such defect densities, a high yield can be achieved for an area overhead lower than 100%. However, for higher defect densities (e.g ) the other schemes do not work, due to the very high number of failing cells. In this case, the fault tolerant cell is employed to reduce the number of failing cells, and is combined with the techniques developed during the first two years (e.g. ECC and word repair) to provide a diversified repair approach that achieves high yield. 18

19 E. Diversified approach for sequential memories combining ECC with word repair based on faulty word bypassing The idea here is to use nanotechnologies to produce memories of large capacitance to replace hard discs and flash memories. Usually, a system uses a smaller and fast runtime memory to execute the current application, and accesses the mass storage memory to store data each time the run-time memory capacity is exceeded. But more predominantly, the system accesses this memory for long-term saving of data and application programmes and for retrieving them when needed by an application program. In this context data are read from and written to the mass storage memory as entire blocks of memory words, instead of individual words as it is the case for the run-time memory. To perform a block read or write, the system addresses the first word of the block and then addresses sequentially the subsequent words of the block. We propose the following architecture to implement a memory having a capacity of N blocks with m words per block and n bits per word. Each block is implemented as a memory having m rows, with a single word of n bits per row. Each row is selected by a word line which is generated by a sequential address-generation circuit. When the block is not accessed, no word-line is selected by this circuit. During a block access, the address generation circuit activates sequentially the one word-line after the other, and when all word-lines have been accessed, it goes to the state that does not select any wordline. The sequential address generation circuit is implemented by using a shift-register of m+1 cells, as shown in figure 8. The first cell of the register does not select any word line, while each of the remaining m cell selects one word-line, when it contains a 1. - When the memory block is not accessed the shift-register is in the state Thus, no word is selected since only the first cell contains a 1. - When the block is accessed, this state is shifted cyclically m times to select the m memory words for reading or writing. - A last shift brings the register in its initial state. 19

20 1 0 0 word 2 0 word 3 0 word m Figure 8. Sequential address generation using a shift-register. The memory can be implemented by using k sequential memory blocks connected to a data bus, and a decoder that decodes r=[log 2 N] bits to generate N block-selection signals, where r is the number of the address bits used by the system to select one out of the N memory blocks, on which it will perform a block write or read. 20

21 0 0 0 G 0 F 0 A 0 '' R R A 0 '' A 0 MUX F 1 A 1 S WL1 MUX F 2 A 2 S WL2 MUX F 3 A 3 S WL3 MUX MUX MUX G 1 F 4 A 4 S WL4 MUX F m+k A m+k S WLm+k 21

22 Figure 9. Repair architecture for memory with sequential addressing To repair the sequential memory, we combine ECC with word repair. The word repair adds a certain number of spare words to each memory block, and uses them for repairing the faulty words. The word repair solution adopted in the diversified repair using ECC with word repair, employs a CAM memory for saving the addresses of the faulty words, and select a spare word each time the current memory address matches the content of a CAM location. This solution requires a hardware 2.5 larger than a memory word, for implementing each spare word and the associated CAM address field. To reduce this cost for sequential memories, instead of storing the faulty memory addresses in a CAM, we use a circuitry that bypasses the faulty words during the sequential addressing. Thus, the memory block will comprise m+k words (m regular and k spare) and will use a sequential address generation circuit, generating m+k word-line selection signals. With the address generation circuit of figure 8, it is easy to bypass faulty words by using a multiplexer for bypassing the shift-register cells of the address circuit generation circuit, which select faulty words. This solution iss shown in figure 9. In this figure we have used two bypass levels. The first level bypasses a single memory word. The second level bypasses t memory words (t = 4 in the figure). We added the second level for two reasons : - When a memory word or the corresponding shift register cell is faulty and the corresponding bypass circuitry is also faulty, the memory cannot be repaired and is rejected. In a context of high defect densities, the probability that this happens for one or more memory words is very high, and will result at a very low yield. - In the context of high defect densities, the probability that several consecutive words are faulty is quite high. In this case, several consecutive words will be bypassed connecting in series several MUXes. If the clock cycle can accommodate the delay of s MUXes, then, a memory containing more than s consecutive faulty words will be rejected. This may reduce yield significantly. The second-level bypass solves this problem, since it can accommodate t s consecutive faulty words within a clock cycle (it introduces one MUX delay for every t consecutive faulty words). Repair Efficiency Evaluation of the BISR Architectures The WP2 of the project focuses on the evaluation of the fault tolerance techniques developed in WP1 and presented above. Initially, the evaluation of the BISR approaches was supposed to be carried out by simulation. However, as the project reviewers asked at the end of the first year, we checked the simulation results against analytical formulas for different defect distributions. By experimenting the approaches developed in WP1 for different defect densities and for different density distributions over various defect types, we were able to determine what are the defect density limits under which the proposed fault tolerant approaches could allow memory repair with an acceptable cost. Thus, we can provide feedbacks to researchers to concentrate their efforts in developing technologies that meet defect density constraints, and eventually abandon technologies that do not conform them. 22

23 Thus, to evaluate the repair efficiency of each implementation with respect to a given defect density we used one of the following two approaches: The analytical approach develops probabilistic formulas that estimate the fabrication yield achieved when using each of the repair schemes for a given defect density, as well as when no repair is used. Formulas used for yield evaluation are detailed in Periodic Progress Report No. 2. The simulation approach where we developed a statistical fault injection and simulation tool to determine the fabrication yield for memories using each of the repair schemes and for memories not using repair. The description of this tool is presented in Periodic Progress Report No.1. To evaluate the repair efficiency of the BISR techniques for increased defect densities, together with the area cost, we have performed a large number of experiments over a 1 Mbit memory using 32-bit word length, and over a 8 Mbit memory using 32-bit word length. We have selected the following defect densities for theses experiments Dd = 10-5, Dd = 2x10-5, Dd=2x10-4, Dd = 10-4, Dd = 3x10-4 and Dd=1x10-3. Such defect densities are more than two orders of magnitude higher than the defect densities in current memory technologies. For these densities the fabrication yield without repair is almost 0. To evaluate the efficiency of the repair architectures developed in WP1, we need to determine for various defect densities the yield improvement obtained by means of these architectures, and the corresponding hardware cost of the extra circuitry related to these architectures. Thus, we need to evaluate various implementations of the repair schemes, in order to determine the best trade-off in terms of repair efficiency versus hardware cost, for each fault density: - The static and dynamic versions of the fixed and the adaptive reconfiguration function schemes - The diversified repair combining bit-level repair and block-level repair must be evaluated for various values of the parameters k and R of the dynamic bitlevel repair schemes and for various numbers of spare blocks, for each defect density. - The static and dynamic versions of the fixed and the adaptive reconfiguration function schemes based on the error polarities, must be evaluated for various values of the parameters k (number of spare blocks) and R (factor that divides a spare block into R repairable units), for each defect density. - The diversified repair combining ECC codes and word repair have been evaluated for various numbers of CAM locations, for each defect density. In the following we present a summary of the conclusions of the evaluation experiments. All the experiment results can be found in the Periodic Progress Reports. For 10-5 defect density (slightly higher than current technologies) level dynamic repair is more efficient than the combined scheme dynamic bit + block repair. Both of them are less costly than the BISR architecture based on error polarity. All BISR schemes achieve impressive yield improvement, in many case from without repair 2% to 100% after repair, and for a moderate area cost. If the mean defect density is twice as large (2x10-5 ), the best results of the dynamic bit level repair scheme are better than the best results of the dynamic scheme 23

24 combining data bit level repair with block level repair. Again the error polarity based BISR implementations present the worst results. In case of 10-4 defect density, and for a configuration of 32k x 32 bits/word memory, the dynamic bit level repair becomes slightly better than the combined scheme, while for 16k x 64 bits memory the dynamic bit repair remains better. Again the scheme using error polarities gives the worst results. When considering even higher defect densities, the combined scheme shows the best results excepting the case of Dd = 1*10-3 (1000 defects) where the scheme using error polarities becomes more efficient than the dynamic bit level repair. For this defect density, the capability of the scheme using error polarities to produce a faultfree unit by combining two faulty units, overcomes its drawback of a high area cost. The combined ECC & word repair scheme is able to repair memories affected by defect densities as high as 10-2 by means of a moderate extra area (98% yield for 37% extra area). For instance, for Dd = 10-4, the combined ECC & word repair scheme requires an area overhead of 19,1%, while the best of the schemes discussed previously requires a area overhead of 28,7%. This approach is able to repair memories affected by defect densities as high as 10-2 by means of a moderate extra area. The diversified repair approach combining fault tolerant cells with ECC and word repair achieves 99% yield for a defect density up to 10-1, by means of 257% area overhead. For this extreme defect density, one out of ten memory cells is defective, and the other repair solutions do not work due to the very high number of defective cells. The diversified repair approach for sequential memories, combining word repair by means of bypassing, ECC, and block repair, achieves a 98% yield, for a 10-1 defect density, by means of 60% area overhead. - 24

25 Nanoparticle Deposition techniques developed within FRACTURE (WP4) Three different types of nanoparticles were studied: CdS; gold particles deposited by the LB technique (Q-Au); and self-assembled gold particles. CdS nanoparticles The Langmuir-Blodgett (LB) technique was used to define nanometre-size II-VI semiconducting CdS particles distributed in a fatty acid matrix. LB layers of fatty acid salts were first deposited in the normal way. Nanoparticles were then formed by exposing the multilayer film to an H 2 S atmosphere, figure 1. For example, in the case of the cadmium salt of arachidic acid, the following reaction takes place [CH 3 (CH 2 ) 18 COO] 2 Cd + H 2 S 2CH 3 (CH 2 ) 18 COOH +CdS H 2 S Cadmium arachidate Arachidic acid CdS Figure 1: Formation of CdS nanoparticles This method of creating the CdS nanoparticles is well-documented: by spreading a solution of arachidic acid (or other suitable fatty acid) in chloroform (10mg/ml) onto a ~1mM CdCl 2 subphase, cadmium ions substitute themselves onto the arachidate chains, forming cadmium arachidate. Monolayers (typically 20) can then be dipped onto a suitable substrate at a surface pressure of ~35 mn m -1. To form the nanoparticles, the resulting organo-metallic film was then exposed to pure hydrogen sulphide at a pressure of 1 atmosphere. This causes the protonation of the arachidate chains, reverting them to the acid and the formation of CdS nanoparticles within the fatty acid matrix. Films of cadmium arachidate were prepared on a variety of substrates and studied using ultra-violet/visible spectral absorption, grazing angle X- ray diffraction, ellipsometry and atomic force microscopy (AFM). Figure 2 shows an AFM image of a cadmium arachidate LB film following H 2 S exposure. 25

26 Figure 2: AFM image of a single LB layer of a cadmium arachidate LB film following exposure to H 2 S. Scan area 1.5 µm x 1.5 µm. The particles occupy about 50% of the surface area, corresponding to the expected 50:50 cadmium arachidate: arachidic acid ratio in the film (deposited at a ph of about 5.8). The individual particle size is about 50 nm and the particles are clustered together in some regions. The AFM image corresponds closely to a schematic model derived to explain the optical absorption and X-ray diffraction data of the CdScontaining multilayer films, figure nm up to 3 µm Figure 3: Proposed distribution of CdS crystals (shown in red) within LB multilayer structure. Not drawn to scale. Attempts were made to incorporate the CdS-containing multilayer into MIS and transistor structures. By depositing either cadmium arachidate (CdAr 2 ) films or simple arachidic acid (AA) spacer layers, the CdS nanoparticles could be positioned at different distances from the underlying silicon surface. The results revealed hysteresis in the capacitance versus voltage curves of the MIS structures, which may be related to charge storage in the CdS particles. However, other explanations are also possible. One problem was the relatively large size of the nanoparticles (figure 3) in relation to the overall LB film thickness (20 layers corresponding to about 55 nm). For this reason, the methods for metal nanoparticle formation described in the following sections were preferred. 26

27 Q-Au nanoparticles The work in this section is was undertaken with nanoclusters of gold, capped with organic ligands (Q-Au). The material has been provided by Dr M Green of Oxonica Ltd. P=O Figure 4: Structure of Q-Au nanoparticle [PAUL03-1] The Q-Au particles were of nominal diameter 10 nm passivated with tri-noctylphosphine oxide/octadecylamine; a schematic diagram of their structure is shown in figure 4. This capping makes the nanoparticles soluble in various organic liquids, but mainly insoluble in water; the Q-Au is thus suitable for LB deposition. The organically passivated nanoparticles were prepared using Schlenk line techniques. In a typical preparation, 10 g octadecylamine, 25 g technical grade tri-n-octylphosphine oxide (TOPO) and g NaBH 4 were charged to a Schlenk flask, the atmosphere evacuated and back flushed with dry nitrogen three times. The organic ligands and reducing agent were then heated under vacuum to 100 ºC for an hour, and finally flushed with dry nitrogen. The temperature was increased and stabilized at 190 ºC. A solution of HAuCl 4 (0.07g, 2.0 x 10-4 M) in 5 mls of 4-tertiary butylpyridine was injected directly into the hot organic ligands, causing an immediate deep red colouration. The solution was allowed to grow for 30 min under dry nitrogen, and then removed from the heating source. The reaction was allowed to cool to 60 ºC, removed from the Schlenk line and ca. 50 ml of methanol added, causing a precipitate. This was isolated by centrifugation, giving a dark red powder, which could be dispersed in non-polar organic solvents, such as toluene. Filtration of the toluene solution yielded a dark red solution of gold nanoparticles with a cubic crystalline core, capped with a mixture of TOPO and octadecylamine. Langmuir-Blodgett film deposition was undertaken using a Molecular Photonics LB700 trough situated in a Class 10,000 microelectronics clean room. The subphase was purified water obtained from a reverse osmosis/deionization/uv sterilization system; the film depositions were undertaken at a subphase ph of 5.8±0.2 and a temperature of 20±2 ºC. Cadmium arachidate films were obtained by spreading arachidic acid (Sigma-Aldrich, purity 99%) on a water subphase containing 5.0x10-4 M cadmium chloride (BDH, Aristar Grade). The deposition pressure for these fatty acid salt films was 22 mn m -1. A transmission electron micrograph (TEM) of the particles, average size 8 nm, is shown in figure 5. 27

28 60 nm Figure 5: Transmission electron micrograph of a single LB layer of Q-Au transferred onto a carbon-coated microscope grid. Self-Assembly of Au nanoparticles One technique for nanoparticle deposition that proved particularly successful during the FRACTURE project was based on chemical processing at room temperature and pressure [KOL03]. The gold nanoparticles were of nominal diameter 5 nm passivated with organic ligands; a schematic diagram of the structure is shown in figure 6. These gold nanoparticles were deposited onto Si/SiO 2 (oxide of a few nm thickness) by a two step process. First, the SiO 2 surface was functionalized with an amine. The functionalized surface was then dipped into a solution of the acid (i.e. COOH) derivatized Au-nanoparticles. To carry out the first step, a 10% solution of 1ml APTES in 9 ml toluene (APTES = 3-aminopropyltriethoxysilane) was used in small sample vials. The solution was kept in a nitrogen ambient. To remove any large polymeric materials, the solution was passed through a 0.2 micron PTFE filter. The Si substrate was kept in the solution for 1 hour and the nitrogen atmosphere was maintained using sure-seal vials.. Figure 6: Schematic diagram of O O - O O functionalized gold particles. O - - O The place SiO 2 S S S chemical reaction that takes at the oxide surface covers the layer with an amine compound, leaving a H 2 functionality 28

29 exposed. The functionalized substrate was dried with nitrogen and held under running ultrapure water for about 1-2 minutes to encourage charging of the amino groups prior to exposure to the nanoparticles. This surface was then dipped into a solution of the acid (i.e. COOH) derivatized Au-nanoparticles. Provided that the ph was adjusted correctly, the acid and amine were mutually attracted. The nanoparticles were therefore positioned at a distance from the SiO 2 surface equal to the length of the amine plus the acid - probably 1 to 2 nm. It was difficult to ascertain the precise size of the gold nanoparticles with atomic force microscopy (AFM) (see figures 9 & 10 later). A much clear indication is provided by the transmission electron micrograph in figure 7 (provided by the University of Leeds). Figure 7: Transmission electron micrograph (provided by Leeds University) of gold nanoparticles. It is evident from the TEM image that the average size of the nanoparticles is around 5 nm. The particles are quite small and stable, suggesting their use in memory devices. Self-Assembly onto Polymer Surfaces We have also studied the self-assembly of functionalized gold nanoparticles onto polymeric surfaces. The deposition technique that we have used is driven by the ionic attraction between opposite charges in two different polyelectrolytes, the so-called layer-by-layer assembly technique [DECH03]. A solid substrate with a positively charged planar surface is immersed in a solution containing an anionic polyelectrolyte and a monolayer of polyanion is adsorbed, figure 8. Since the adsorption is carried out at relatively high concentrations of the polyelectrolyte, most of the ionic groups 29

30 remain exposed to the interface with the solution and thus the surface charge is reversed. After rinsing in pure water, the substrate is immersed in a solution containing the cationic polyelectrolyte. Again, a monolayer is adsorbed but now the original surface charge is restored, thus resulting in the formation of a multilayer assembly of both polymers. Figure 8: Schematic representation of the build up of multilayer assemblies by consecutive adsorption of anionic and cationic polyelectrolytes [DECH03]. The surface of Au particles (i.e the acid COOH group) is negatively charged, allowing them to attach to a positively charged surface. Poly(ethyleneimine) (PEI) was used to charge the substrate layer. 1 mg of PEI was dissolved in 1 ml of tris(hydroxymethyl)aminomethane, C 4 H 11 NO 3 (tris), buffer solution. To this, a definite quantity of hydrochloric acid was added to bring the solution to a ph of 6.5. A number of substrates (namely Si with a thin oxide, glass, pentacene on glass) were soaked in this solution for 10 minutes. At the end of this time, the substrates were dried with a nitrogen gun. Figure 9(a) shows an AFM image of the gold nanoparticles deposited on an amine terminated silicon substrate. It is evident from the image that the gold nanoparticles are deposited densely on the substrate. In contrast, figure 9(b) shows gold deposited particles on the PEI covered silicon substrate. The image shows that the attachment of the gold nanoparticles is not as dense and uniform as the amine terminated surface. This was found to be the case for all the samples we have examined. It has been suggested [SCH99] that PEI is in the form of coils on the surface of a substrate. This may lead to non-uniform distribution of surface charges and hence the observed distribution of the gold particles. We have made attempts to increase the density of the nanoparticles by using alternate layers of positively charged PEI and negatively charged layers of poly(ethylene-comaleic acid) (PMAE). Figure 10 shows the AFM images of gold particles deposited on single PEI layer, figure 10(a), and on a three layer multilayer architecture with the PEI on the top, figure 10(b). In the latter case, the gold nanoparticles seem to be less aggregated on the surface. This may be due to a straightening of the PEI layer by the PMAE. 30

31 In summary, we have investigated the attachment of acid derivatized gold nanoparticles to amine terminated silicon surface and PEI surfaces. The results may be relevant in the realization of memory devices using metallic or semiconductive nanoparticles. (a) (b) Figure 9: AFM image of the gold particles deposited on (a) an amine terminated silicon surface and (b) a PEI covered silicon substrate. Scan area 1 µm x 1 µm. (a) (b) 31

32 Figure 10: AFM images of gold particles on (a) single PEI layer and (b) a three layer PEI/PMAE/PEI structure. Scan area 5 µm x 5µm. Nanoparticle Manipulation We have spent some effort in studying how the metal particles might be patterned onto device structures of nanometre dimensions. One promising method that has recently been developed at Northwestern University is called Dip-Pen Nanolithography (DPN). This technique, illustrated in the figure 11, is able to deliver organic molecules in a positive printing mode. An AFM tip is used to write alkanethiols on a gold thin film in a manner analogous to that of a fountain pen. Molecules flow from the AFM tip to a solid substrate ( paper ) via capillary transport, making DPN a potentially useful tool for assembling nanoscale devices. (a) (b) Figure 11: Schematic diagram showing the use of an AFM tip to: (a) remove Q-Au particles from a substrate; and (b) to deposit Q-Au onto a substrate.. In a series of preliminary experiments, we have used DPN to manipulate nanoparticles of Q-Au on a silicon surface. The micrograph shown in figure 12 reveals that a cast Q-Au film has a distinct multilayer structure, with each layer equal to approximately twice the molecular length expected from the structure shown in figure 4, i.e. 3-4 nm. The AFM tip can then be used to remove the Q-Au from the surface, as shown by the slot (obtained by scanning the AFM tip to and fro) in the 32

33 micrograph. Figure 13 shows that the Q-Au has been removed down to the underlying silicon substrate surface. Figure 12: AFM image showing selective removal of Q-Au cast onto a silicon surface. Figure 13: Profile of AFM image shown in Fig 12. We have also been able to use the technique to also write the Q-Au. The Q-Au particles were solution cast, as described in the previous report, onto half of the substrate. These clusters of nanoparticles thus provided an ink well to coat the AFM tip. The most successful results were obtained using evaporated gold surfaces treated with the silanizing agent. The first experiments conducted were to determine the minimum feature size possible. Figure 14 shows AFM images of a series of lines written with the Q-Au particles. The vertical lines present are scratches on the gold substrate. Four lines were written, each one twice the width of the previous line. The scan speed used was 25 µm s -1 and the 33

34 AFM tip scanned across each area ten times, with the scan aspect ratios and the scan widths shown in the figure. The measured line widths were all larger than the scan widths used. This is likely to be caused by two factors: the surface roughness of the substrate (AFM studies of the uncoated evaporated gold substrate revealed a grain size of nm); and the diffusion of the nanoparticles from the tip. Figure 14: AFM images showing the results of writing experiments using Q-Au. Metal-Insulator-Semiconductor Structures Silicon (p-type, (100) orientation, resistivity 1-2 Ω cm) wafers with a 3.8 nm thermally grown oxide were used as the substrates. Ohmic back contacts were first formed by the thermal evaporation of Al (thickness 300 nm) and subsequent annealing at 490 C for 10 minutes in a nitrogen ambient. Following LB deposition, Al top contacts (thickness 300 nm, 1 mm diameter) were thermally evaporated in a vacuum chamber (pressure 10-6 mbar) onto the organic films through a metal shadow mask. Figure 15 shows the various MIS structures that were investigated in this work: (a) Al/SiO 2 /p-si; (b) Al/20 LB layers CdA 2 /SiO 2 /p-si; and (c) Al/20 LB layers CdAr 2 /one LB layer Q-Au/SiO 2 /p-si. The current voltage and capacitance-voltage characteristics were measured using a PC-driven pico-ammeter (HP4140B) and an LCR bridge (HP4192). Provided that the top contact metallization was undertaken carefully, reliable MIS devices (i.e. non short-circuit) were obtained. Figure 16 shows the normalised capacitance versus voltage (C-V) data, measured at 1 MHz and a voltage sweep rate of 40 mv s -1, for the three different device structures investigated. In each case, the voltage scan was started in the inversion region and swept towards accumulation. The C-V curve for the reference Al/SiO 2 /Si sample (i.e. figure 15(a)) reveals the usual accumulation/depletion/inversion characteristics associated with MIS structures, with a flat-band voltage of approximately 1 V. Negligible hysteresis was evident on 34

35 reversing the voltage scan. The data for the Si/SiO 2 /CdAr 2 structure also show clear accumulation, depletion and inversion regions, with no hysteresis on reversing the direction of the voltage scan. The absolute value of the accumulation capacitance ( 255 pf) was consistent with that expected from the fatty acid film (20 layers) on top of the 3.8 nm SiO 2 layer. [PAUL03-1] (a) Al 3.8 nm SiO 2 Si (b) Al LB 3.8 nm SiO 2 Si (c) nanoparticles Figure 15: Schematic diagrams of different metal-insulator-semiconductor structures studied in WP4. The data in figure 16 reveal that the flat band voltages of both LB film MIS devices are approximately 3 V, shifted by about 2 V when compared to the Si/SiO 2 device. This suggests that the fatty acid salt LB structure has some incorporated positive charge at the LB film/sio 2 interface or within the insulator, i.e. a more negative 35

36 potential has to be applied to the gate electrode to achieve the same flat band conditions in the semiconductor. Such effects have been reported previously in MIS devices incorporating fatty acid and fatty acid salt insulators [PET90]. Normalised Capacitnace C/C max Si/SiO 2 Cd-AA/SiO 2 /Si Cd-AA/LB-gold/SiO 2 /Si Voltage (V) Figure 16: Normalized capacitance versus voltage characteristics for the different device configurations investigated (figure 15). MIS structure with (full line) SiO 2 as an insulator; (dashed line) SiO 2 /CdAr 2 ; and (dotted line) SiO 2 /Q-Au/CdAr 2. Measurement frequency 1 MHz. Scan rate 40 mv s -1. The most significant difference in the structures with and without the Q-Au nanoparticles is the relatively large hysteresis in the MIS structure containing the Q- Au layer. The clockwise nature of this hysteresis (for a p-type semiconductor) is usually associated with ion drift or polarisation of the insulator [SAW79]. However, the lack of any hysteresis for the LB reference MIS sample (i.e. structure shown in figure 15(b)) indicates that an alternative explanation may be more appropriate. We therefore suggest that charge storage in the Q-Au layer might account for the observed hysteresis. In accumulation (negative bias applied to the top metal electrode), electrons may be injected from the top electrode to the nanoparticles, which then become negatively charged. The opposite effect occurs in the inversion region, i.e. electrons are extracted from the nanoparticles to the top electrode. Previous work with LB film MIS devices based on GaP has shown that a relatively thick fatty acid film can support significant electron and hole currents, but the precise conduction mechanisms were unclear [PET85]. Although the SiO 2 layer used in this work is relatively thin (3.8 nm), the distance between the surface of the silicon and the gold particles is effectively increased to over 5 nm because of the presence of the organic capping layer associated with the Q-Au. This may prevent easy charge transfer via tunnelling from the semiconductor to the Au. 36

37 The charge storage effects were examined further by monitoring the C-V curves for different voltage sweeps, using an applied voltage steps of 0.2V and a step delay time of 1 s, figure 17. Figure 17: C-V sweeps measured on MIS structures incorporating Au nanoparticles. Solid line corresponds to a sweep ±4V, dashed line to ±5V and dotted line to ±6V. The inset shows the flat-band voltage shift as a function of the bias voltage limit. Here, the scan starts from different voltages in the inversion region; the solid line corresponds to a sweep of ±4V, the dashed line to ±5V and the dotted line to ±6 V. The magnitude of the hysteresis is a figure of merit for charge storage in the Q-Au layer. The flat-band voltage shift between the forward and reverse scans V FB can be defined V FB = V FB V + FB where V FB - and V FB + are the flat-band voltages of the forward and backward C-V curves. The dependence of the flat-band voltage shift on the voltage limits of the C-V measurement is presented in the inset figure. To a first approximation, V FB is proportional to the bias voltage limit. In conclusion, Langmuir-Blodgett layers of organically capped gold nanoparticles have been successfully built-up on silicon/silicon oxide surfaces. Layers of cadmium arachidate were deposited on top of a single layer of the nanoparticles to form a metal/insulator/semiconductor structure. The capacitance versus voltage characteristics of these devices were shown to exhibit hysteresis when the voltage scan was reversed. This effect was dependent on the starting sweep voltage and attributed to the storage of charge in the nanoparticles. 37

38 A number of other MIS samples have been studied in order to obtain further understanding into the charge storage process [PAUL03-2]. The substrates were p- and n-type silicon, both with and without a 3-4 nm oxide layer. Charge storage in n-si (with and without the oxide layer) was not observed. However, the capacitance versus voltage data for p-si without an oxide layer were interesting, figure 18 6x x x x Hz 10 4 Hz Capacitance (F) 4x x x x Hz 10 4 Hz Capacitance (F) 4x x x x Voltage (V) (a) Voltage (V) (b) Figure 18: Capacitance versus voltage curves for MIS devices based on p-si (no SiO 2 ). (a) Reference device. (b) Device incorporating Q-Au nanoparticles. In the case of the reference p-type silicon substrates (i.e. no nanoparticles), figure 18(a), the C-V curves are very stretched out, possibly reflecting a large density of traps at the p-si/cdar 2 interface. Little, or no, hysteresis is evident. The data for the devices containing the Q-Au layer, figure 18(b), show inversion and depletion characteristics, but no clear accumulation. However, the C-V curves for these devices reveal a distinct hysteresis in the opposite sense (anticlockwise for the p-silicon) to that observed in other MIS samples in this work. This is indicative of charge storage in the Q-Au nanoparticles by tunnelling from the semiconductor surface. Similar effects have been reported for thin SiO 2 layers implanted with silicon nanocrystals [KAP00]. The Q-Au layer seems to have taken on a dual role in this structure. First, its presence has influenced (reduced) the density of trapping states at the p-silicon surface, allowing an external voltage to affect the depletion characteristics of the device. As the SiO 2 layer has now been removed, the gold nanoparticles are positioned closer to the silicon surface at a distance equal to the thickness of the organic capping layer, 1-2 nm. This allows electrons to move between the silicon surface and the Q-Au, charging and discharging this layer as the MIS device is cycled in voltage. One problem, however, is the lack of full accumulation characteristics for this device. As accumulation is approached, the applied voltage cannot be sustained across the fatty acid LB film. A better insulator is therefore required in order to exploit the charge storage phenomenon in a memory device. Options for this were explored by the Demokritos group in Workpackage 5. Molecular Channels One challenge in the FRACTURE project was to produce an all-organic memory device. Organic materials with reasonably high carrier mobilities (of the order cm 2 V -1 s -1 ) that are currently under investigation for organic TFTs include thiophene derivatives and pentacene. (However, it should be noted that some very recent published data in this area have been the subject of considerable controversy.) We 38

39 begun our investigations using pentacene, deposited by thermal evaporation. High quality layers of this organic semiconductor could be produced by evaporation onto a number of different substrates. Improvements in the in-plane dc conductivity were achieved by annealing the evaporated films after deposition, by increasing the grain size in the films. Figure 19 shows atomic force micrographs comparing the morphological structure of films before an after annealing in nitrogen ambient. The optimum annealing conditions were found to be 70 ºC for 1 h. (a) (b) (c) Figure 19: AFM images of thermally evaporated pentacene on glass. (a) Unannealed. (b) Annealed at 50 ºC for 1 h in nitrogen. (c) Annealed at 70 ºC for 1 h in nitrogen. Scan area 2 µm x 2 µm. Field effect transistor (FET) structures were fabricated on low resistive (0.025 Ωcm) n-type Si substrates, figure 20. The source/drain contacts were defined by photolithography. The leakage current through the gate insulator was measured by shorting the drain and source; the value of leakage current was typically 5 pa. This suggests the quality of SiO 2 layer is good and the measured gate and drain transfer characteristics are solely due to the active channel material (i.e. pentacene), figure 21. Pentacene Source Drain Gold SiO 2 (200 nm) Gate Si +n Figure 20: Structure of pentacene FET. 39

40 I DS (A) 1.2x10-6 V = 5 V 1.0x10-6 DS 8.0x x x x I DS (A) V G (volts) V G (volts) I DS (A) 6x10-5 V G = 20 V x10-5 4x10-5 3x10-5 2x10-5 1x10-5 I DS (A) V DS (volts) = 0 V = -20 V V DS (volts) Figure 21: Gate transfer characteristic (top) and drain transfer characteristic (bottom) of pentacene FETs. We have also collaborated with workers at Cornell University, USA, for pentacene FET work. One issue that was identified in all the FET structures investigated was the hysteresis in the electrical characteristics. This needs to be eliminated, or substantially reduced, in order to see any affect due to charge storage on incorporated nanoparticles. Future Outlook While the molecular materials part of the FRACTURE project has made good progress, we have yet to achieve one objective that of demonstrating a memory device based on an organic semiconductor. The intention is to pursue this goal, outside the FRACTURE project. Figure 22 shows a proposed device structure, which will form an initial target. Evaporated pentacene forms the semiconductive channel while the gate and gate insulator are provided by silicon and silicon dioxide, 40

41 respectively. The nanoparticles will be deposited by both the LB method and the selfassembly technique. One further development could be to replace the silicon dioxide gate insulator with an organic (e.g. polymer) material. Figure 22: Proposal for Organic (pentacene) based nanoflash memory device incorporating the gold nanoparticles. It is anticipated that the collaboration between Durham and Athens will continue to be funded in-house. An Anglo-Greek collaborative grant proposal has also been submitted to provide further funding. 41

42 RESULTS ON MEMORY AND 3-D DEVICES (WP3 and WP5) 1. Demonstration of room temperature memory device comprising gold nanoparticles over a conventional FET structure. The nanoparticles are isolated from the Aluminum gate by either an organic insulator (LB deposited) or e-gun evaporated SiO2 layer. Figure 1. Schematic of the proposed and realized device. S and D are the source and drain of the device, C the channel area. The memory stack is made of a 5 nm SiO 2 (bottom, numbered by 1), gold nanoparticle layer in the middle (2) and organic insulator on top (3). Fabrication technology and innovations The device is fabricated on commercial SOI wafers of thickness 160 nm. The S/D areas are As implanted diffused and the channel is Boron doped. The thermal oxide thickness was either 3 nm or 5nm grown at 900 C. Fabrication details are described in [KOL03]. A device just prior to nanoparticle depositions is presented in the figure below: Fig.2 SEM image of the device before formation of gate stack. We remark that both S/D metallic contacts have been fabricated before nanoparticle deposition. 42

43 Once nanoparticles have been deposited followed by the deposition of Cadmium Arachidate (organic insulator) the aluminium gate was formed paying attention to avoid high temperature treatments (>75 C) of the device further on. New Metallization process In the case of samples B and C, care was taken during Al deposition and patterning that the temperature of the samples did not exceed 75 0 C; this minimised damage to the underlying organic films. For this, a special process was developed to achieve good yield of devices. This is described in more detail below. Remark that conventional Al lithography requires temperatures up to 110 ºC and Al etching with phosphoric acid. During the Al evaporation a relatively low deposition rate was used to avoid heating the wafer. For gate electrode patterning, AZ5214 photoresist was used. After resist spinning a pre-bake step was performed at T=65 0 C for 60 min. The foregoing represent the optimum process conditions using the temperature limitations since for post-bake temperature lower than 60 0 C the photolithography was not possible. The photoresist was patterned followed by a post-bake step at 65 0 C for 90 min on a hotplate. Aluminum etching was performed by dipping the samples into AZ726 developer for 90 sec at room temperature. Finally, the remaining resist was removed using acetone in ultrasonic bath. This process was applied for Al metal patterning of both capacitors and FETs. In fig3a metal lithography for the formation of capacitors is shown that demonstrates that the process works quite nicely. In fig. 3b-3c the lithography for the gate metal of the FETS is shown that is also of good quality. There is a problem with the metal contacts for S/D because they are etched during the lithography of gate metal. For that reason S/D metal contacts which are defined before the metallization step for gate metal are made quite thick (500 nm) in comparison with gate metal that is only 100 nm thick. By this way the S/D contacts although attacked during metal gate etching remain in place. Some more comments on metallization are made in page 90. Fig3a. Aluminum gate Capacitors defined over the memory stack Fig. 3b. A FET device with S/D and Al contacts 43

44 Fig. 3c. A view of several FET devices. Electrical characterization and demonstration of memory effect In figure 4, the transfer (I DS -V GS ) characteristics in the linear region (V DS =100 mv) are compared for the three types of FET device. For comparison all tested transistors have a gate width W = 10 µm and a gate length L = 1.5 µm. Thus, no short channel effects affect our device operation and the memory characteristics are easily distinguished. Figure 4. Transfer I-V characteristics of tested devices and their sub-threshold regions: (solid line) reference of 5 nm SiO 2 MOSFET, (dashed line) reference of 5 nm SiO 2 plus the organic insulator layer MISFET and (dotted line) MISFET single memory cell with Au nano-particles. The inset shows the same curves in linear scale. It is evident from fig. 4 that there is a threshold voltage variation as the insulator stack configuration is changed, which is mainly attributed to the presence of fixed charges in the organic insulator. This has been already observed in other LB deposited insulators and explained as trapped charge at the interface between sequentially deposited layers [EVA88]. The sub-threshold slope is also affected by the nature of the insulating layer. The reference MOSFET transistor (device A) has a subthreshold slope equal to 89 mv/dec, typical for long-channel devices, while that for 44

45 the LB MISFET (device B) is 523 mv/dec and that for the nanoparticle-containing MISFET (device C) is 364 mv/dec. No hysteresis was noted in the I-V characteristics of either reference device (A or B) when the gate voltage sweep changed direction. However, the MISFETs containing the Au nano-particles possessed transfer characteristics with a hysteresis that increased as the gate voltage increased. Typical behavior is shown in figure 5. Figure 5. Transfer I-V characteristics of tested MISFET with embedded Au nano-particles into the gate insulator measured with different voltage sweep limits: (open circles) ±2V, (solid line) ±4V. This hysteresis is a well-known effect of charge storage in the insulator. Since neither of the reference devices exhibited this effect, we attribute the charge storage to the presence of the Au nanoparticles. It is significant that this hysteresis direction is counterclockwise, indicating that electrons are extracted from the nanoparticles for positive gate voltages and injected into them from the gate electrode for negative gate voltages. Although the SiO 2 layer used in this work is relatively thin (5 nm), the distance between the surface of the silicon and the gold particles is effectively increased to over 10 nm because of the presence of the amine capping layer associated with the Au nanoparticles. This prevents easy charge transfer via tunneling from the semiconductor to the Au. If we consider a simple tunnelling expression to compare the currents to the gold nanoparticles either from the top metal gate electrode or from the Si channel we can write that: 0.5 I = I 0 exp( kd( ) ) where, I 0 is a constant current value, k is a constant, d is the insulator thickness and is the tunneling barrier of the insulator. For the Si/SiO 2 system the energy barrier height for electrons is 3.2 ev and for a fatty acid film values of 2 ev have been reported in the literature [POL78]. Even if there is a lowering of barrier height for the Cd-AA film its thickness cannot justify a direct tunneling mechanism through it. However, it has been also reported [NAB02] that the dc current conductivity measured in LB deposited multilayers can be attributed to a combination of two mechanisms: (i) direct tunneling through each LB bi-layer and (ii) thermally activated hoping within the plane of carboxylic head groups. We believe that these mechanisms could in fact explain the charge transfer to the gold nanoparticles through the fatty acid film and not through the thermal oxide film. 45

46 We have then fabricated simple MIS structures to get more experimental results of the dc conductivity properties of our insulators. In fig.6 we present results on J-V measurements of MIS structures where the insulator is made out of either a 5 nm thermal SiO 2 (fig 6(a)), or a combination of a thermal SiO 2 and 54 nm of the Cd- AA insulator (fig 6(b)) or a combined film of a thermal SiO 2, an amine layer and 54 nm of the Cd-AA film (fig 6c). The metal electrode is aluminum. The second of these experiments (fig. 6(b)) can be compared with previous measurements on the conductivity of fatty acid multi layers performed either up to 0.8 V [MAN71] or up to 3V. We find a good agreement of our measurements with these investigators. The current remains low in the sub-1v regime and increases two orders of magnitude for voltages of 3V. For higher voltages the Cd-AA film of 54 nm breaks down. The thin thermal oxide of 5 nm exhibits better insulating properties for these voltage values (fig 6(b)) that can justify the charging of the nanoparticles in our memory structure from the top gate electrode. Current densisty, J (A/cm 2 ) 1x10 3 1x1 1x10-3 1x10-6 1x ACC INV Voltage (V) Current Density, J (A/cm 2 ) 10-1 INV ACC 1x as-deposited LB annealed LB Gate Voltage (V) Current Density, J (A/cm 2 ) 1x1 1x10-3 1x10-6 1x ACC INV Gate Voltage (V) 46

47 Figure 6. Current density as a function of the gate voltage flowing through three different gate insulators of MIS capacitors: (a) 5nm thermal SiO 2, (b) thermal SiO 2 plus an 54nm LB CdA insulator and (c) the previous sample with an anime interlayer. The application of different voltage pulses to the gate electrode may be used to elucidate the programming behaviour of these MISFET memory devices. In figure 7a, the effect of a symmetrical pulse sequence on the threshold voltage is shown. The erase process was obtained by a saturation pulse +6V for 1s while for the write process a pulse 6V was used with the same time period. If a gate voltage of 0.5V was used for reading the memory, it was possible to distinguish between a written ( 1 ) and the erased state ( 0 ) by the drain current level. Figure 7b shows the dependence of threshold voltage shift on the height of the applied voltage pulse. No change in the memory state was achieved utilizing pulses well below 1s. The need for relatively long programming times can be attributed to the large sub-threshold slope: the highest the sub-threshold swing, the poorer the control of the gate over drain current. Finally, similar insulating layer as the one used in our memory device exhibited tunneling current density of the order to 10-7 A/cm 2 [25]. This current density divided by the 1 sec time we need to apply the voltage on the gate gives a corresponding charge density to the nanoparticles at 10-7 C/cm 2. This value seems to be in agreement with the charge trapped in the insulator as calculated from the voltage shift (fig. 7b) in our device after a 6V applied voltage pulse to the gate. The trapped charge is calculated C/cm 2 by ( V th C 0 ) where C 0 is measured at F/cm 2 for accumulation using an MIS capacitor structure with a thin oxide, amine layer and the Cd-AA film. The values of the charge transferred and of the charge trapped in the nanoparticles are in quite good agreement. One could go a step further by estimating how many electrons are trapped per nanoparticle since the nanoparticle density is also known from TEM measurements. Figure 7. Programming characteristics of MISFETs single memory devices with Au nano-particles embedded into the gate insulator stack. (a) Write/Erase (W/E) process 47

48 obtained by applying 6V and 6V voltage pulses respectively. The pulse period was 1s. (b) The effect of the programming voltage on the memory window for pulse 1s. In order to check the non-volatility of these memory devices charge retention measurements of the charge retention time at room temperature have been performed through application of ±6 V gate voltage stress for 1 sec with a source to drain bias at 0.1 V. The retention characteristics shown in fig.8 demonstrate that the memory window is not practically decreased from its initial value for times as long as 4x104 sec. This reveals a remarkable potential for the proposed device as a non-volatile memory given not only the simplicity of its fabrication technology but also the early stage of its development. Figure 8. Retention characteristics of sample C after application of ±6 V on the gate for 1 sec. Replacement of the organic insulator with Deposited Silicon Oxide MOSFET devices have been fabricated with deposited 10 nm SiO2 at room temperature under high vacuum (10-8 Torr) at very slow rate (1A/sec) using e-gun evaporation. The process has been performed at the Institute of Electonic Structure and Lasers/Forth in Crete in cooperation with Dr. G. Konstandinidis. As stated before this was insulator was used in order to prevent current flow between Au-nps layer and the metal gate. The thermal gate oxide thickness of the devices was 3 nm and nanoparticles have been deposited by self-assembly on the functionalized silicon surface. As it has been hoped in that case charging of the nanoparticles has been observed from the channel region of the device. Applying positive gate voltage pulses to the FET we observe transfer of negative charge from the channel region while negative pulses extract the electrons from the nanoparticles to the channel. Typical output characteristics are shown in figure 9(a). In figure 9(b) results of the memory window from the unstressed state (fresh) obtained after successive pulses at 100ms is presented. The maximum value of this window is around 0.5V. 48

49 (a) (b) Fig.9. Id-Vd and memory properties of devices with self-assembled nanoparticles and a deposited silicon oxide insulator on top. 2. Demonstration of low temperature wafer bonding of silicon wafers with maximum temperature less than 200 C and high bonding strength. Use of spin on glass layer in between bonded wafers that shows good step coverage. Demonstration of thin silicon film transfer (100 nm) by the above technique. Low temperature wafer bonding appears as an attractive solution for wafer level packaging of heterogeneous systems as for example of electronics and MEMS [NIK00]. Especially for successful thin layer transfer it is critical that the bonding strength is sufficiently high to withstand mechanical and/or chemical thinning of one of the two wafers down to some hundreds of nanometers thickness. Several efforts have been reported [HEN00, WEN01] focusing on the bonding strength and its increase to high values (>1500 mj/cm 2 ) following different processing conditions for surface activation. These use plasma surface activation of the wafers before bonding. The use of plasma activation, however, may result in charge being trapped in the activated oxide, which could be detrimental for the operation of devices [WU00]. Contrary to plasma activation, with chemical surface activation these problems are avoided, while the bonding strength is high enough to permit thin film Si transfer. Experimental We have used 4-in p-type silicon wafers of 525 µm thickness. On wafer, which will be the top wafer on the bonded stack, is oxidized to form a 20nm oxide. Another wafer is used for substrate, and is first Piranha cleaned (H 2 SO 4 :H 2 O 2 volumetric 1:1) for 15 min. This is followed by DI water cleaning and spin-on-glass (SOG) material coating. The SOG film used was a Methylsilsesquioxane (MSSQ) from a commercial vendor. This material shows good step coverage in the case that patterns exist on the wafer surface. The MSSQ was first filtered using a 0.2 µm filter and then spinned on the wafer surface. The spinning conditions were 5000rpm for 30sec and resulted in the formation of a 300 nm thick SOG film. The wafer is then annealed at 180 C for 2min and 250 C for 1min on a hot plate followed by a 400 C for 30min annealing in a furnace under N 2. 49

50 Then both wafers are processed together according to the bonding procedure. This procedure includes a surface activation step in a NH 2 :H 2 O 2 :H 2 O volumetric 4:1:6 solution at 55 C for 3 min. This step results in the formation of Si-OH bonds and renders the surface hydrophilic [8]. After a thorough DI water cleaning followed by a drying process, the two wafers are brought into contact at room temperature under a class 100-hood environment. After contacting the two wafers were gently pressed on the center of the bonded pair with a tweezers for 30sec to remove any trapped air within the two wafers. The annealing process of the bonded wafer pair is performed at 200 C for 6h in N 2 ambient. The storage time at room temperature between bonding and annealing is between 1 and 45 days. To compare the results of the chemically activated process with plasma surface activation, some wafers were bonded using oxygen plasma activation. The conditions of the oxygen plasma were: pressure 15mTorr, plasma power 100W and oxygen flow 80sccm. Thorough DI water cleaning and a drying process followed the plasma treatment. The SOG spin-coat and the annealing process was the same as with the chemically activated wafers. After optimizing the bonding process we have fabricated Silicon-On-Insulator (SOI) structures with a silicon overlayer thickness of about 400 nm. Results Chemical treatment The bonding strength of the two bonded wafers was measured using the crack opening method [TON99]. In a first test, the bonding strength was measured as a function of storage time at room temperature (for a minimum duration of some minutes after the bonding to a maximum duration of 45days) and prior to annealing the wafer stack. In a second test, the bonding strength was again measured, as a function of the storage time prior to annealing, after an annealing phase at 200 C for 6h. Bonding strength is characterized by the interface surface energy γ and is estimated by the crack-opening method. In this method a blade is inserted between the two bonded wafers and a crack is generated. The whole process takes place under an IR camera where accurate measurements of the crack length L are possible. The crack length is related to the interface energy by equation (1) [TON99]: E tw tb γ = () L where t w is the thickness of each of the wafers, t b the thickness of the blade and E is the Young s modulus of the wafers. The crack length was measured with an accuracy of ±0.5mm, thus the surface energy error was calculated accordingly. The error bars in figures 1, 3 depict this calculated error. We observe that just after bonding at room temperature the value of γ is only 5 ± 0.3 mj/m 2. If this crack-tested wafer is left for 6 days at room temperature and then repeat the crack test we measure a value of 80 ± 8mJ/m 2. Measurements for non-annealed wafers as a function of storage time are seen in figure 1. The hydrophilic bonding of the two wafers is due to hydrogen bonds between water molecules acting as bonding bridges. During room temperature wafer storage, water molecules rearrange at the interface, thus increasing surface energy. 50

51 Fig. 1 Energy measurements performed, after bonding and before annealing, as a function of storage time (at room temperature). To inspect the macroscopic changes of the bonding area we have used a sensitive to IR black & white camera (Hitachi KP-161) with an infrared band pass filter. The images were taken by transmitting IR light through the one side of the bonded wafer pair and observation of the other side using the camera. Figure 2 shows the IR images of bonded wafers just after bonding and after some days of storage. These images clearly show that the bonding quality is increased with storage time (figure 2a-c) with many voids completely disappearing or very much reduced. We attribute the presence of voids to the presence of particles that inhibit wafer bonding in the nearby by area. Note that the nature of the formation of a SOG film (during the spinning and the annealing steps) makes it more prone to particle deposition on its surface that cannot be removed afterwards. After annealing, the IR image (figure 2d) shows no difference with the long storage time IR image. This is due to the fact that IR inspection cannot distinguish between bonding strengths and thus remains a useful qualitative tool for macroscopic inspection only. F ig. 2a IR image just after bonding. Fig. 2b IR image after 4 days stor age at room temperature. Fig. 2c IR image after 40 days s torage. Fig. 2d IR image after Annealing. 51

52 We present now our crack test method measurements after annealing the bonded pairs at 200 C/6h. On figure 3 we present our measurements of the bonding energy after annealing as a function of storage time before annealing. Fig. 3 Energy measurements performe d, after annealing, as a function of storage time before annealing. The annealing step takes place after storage at room temperature. In this case an important increase of the interface energy with storage time is also observed. For example, after 5 days storage time energy of 500 ± 80mJ/m 2 is measured. This energy increases up to 1500 ± 350mJ/m 2 after 45 days of storage. Note that other investigators report that bonding energies up to 2500 mj/m 2 were sufficient to demonstrate layer transfer by the smart-cut process [HEN00]. During thermal annealing polymerization of silanol (Si-OH) groups across the interface takes place, according to reaction (2). Si OH + HO Si Si O Si + HOH (2) As a result, strong siloxane (Si-O-Si) bonds are formed that strengthen the bonding energy of the wafer pair. The long time storage of the bonded wafers at room temperature results in the polymerisation process starting under better conditions due to water molecules rearrangement, forming more stable hydrogen bonding structures [TON99]. The rearrangement takes place at temperature below 110 o C. At higher temperatures the water molecules either diffuse along the bonding interface towards the outer wafer rim to the outside, or through the surrounding native oxide to react with Si to form SiO 2 and hydrogen. For temperatures higher than 110 ο C we enter the phase of permanent wafer bonding. Finally during room temperature storage the increase of the bonding energy with time results in the reduction of void size since initially apart surfaces are brought to contact where this is not prohibited by the presence of a particle. To demonstrate the possibility to obtain a Silicon-on-Insulator structure using the above bonding technology we have then proceeded to bond a bulk silicon substrate wafer with a SIMOX commercial wafer with an epitaxial layer over it for purposes described in WP5. The total Si thickness is 360 nm. The process used for bonding is a similar with the one described above. After bonding the SIMOX wafer was mechanically thinned down to 40 um using a Logitech system. The mechanical thinning was then followed by chemical selective etching using an EPW (Ethylenediamine-Pyrocatechol-Water) at 110 C. This etchant is known that 52

53 selectively removes silicon and stops at the buried oxide layer of the SIMOX wafer. In Fig. 6 we show IR images of the bonding of the SIMOX wafer before thinning and after final thinning. As can be observed the final area of silicon left is about the 70% of the total wafer area. This is a quite promising result given the fact that we are in an exploratory phase of the technology. Fig. 6 Process sequence for thin Si film transfer with low temperature bonding. (a) The SOG film is spinned on top of a SOI wafer. (b) Bonding of the two wafers, the dashed line indicates the bonding interface. (c) After mechanical lapping the thickness of the top wafer is reduced to 40um. (d) The remaining 40um Si film is removed with anisotropic chemical etching, down to the buried oxide. (e) Removal of the buried oxide completes the thin crystalline Si film transfer. Fig. 7a IR image of the bonded SOI wafer, after the annealing at 200 o C for 6h. Fig. 7b Image of bonded SOI wafer, after the lapping process. Fig. 7c Image of the finished Si film transfer (fig 6e). The white dashed line indicates the boundaries of the transfer film 53

54 Fig.7 TEM images of an SOI structure with the Si overlayer of 360 nm, the SOG (300nm) and a thermal oxide (200 nm). The bonding is between SOG and thermal oxide as can be seen in higher magnification on (b). 3. Demonstration of operation of an SOI MOSFET as well as of a memory device fabricated on thin film crystalline silicon transferred by low temperature wafer bonding. Source/Drain and channel doping are performed before wafer bonding. Device is formed using anisotropic silicon etching technique. The first fabrication process step consists of the growth of 10nm thick sacrificial dry oxide on the silicon surface of a SIMOX wafer. Arsenic implantation at a dose of 2x10 15 cm -2 with 40keV accelerating energy into the silicon overlayer and subsequent thermal annealing at 1000 C for 120 min are then performed. Such a thermal budget results in the dissolution of end-of-range damage initially created at the amorphous/crystalline interface and a uniform profile of As through the silicon overlayer with a concentration of cm -3 as predicted by SUPREM simulations. Sheet resistance measurements give a value of 40 Ohm/sq. in relative agreement with the doping profile predictions. This wafer is then sent out (KTH, Sweden, Dr.H. Radamson) for epitaxial growth of a 200 nm Boron doped (1017 cm-3) epitaxial layer. In total 3 SIMOX wafers have been grown with this B layer. Other two have been grown with a SiGe relaxed film doped with the same Boron concentration. The SiGe layers were grown for investigating the etch stop capability. The wafer was then subsequently bonded on a substrate silicon wafer with a SOG intermediate layer as described in detail in the Deliverable 3.1 (1 st year report). 54

55 Subsequently the SIMOX wafer was mechanically thinned down to 40 um using a Logitech system. The mechanical thinning was then followed by chemical selective etching using an EPW (Ethylenediamine-Pyrocatechol-Water) at 110 C. This etchant is known that selectively removes silicon and stops at the buried oxide layer of the SIMOX wafer. The buried oxide can be either removed with HF either used as a mask for further processing. The process is shown in fig.1a The schematic of the structure thus obtained structure after wafer bonding, thinning and oxide removal is shown in fig.1b: Figure 1a: Process for the fabrication of SOI layers shown in fig. 2b Low T Wafer bonding Si sub. SiO 2 /BOX As doped Si B doped epi Si or SiGe SOG layer A first lithographic mask has been applied to define lines of different width between 0.8 um to 2 um using optical lithography. Following the same procedure as in Deliverable 3.2 (1st year report) we have made a V-groove using EPW etching in the areas of the defined lines. A second mask has defined the transistor by removing silicon from the other part of the wafer. A SEM image (fig.2a) shows the V-groove with the silicon channel. A third mask defines the metal contacts for Source/Drain and a fourth mask defines the metal gate. The complete device is shown in fig 2c. 55

56 Fig. 2a A SEM side view of the channel area Fig. 2b. The channel shown in fig.5a after gate metallization Fig. 2c. A far view of the device with S/D on left/right and gate metal over the channel in the middle. Demonstration of SiGe channel devices The above technology has been only successful when the the thin trnferred layer was from SiGe. The main reason is that SiGe is an efficient etch-stop exhibiting selectivity with silicon over 100. So all MOSFET transistors achieved during FRACTURE on low temperature wafer bonding and etch-back make use of a SiGe layer. This layer 56