High Speed Quad SPST CMOS Analog Switch

Transcription

1 High Speed Quad SPST CMOS Analog Switch HI-21HS/883 The HI-21HS/883 is a monolithic CMOS analog switch featuring very fast switching speeds and low ON resistance. This integrated circuit consists of four independently selectable SPST switches and is pin compatible with the industry standard HI-21 switch. Fabricated using silicon-gate technology and the Intersil dielectric isolation process, this TTL compatible device offers improved performance over previously available CMOS analog switches while eliminating the problem of latch-up associated with other fabrication processes. Featuring maximum switching times of 5ns, low ON resistance of 5Ω maximum, and a wide analog signal range, the HI-21HS/883 is designed for any military application where improved switching performance, particularly switching speed, is required. (A more detailed discussion on the design and application of the HI-21HS/883 can be found in Application Note AN543.) The HI-21HS/883 is available in a 16 Ld CerIP package and is specified over the temperature range of -55 C to +125 C. Features This Circuit is Processed in Accordance to MIL-ST-883 and is Fully Conformant Under the Provisions of Paragraph Low On Release Ω Max Wide Analog Signal Range ±15V Turn-On Time ns Analog Current Range (Continuous) mA TTL/CMOS Compatible No Latch-Up Pin Compatible with Standard HI-21 Applications High Speed Multiplexing High Frequency Analog Switching Sample and Hold Circuits igital Filters Op Amp Gain Switching Networks Integrator Reset Circuits Pin Configuration Functional iagram HI1-21HS/883 (16 L CERIP) TOP VIEW V+ SOURCE INPUT A 1 OUT A 2 OUT2 TTL LOGIC INPUT LEVEL SHIFTER AN RIVER GATE SWITCH CELL RAIN GATE IN1 V IN2 V+ OUTPUT 5 12 NC V- IN4 OUT IN3 OUT3 Ordering Information A A 3 PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. WG. # TRUTH TABLE HI1-21HS/883 HI1-21HS/ to Ld CerIP F16.3 LOGIC 1 SWITCH ON OFF April 9, 212 FN CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Americas Inc. 1989, 212. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 HI-21HS/883 Absolute Maximum Ratings Voltage Between V+ and V- Terminals V ±V SUPPLY to Ground (V+, V-) ±18V Analog Input Voltage, (+V S ) V SUPPLY +2V Analog Input Voltage, (-V S ) V SUPPLY -2V igital Input Voltage, (+V A ) V SUPPLY +4V igital Input Voltage, (-V A ) V SUPPLY -4V Peak Current (S or ) (Pulse at 1ms, 1% uty Cycle Max) mA Continuous Current Any Terminal (Except S or ) mA Thermal Information Thermal Resistance θ JA ( C/W) θ JC ( C/W) CerIP Package Package Power issipation at +75 C CerIP Package W Package Power issipation erating Factor above +75 C CerIP Package mW/ C Junction Temperature C Storage Temperature Range C to +15 C Lead Temperature (Soldering 1s) C Recommended Operating Conditions Operating Temperature Range C to +125 C Operating Supply Voltage Range (±V SUPPLY ) ±15V Analog Input Voltage (V S ) ±V SUPPLY Logic Low Level (V AL ) V to.8v Logic High Level (V AH ) V to +V SUPPLY CAUTION: o not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. TABLE 1..C. ELECTRICAL PERFORMANCE SPECIFICATIONS evice Tested at: +V SUPPLY = +15V, V SUPPLY = 15V, = V, unless otherwise specified..c. PARAMETERS SYMBOL CONITIONS Switch ON Resistance r S V A =.8V, V S = 1V, I = -1mA All Unused Channels V AL =.8V Source OFF Leakage Current rain OFF Leakage Current Channel ON Leakage Current V A =.8V, V S = -1V, I = 1mA All Unused Channels V AL =.8V I S(OFF) V S = +14V, V = -14V, V AH = 3.V All Unused Channels V AH = 3.V, V = +14V, V S = -14V V S = -14V, V = +14V, V AH = 3.V All Unused Channels V AH = 3.V, V = -14V, V S = +14V I (OFF) V = -14V, V S = +14V, V AH = 3.V All Unused Channels V AH = 3.V, V = +14V, V S = -14V V = +14V, V S = -14V, V AH = 3.V All Unused Channels V AH = 3.V, V = -14V, V S = +14V I (ON) V = V S = +14V, V AL =.8V, All Unused Channels V AL =.8V, V = V S = -14V V = V S = -14V, V AL =.8V, All Unused Channels V AL =.8V, V = V S = +14V Low Level Input Current I AL V AL =.8V All Unused Channels V AH = 4.V GROUP A SUBGROUPS TEMPERATURE ( C) MIN MAX UNITS Ω 2, 3-55 to Ω Ω 2, 3-55 to Ω na 2, 3-55 to na na 2, 3-55 to na na 2, 3-55 to na na 2, 3-55 to na na 2, 3-55 to na na 2, 3-55 to na µa 2, 3-55 to µa High Level Input Current I AH V AH = 4.V µa All Unused Channels V AL =.8V 2, 3-55 to µa Supply Current +I CC All Channels V AL =.8V 1, 2 +25, ma ma All Channels V AH = 3.V 1, 2 +25, ma ma 2 FN8265. April 9, 212

3 HI-21HS/883 TABLE 1..C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) evice Tested at: +V SUPPLY = +15V, V SUPPLY = 15V, = V, unless otherwise specified..c. PARAMETERS SYMBOL CONITIONS GROUP A SUBGROUPS TEMPERATURE ( C) MIN MAX UNITS Supply Current -I CC All Channels V AL =.8V 1, 2 +25, ma ma All Channels V AH = 3.V 1, 2 +25, ma ma TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS evice Tested at: +V SUPPLY = +15V, V SUPPLY = 15V, = V, unless otherwise specified. PARAMETERS SYMBOL CONITIONS Turn ON Time t (ON) C L = 35pF, R L = V AH = 3.V, V AL -.8V Turn OFF Time t (OFF) C L = 35pF, R L = V AH = 3.V, V AL -.8V GROUP A SUBGROUPS TEMPERATURE ( C) MIN MAX UNITS ns 1, 11-55, ns ns 1, 11-55, ns TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1) evice Characterized at: +V SUPPLY = +15V, V SUPPLY = 15V, = V PARAMETERS SYMBOL CONITIONS NOTE TEMPERATURE ( C) MIN MAX UNITS Address Capacitance C A f = 1MHz, V AL = V pf Switch Input Capacitance C S (OFF) f = 1MHz, V AH = 5V, Measure Input to pf Switch Output Capacitance C (OFF) f = 1MHz, V AH = 5V, Measure Output to Ground C (ON) f = 1MHz, V AL = V, Measure Output to Ground pf pf rain to Source Capacitance C S f = 1MHz, V AH = 5V pf Off Isolation V ISO f = 1kHz, V A = 3., R L = 1k, db V GEN = 1V P-P, C L = 1pF Cross Talk V CT f = 1kHz, V A = 3., R L = 1k, V GEN = 1V P-P, C L = 1pF db Charge Transfer Error V CTE R L = 1k, C L =.1µF mv NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL REQUIREMENTS MIL-ST-883 REQUIREMENTS SUBGROUPS (Tables 1 and 2) Interim Electrical Parameters (Pre Burn-in) 1 Final Electrical Test Parameters 1 (Note 2), 2, 3, 9, 1, 11 Group A Test Requirements 1, 2, 3, 9, 1, 11 Groups C & Endpoints 1 NOTE: 2. PA applies to Subgroup 1 only. 3 FN8265. April 9, 212

4 HI-21HS/883 Test Circuits +V CC +V CC S S V S I V I IN -V CC -V CC FIGURE 1. INPUT LEAKAGE CURRENT FIGURE 2. I (OFF) +V CC +V CC V S I S V S I (ON) V -V CC -V CC FIGURE 3. I S(OFF) FIGURE 4. I (ON) +V CC I 1 S STEP GENERATOR (See Note) IN 1 15V STEP GENERATOR V+ IN 3 (See Note).1µF S 1 1 IN 2 S 3 3 IN 4.1µF I 2.1µF S 2 2 V- S 4 4.1µF -V CC -15V NOTE: The pulse generator has the following characteristics: V GEN =Vto3V, rise time 2ns, fall time 2ns, PRR = 1kHz. FIGURE 5. SUPPLY CURRENTS FIGURE 6. CHARGE TRANSFER ERROR 4 FN8265. April 9, 212

5 HI-21HS/883 Test Circuits (Continued) +V CC SINE WAVE GENERATOR (See Note) 2.4V A 1 S 1 15V V+ A 3 S 3 SINE WAVE GENERATOR (See Note) S 3.V 1 A 2 S 2 3 A 4 S 4 3.V V 2 V- 4 -V CC -15V NOTE: The pulse generator has the following characteristics: V GEN =1V P-P, Frequency = 1kHz. FIGURE 7. R S FIGURE 8. OFF CHANNEL ISOLATION 3.V.8V A 1 15V V+ A 3 3.V.8V 3.V.8V S 1 1 A 2 S 2 2 V- S 3 3 A 4 S V 3.V.8V SINE WAVE GENERATOR (See Note) NOTE: The pulse generator has the following characteristics: V GEN =1V P-P, Frequency = 1kHz. FIGURE 9. CROSSTALK BETWEEN CHANNELS 5 FN8265. April 9, 212

6 HI-21HS/883 Switching Waveforms (See Note 3) +3V R L = ±5% C L = 35pF ±5% Includes wiring and probe capacitance NOTES: 3. The pulse generator has the following characteristics: V GEN = 3.V, t THL 2ns 4. See Table 2 for complete terminal conditions FALL TIME RISE TIME IGITAL INPUT 5% 9% 5% 1% V IH = 3.V V GEN V IL =.V t ON t OFF CONITION A SWITCH OUTPUT V 9% 9% V CONITION B 9% 9% NOTE: Rise time and fall time 2ns. 6 FN8265. April 9, 212

7 HI-21HS/883 Burn-In Circuit HI-21HS/883 CERIP NOTE: R =, 5%, 1/4W or 1/2W. C 1 = C 2 =.1µF (per socket) or.1µf (per row). 1 = 2 = IN42 or equivalent (one per board). (V+) - (V-) = 3V. Schematic iagrams SWITCH CELL A Q MN31 ANALOG IN MP32 MP33 MN32 ANALOG OUT MN33 MP31 Q B 7 FN8265. April 9, 212

8 Schematic iagrams (Continued) HI-21HS/883 REFERENCE/LEVEL SHIFTER V+ P41 MP42 MP43 MP44 MP45 QN41 QN V R42 R41 QN43 C48 QP44 QN44 QN45 V R1 C49 Z42 5.6V QP41 QP42 MN42 MN44 MN45 V EE M N46 M P51 M P52 Q N6 Q N8 M P4 M P8 A Q N9 M P3 M P7 I Q I X3 I X4 I X1 Q N7 VR1 IX2 M P5 M P6 M P9 M P1 M P11 M P12 Q N1 VA C 1 R 1 R POLY Q P1 V R1 I Q Q P4 Q N4 Q P5 Q N5 R 3 R 2 Q N2 C 2 M N11 V EE V CC M P13 M N12 M P14 Q Q I X1 IX2 I X3 C FF Q P7 Q P6 I X4 Q P9 M N3 Q P2 M N5 M N4 M N6 M N7 M N9 M N8 M N1 M N13 M N14 Q P8 M N51 REPEAT FOR EACH LEVEL SHIFTER M N52 B 8 FN8265. April 9, 212

9 HI-21HS/883 ie Characteristics IE IMENSIONS: 92mils x 111mils x 19mils METALLIZATION: Type: Aluminum Thickness: 16kÅ ±2kÅ Metallization Mask Layout A1 HI-21HS/883 GLASSIVATION: Type: Nitride Nitride Thickness: 7kÅ ±.7kÅ WORST CASE CURRENT ENSITY: 4.5 x 1 5 A/cm 2 at 25mA This device meets Glassivation Integrity Test requirement per Mil-Std-883 Method 221 and Mil-M-3851 paragraph A2 OUT1 OUT2 IN1 IN2 V- V+ IN4 IN3 OUT4 OUT3 A4 A3 9 FN8265. April 9, 212

10 HI-21HS/883 The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves T A = +25 C, V SUPPLY = ±15V, V AH = 3.V, V AL =.8V T A = +25 C V+ = +8V, V- = -8V ON RESISTANCE (Ω) C +25 C -55 C ON RESISTANCE (Ω) V+ = +1V, V- = -1V V+ = +12V, V- = -12V ANALOG INPUT (V) FIGURE 1. ON RESISTANCE vs ANALOG SIGNAL LEVEL AN TEMPERATURE ANALOG INPUT (V) FIGURE 11. ON RESISTANCE vs ANALOG SIGNAL LEVEL AN POWER SUPPLY VOLTAGE LEAKAGE CURRENT (na) LEAKAGE CURRENT (na) TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 12. I S(OFF) OR I (OFF) vs TEMPERATURE FIGURE 13. I (ON) vs TEMPERATURE SUPPLY CURRENT (ma) I+ 4 I TEMPERATURE ( C) LEAKAGE CURRENT (pa) I S(OFF) V = V I (OFF) V S = V -8 I (ON) I S(OFF) /I (OFF) ANALOG INPUT (V) FIGURE 14. SUPPLY CURRENT vs TEMPERATURE FIGURE 15. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE 1 FN8265. April 9, 212

11 HI-21HS/883 The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves T A = +25 C, V SUPPLY = ±15V, V AH = 3.V, V AL =.8V (Continued) LEAKAGE CURRENT (µa) 6 4 V AL = V, V AH2 = 3V, V AH1 = 5V TEMPERATURE ( C) FIGURE 16. IGITAL INPUT LEAKAGE CURRENT vs TEMPERATURE 95 I AH1 I AH2 I AL 115 LEAKAGE CURRENT (na) 1 9, T A = +25 C 8 I 7 S(OFF) V = V 6 I (OFF) V S = V ANALOG INPUT (V) FIGURE 17. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE 16. SWITCHING TIME (ns) t OFF2 t OFF1 t ON V+ = +15V V- = -15V R L = C L = 35pF SWITCHING TIME (ns) R L =, C L = 35pF, T A = +25 C t OFF2 t OFF1 t ON TEMPERATURE ( C) FIGURE 18. SWITCHING TIME vs TEMPERATURE POSITIVE AN NEGATIVE SUPPLY VOLTAGE (±V) FIGURE 19. SWITCHING TIME vs POSITIVE AN NEGATIVE SUPPLY VOLTAGE 35 3 V- = -15V, R L = C L = 35pF, T A = +25 C 35 3 V+ = +15V, R L = C L = 35pF, T A = +25 C SWITCHING TIME (ns) t OFF2 t OFF1 SWITCHING TIME (ns) t ON t OFF2 t OFF1 t ON POSITIVE SUPPLY (V) NEGATIVE SUPPLY (V) FIGURE 2. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 21. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE 11 FN8265. April 9, 212

12 HI-21HS/883 The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves T A = +25 C, V SUPPLY = ±15V, V AH = 3.V, V AL =.8V (Continued) SWITCHING TIME (ns) 35 V + = +15V, V- = -15V, R L = 3 C L = 35pF, V AL = V, T A = +25 C 25 2 t OFF t 5 OFF1 t ON IGITAL INPUT AMPLITUE (V) FIGURE 22. SWITCHING TIME vs INPUT LOGIC AMPLITUE INPUT LOGIC THRESHOL (V) SUPPLY VOLTAGE (±V) FIGURE 23. INPUT SWITCHING THRESHOL vs POSITIVE AN NEGATIVE SUPPLY VOLTAGE CHARGE INJECTION (pc) IN OUT ΔV O V A ΔQ O = C L x ΔV O C L Q OUT -3-4 C L = 1nF, R IN = Ω ANALOG INPUT (V) FIGURE 24. CHARGE INJECTION vs ANALOG INPUT CAPACITANCE (pf) 4 35 C (ON) C (OFF) OR C S(OFF) 1 5 C S(OFF) ANALOG INPUT (V) FIGURE 25. CAPACITANCE vs ANALOG INPUT = 3V RMS, V A = 3V = 3V RMS, V A = 3V OFF ISOLATION (db) IN OUT V O R L = 2 OFF ISOLATION = 2 Log V O 1k 1k FREQUENCY (Hz) R L = 1Ω R L = 1M 1M CROSSTALK (db) 1 IN k OUT V O1 R L = V O2 R L = V O2 CROSSTALK = 2 Log V O1 1k 1M FREQUENCY (Hz) 1M FIGURE 26. OFF ISOLATION vs FREQUENCY FIGURE 27. CROSSTALK vs FREQUENCY 12 FN8265. April 9, 212

13 HI-21HS/883 Ceramic ual-in-line Frit Seal Packages (CERIP) BASE PLANE SEATING PLANE S1 b2 ccc M bbb S b C A - B C A - B S A A e S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. imensions b1 and c1 apply to lead base metal only. imension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. imension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. imensioning and tolerancing per ANSI Y14.5M Controlling dimension: INCH. E L M c1 ea/2 S S aaa M C A - B LEA FINISH BASE METAL b1 M (b) SECTION A-A -- -A- Q -C- A -Bα S ea c S (c) F16.3 MIL-ST-1835 GIP1-T16 (-2, CONFIGURATION A) 16 LEA CERAMIC UAL-IN-LINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c E e.1 BSC 2.54 BSC - ea.3 BSC 7.62 BSC - ea/2.15 BSC 3.81 BSC - L Q S α 9 o 15 o 9 o 15 o - aaa bbb ccc M , 3 N Rev. 4/94 For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 13 FN8265. April 9, 212