Performance Metrics & Architectural Adaptivity. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So
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1 Performance Metrics & Architectural Adaptivity ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So
2 What are the Options? Power Consumption Activity factor (amount of circuit switching) Load Capacitance (size of circuit) Voltage Swing Supply Voltage Clock frequency P total = α( C L V sw V dd f ) clk + I sc V dd + I leakage V dd Dynamic Static Energy per operation Total Energy Consumption E op P dyn / f clk = α C L V sw V dd E total = E op no. of operations Total Run Time T total = no. of operations CPI / f clk H. So, Sp10 Lecture 4 - ELEC8106/6102 2
3 Metrics How do we quantify Performance, Power and Energy? How do we quantify Energy Efficiency? Many different quantities: Power-delay product Energy-delay product Performance/Power Performance 2 /Power H. So, Sp10 Lecture 4 - ELEC8106/6102 3
4 Absolute wall clock time Measures the absolute wall clock time to finish a task Compared to virtual OS time, etc Measure in seconds Includes all overhead from hardware, software, as well as the OS Cons Doesn t tell you the portion of time spent because of time sharing machine, OS overhead, etc Solution: run in single-user mode H. So, Sp10 Lecture 4 - ELEC8106/6102 4
5 IPS, kips, MIPS, bips IPS = instruction per second Measures throughput of a computer A very simple first-order estimation of how much work a computer can perform per unit time. A machine that completes 1 instruction per cycle running at 1 Megahertz = 1 MIPS Varies GREATLY depending on the input benchmark IPS = IPC * Cycle per second (Hz) Very often used, but can be very misleading H. So, Sp10 Lecture 4 - ELEC8106/6102 5
6 FLOPS Floating Point Operations per Second Similarly calculated as MIPS A machine that performs 1 floating point operation per cycle running at 1 MHz is running at 1 FLOPS Similar to MIPS, FLOPS rating of a system depends highly on the input workload Also, system performances, e.g. memory, bus E.g. top500 list use FLOPS to measure super computers using LINPACK The sustained FLOPS of a system is used to rank, not the theoretical peak. H. So, Sp10 Lecture 4 - ELEC8106/6102 6
7 Energy and Power Power: Watt (W) Energy: Joules (J) kwh, (mah?) Power = Energy consumed per unit time H. So, Sp10 Lecture 4 - ELEC8106/6102 7
8 Energy efficiency How much performance can you get per unit of energy spent Three possible measurements: 1. Power/Throughput 2. Power/Throughput 2 3. BIPS/w H. So, Sp10 Lecture 4 - ELEC8106/6102 8
9 Power/Throughput Good for fixed throughput systems Such as DSP systems Data stream into system and processed continuously Power Throughput = Energy/time Operation/time = Energy Operation In such fixed throughput systems, number of operation per unit time is constant Drawback: Doesn t take performance into account System A may be better than System B in terms of Energy/Op, but System B may be much faster Similar to Power-Delay-Product in circuit design H. So, Sp10 Lecture 4 - ELEC8106/6102 9
10 Power/Throughput 2 ETR = E MAX T MAX = Power Throughput 2 Balances both Energy/Op and Throughput If system A has lower ETR than System B, then either 1. A has lower energy/op than B at the same throughput, OR 2. A has higher throughput than B at the same energy/op Similar to Energy-Delay-Product in circuit designs, But hasn t taken into account architectural effects H. So, Sp10 Lecture 4 - ELEC8106/
11 Optimizing ETR Need to apply powerdelay tradeoff Vdd scaling only works within a limited range Frequency scaling alone doesn t work Frequency doesn t affect E/op lowered frequency decrease throughput higher ETR H. So, Sp10 Lecture 4 - ELEC8106/
12 Optimizing ETR Algorithm and Architectural changes most effective! Architecture: If a machine can perform S operations at the same time, throughput is increased by S while energy/op is constant ETR decreased by S Algorithm: If the length of an application is reduced by a factor of S Then, switching capacitance is reduced by S, throughput increased by S, so ETR is reduced by S 2 H. So, Sp10 Lecture 4 - ELEC8106/
13 FPGA coprocessing on ETR Offloading computation to FPGA very likely improve ETR 1. Decreases code size in sw (S 2 factor) 2. Decreases overall run time (overall E) 3. Increases operation/cycle But Increased seconds/cycle decreases operation per second H. So, Sp10 Lecture 4 - ELEC8106/
14 Efficiency Trends and Limits from Comprehensive Microarchitectural Adaptivity Benjamin C. Lee and David Brooks, ASPLOS 08 H. So, Sp10 Lecture 4 - ELEC8106/
15 Overview Studied the effectiveness of architectural adaptation 15 different architectural parameters are adapted to the running application both temporally and spatially H. So, Sp10 Lecture 4 - ELEC8106/
16 Overview Temporal and Spatial sampling to reduce exploration space Genetic algorithm is used to find optimal configuration for an application at a given time H. So, Sp10 Lecture 4 - ELEC8106/
17 BIPS 3 per Watt Lee and Brooks used bips 3 /w as a metrics Argument: voltage invariant w V 2 f and f V w f 3 bips f Similar to Power Throughput 3 bips3 w = k What s the catch? H. So, Sp10 Lecture 4 - ELEC8106/
18 Temporal Adaptivity Improved power Improved performance Optimal architecture evaluated after a block of instructions have been executed Any or all of the 15 parameters can be adapted to their optimal values. Higher temporal adativity higher overall efficiency H. So, Sp10 Lecture 4 - ELEC8106/
19 Parameter Adaptation High temporal adaptivity smaller # of parameters changed smaller parameter delta values more high value changes H. So, Sp10 Lecture 4 - ELEC8106/
20 Spatial Adapativity What if not all 15 parameters can be changed at the same time? Pick the 3 optimal parameters? Which 3? H. So, Sp10 Lecture 4 - ELEC8106/
21 Limited spatial adaptivitiy Most benefits come from the 3 most important parameters But Some benchmarks require adapting all 15 parameters to be effective H. So, Sp10 Lecture 4 - ELEC8106/
22 DVFS as adaptation Each bar relative to case w/o DVFS During each iteration, after spatial parameters are changed, adjust voltage and the corresponding frequency to maximize m3pw Since all bars relative to th H. So, Sp10 Lecture 4 - ELEC8106/
23 DVFS as adaptation Each bar relative to case w/o DVFS During each iteration, after spatial parameters are changed, adjust voltage and the corresponding frequency to maximize m3pw DVFS only useful in a few cases in static (non-adapting) cases Why? H. So, Sp10 Lecture 4 - ELEC8106/
24 In conclusion Metrics for energy efficiency must be carefully constructed to suit actual need Energy/Throughput seems reasonable for this class Throughput 3 /Power also used Offloading computation to reconfigurable hardware accelerators can significantly improve energy efficiency metrics Reconfigurable systems allow flexible tradeoffs in energy efficiency tradeoff Reconfigurable systems allow run time architectural adaptation that can improve energy efficiency by factor of 5 H. So, Sp10 Lecture 4 - ELEC8106/
Performance, Power & Energy. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So
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