Revision No History Draft Date Remark. 00 Initial Draft Dec Preliminary. 01 Package Height Changed 1.0mm -> 0.9mm Mar.05.
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1 256Kx16bit full MOS SRM Document Title 256K x16 bit 2.7 ~ 3.3V Super Low Power FMOS Slow SRM Revision History Revision No History Draft Date Remark 00 Initial Draft Dec Preliminary 01 Package Height hanged 1.0mm -> 0.9mm Mar Preliminary 02 dd Package Size Option (6.0mmx8.0mm) Feb Final This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Hynix Semiconductor
2 DESRIPTION The HY62UF16404E is a high speed, super low power and 4Mbit full MOS SRM organized as 256K words by 16bits. The HY62UF16404E uses high performance full MOS process technology and is designed for high speed and low power circuit technology. It is particularly well-suited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. Fully static operation and Tri-state output TTL compatible inputs and outputs Battery backup V(min) data retention Standard pin configuration ball FBG FETURES Product No. Standby Voltage Operation Temperature Speed (ns) urrent(u) (V) urrent/icc(m) ( ) SL LL HY62UF16404E-I 2.7~3.3 55/ ~85 Note 1. I : Industrial 2. urrent value is max. PIN ONNETION BLOK DIGRM B D E F G H /LB /OE N IO9 /UB 3 4 /S IO1 IO10 IO IO2 IO3 Vss IO IO4 Vcc Vcc IO13 N 16 IO5 Vss IO15 IO IO6 IO7 IO16 N /WE IO8 N N 0 17 /S DD INPUT BUFFER PRE DEODER OLUMN DEODER BLOK DEODER ROW DEODER MEMORY RRY 256K x 16 SENSE MP WRITE DRIVER DT I/O BUFFER I/O1 I/O8 I/O9 I/O16 FBG /OE /LB /UB /WE PIN DESRIPTION Pin Name Pin Function Pin Name Pin Function /S hip Select I/O1~I/O16 Data Inputs/Outputs /WE Write Enable 0~17 ddress Inputs /OE Output Enable Vcc Power (2.7~3.3V) /LB Lower Byte ontrol (I/O1~I/O8) Vss Ground /UB Upper Byte ontrol (I/O9~I/O16) N No onnection 2
3 ORDERING INFORMTION Part No. Speed Power Temp. Package HY62UF16404E-SF(I) 55/70 SL-part I FBG HY62UF16404E-DF(I) 55/70 LL-part I FBG Note 1. I : Industrial BSOLUTE MXIMUM RTINGS (1) Symbol Parameter Rating Unit Remark VIN, VOUT Input/Output Voltage -0.3 to V+0.3V V Vcc Power Supply -0.3 to 3.6 V T Operating Temperature -40 to 85 HY62UF16404E-I TSTG Storage Temperature -55 to 150 PD Power Dissipation 1.0 W TSOLDER Ball Soldering Temperature & Time sec Note 1. Stresses greater than those listed under BSOLUTE MXIMUM RTINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TBLE I/O Pin /S /WE /OE /LB /UB Mode Power I/O1~I/O8 I/O9~I/O16 H X X X X Deselected High-Z High-Z Standby X X X H H L X L H H Output Disabled High-Z High-Z ctive X L L H DOUT High-Z L H L H L Read High-Z DOUT ctive L L DOUT DOUT L H DIN High-Z L L X H L Write High-Z DIN ctive L L DIN DIN Note: 1. H=VIH, L=VIL, X=don't care (VIL or VIH) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16. 2
4 REOMMENDED D OPERTING ONDITION Symbol Parameter Min. Typ Max. Unit Vcc Supply Voltage V Vss Ground V VIH Input High Voltage Vcc+0.3 V VIL Input Low Voltage V Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns 2. Undershoot is sampled, not 100% tested. D ELETRIL HRTERISTIS T = -40 to 85 Sym Parameter Test ondition Min Typ 1. Max Unit ILI Input Leakage urrent Vss < VIN < Vcc -1-1 u ILO Output Leakage urrent Vss < VOUT < Vcc, /S = VIH or /OE = VIH or /WE = VIL or -1-1 u /UB = VIH, /LB = VIH Icc Operating Power Supply urrent /S = VIL, VIN = VIH or VIL, II/O = 0m 3 m /S = VIL, VIN = VIH or VIL, 55ns 20 m I1 verage Operating urrent ycle Time = Min, 100% Duty, II/O = 0m 70ns 15 m /S < 0.2V, VIN < 0.2V or VIN > Vcc-0.2V, ycle Time = 1us, 2 m 100% Duty, II/O = 0m ISB Standby urrent (TTL Input) /S = VIH or /UB, /LB = VIH VIN = VIH or VIL 300 u ISB1 Standby urrent (MOS Input) /S > Vcc - 0.2V or /UB, /LB > Vcc - 0.2V SL u VIN > Vcc - 0.2V or VIN < Vss + 0.2V LL u VOL Output Low IOL = 2.1m V VOH Output High IOH = -1.0m V Note 1. Typical values are at Vcc = 3.0V T = Typical values are not 100% tested PITNE (Temp = 25, f= 1.0MHz) Symbol Parameter ondition Max. Unit IN Input apacitance(dd, /S,/LB,/UB, /WE, /OE) VIN = 0V 8 pf OUT Output apacitance(i/o) VI/O = 0V 10 pf Note : These parameters are sampled and not 100% tested 3
5 HRTERISTIS T = -40 to 85, unless otherwise specified # Symbol Parameter 55ns 70ns Min. Max. Min. Max. Unit RED YLE 1 tr Read ycle Time ns 2 t ddress ccess Time ns 3 ts hip Select ccess Time ns 4 toe Output Enable to Output Valid ns 5 tb /LB, /UB ccess Time ns 6 tlz hip Select to Output in Low Z ns 7 tolz Output Enable to Output in Low Z ns 8 tblz /LB, /UB Enable to Output in Low Z ns 9 thz hip Deselection to Output in High Z ns 10 tohz Out Disable to Output in High Z ns 11 tbhz /LB, /UB Disable to Output in High Z ns 12 toh Output Hold from ddress hange ns WRITE YLE 13 tw Write ycle Time ns 14 tw hip Selection to End of Write ns 15 tw ddress Valid to End of Write ns 16 tbw /LB, /UB Valid to End of Write ns 17 ts ddress Set-up Time ns 18 twp Write Pulse Width ns 19 twr Write Recovery Time ns 20 twhz Write to Output in High Z ns 21 tdw Data to Write Time Overlap ns 22 tdh Data Hold from Write Time ns 23 tow Output ctive from End of Write ns TEST ONDITIONS T = -40 to 85, unless otherwise specified Parameter Value Input Pulse Level 0.4V to 2.2V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load tlz, tolz, tblz, thz, tohz, tbhz, twhz, tow L = 30pF + 1TTL Load Others L = 30pF + 1TTL Load TEST LODS V TM =2.8V 1029 Ohm D OUT L(1) 1728 Ohm Note 1. Including jig and scope capacitance: 4
6 TIMING DIGRM RED YLE 1 (Note 1,4) DDR tr /S t ts toh /UB,/ LB tb thz(3) /OE toe tbhz(3) Data Out High-Z tolz(3) tblz(3) tlz(3) tohz(3) Data Valid RED YLE 2 (Note 1,2,4) tr DDR toh t toh Data Out Previous Data Data Valid RED YLE 3(Note 1,2,4) /S /UB, /LB ts tlz(3) thz(3) Data Out Data Valid Notes: 1. read occurs during the overlap of a low /OE, a high /WE, a low /S and /UB and/or /LB. 2. /OE = VIL 3. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. /S in high for the standby, low for active /UB and /LB in high for the standby, low for active 5
7 WRITE YLE 1 (1,4,8) (/WE ontrolled) tw DDR /S /UB,/LB tw tw tbw twr(2) /WE ts twp tdw tdh Data In High-Z Data Valid Data Out twhz(3,7) tow (5) (6) WRITE YLE 2 (Note 1,4,8) (/S ontrolled) tw DDR ts tw twr(2) /S tw tbw /UB,/LB /WE twp Data In High-Z tdw Data Valid tdh Data Out High-Z 6
8 Notes: 1. write occurs during the overlap of a low /WE, a low /S and a low /UB and/or /LB. 2. twr is measured from the earlier of /S, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /S, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. /S in high for the standby, low for active /UB and /LB in high for the standby, low for active DT RETENTION ELETRI HRTERISTI T = -40 to 85 Symbol Parameter Test ondition Min Typ 1. Max Unit VDR Vcc for Data Retention /S > Vcc - 0.2V or /UB, /LB > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V V Vcc=1.5V, /S > Vcc - 0.2V or SL u Iccdr Data Retention urrent /UB, /LB > Vcc - 0.2V VIN > Vcc - 0.2V or VIN < Vss + 0.2V LL u tdr hip Deselect to Data Retention Time See Data Retention Timing Diagram ns tr Operating Recovery Time tr - - ns Notes: 1. Typical values are under the condition of T = Typical value are sampled and not 100% tested DT RETENTION TIMING DIGRM V DT RETENTION MODE 2.7V tdr tr VIH VDR /S /S >V-0.2V VSS 7
9 PKGE INFORMTION (6.0mm X 7.0mm) 48ball Fine Pitch Ball Grid rray Package (F) BOTTOM VIEW B 1 ORNER INDEX RE TOP VIEW B D E F G 1/2 H 1 B1/2 B1 SIDE VIEW 5 E1 E r E2 SETING PLNE 4 3 D(DIMETER) Symbol Min. Typ. Max B B D E E E r Note 1. DIMENSIONING ND TOLERNING PER SME Y14. 5M LL DIMENSIONS RE MILLIMETERS. 3. DIMENSION D IS MESURED T THE MXIMUM SOLDER BLL DIMETER IN PLNE PRLLEL TO DTUM. 4. PRIMRY DTUM (SETING PLNE) IS DEFINED BY THE ROWN OF THE SOLDER BLLS. 5. THIS IS ONTROLLING DIMENSION. 8
10 PKGE INFORMTION (6.0mm X 8.0mm) 48ball Fine Pitch Ball Grid rray Package(F) BOTTOM VIEW B 1 ORNER B1/2 INDEX RE TOP VIEW B D E F G 1/2 1/2 H 1 B1/2 B1 SIDE VIEW 5 E1 E r E2 SETING PLNE 4 3 D(DIMETER) Symbol Min. Typ. Max B B D E E E r Note 1. DIMENSIONING ND TOLERNING PER SME Y14. 5M LL DIMENSIONS RE MILLIMETERS. 3. DIMENSION D IS MESURED T THE MXIMUM SOLDER BLL DIMETER IN PLNE PRLLEL TO DTUM. 4. PRIMRY DTUM (SETING PLNE) IS DEFINED BY THE ROWN OF THE SOLDER BLLS. 5. THIS IS ONTROLLING DIMENSION. 9
11 MRKING INFORMTION Package Marking Example H Y U F E FBG c s s t y w w p x x x x x K O R Index HYUF6404E : Part Name c : Power onsumption - D : Low Low Power - S : Super Low Power ss : Speed - 50 : 55ns - 70 : 70ns t : Temperature - I : Industrial ( -40 ~ 85 ) y : Year (ex : 2 = year 2002, 3= year 2003) ww : Work Week ( ex : 12 = work week 12 ) p : Process ode - (6.0mm X 7.0mm) - B (6.0mm X 8.0mm) xxxxx KOR : Lot No. : Origin ountry Note - apital Letter : Fixed Item - Small Letter : Non-fixed Item 10
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74LCX16374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
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74AUP1G59 TinyLogic Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
74UP1G9 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Features 0.8V to.v V Supply Operation.V Over-Voltage Tolerant I/Os at V from 0.8V to.v Extremely High Speed tpd
LH5P832. CMOS 256K (32K 8) Pseudo-Static RAM
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ML ML Digital to Analog Converters with Serial Interface
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2M x 32 Bit 5V FPM SIMM. Fast Page Mode (FPM) DRAM SIMM S51T04JD Pin 2Mx32 FPM SIMM Unbuffered, 1k Refresh, 5V. General Description.
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7S32 us Switch The 7S32 us Switch is an advanced high speed line switch in ultra small footprint. Features High Speed: t PD = 0.2 ns (Max) @ V =. V 3 Switch onnection etween 2 Ports Power Down Protection
PO3B14A. Description. Truth Table. High Bandwidth Potato Chip V CC N.C. EN EN S 1 A 3 B 3 B 2 A 2 A 1 B 1 Y A Y B GND
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Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and
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MM74HC573 3-STATE Octal D-Type Latch
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PYA28C16 2K X 8 EEPROM FEATURES Access Times of 150, 200, 250 and 350ns Single 5V±10% Power Supply Fast Byte Write (200µs or 1 ms) Low Power CMOS: - 60 ma Active Current - 150 µa Standby Current Endurance:
74ACT825 8-Bit D-Type Flip-Flop
8-Bit D-Type Flip-Flop General Description The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming
MC74VHC1G05. Single Inverter with Open Drain Output
Single Inverter with Open Drain Output The is an advanced high speed MOS inverter with open drain output fabricated with silicon gate MOS technology. The internal circuit is composed of three stages, including
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Ultrafast Rectifier, x 5 FRED Pt ommon cathode, Base FETURES Ultrafast recovery time Low forward voltage drop 75 operating junction temperature 3 TO-47 3L node 3 node Low leakage current Designed and qualified
MR48V256A GENERAL DESCRIPTION FEATURES PRODUCT FAMILY. PEDR48V256A-06 Issue Date: Oct. 17, 2011
32,768-Word 8-Bit FeRAM (Ferroelectric Random Access Memory) PEDR48V256A-06 Issue Date: Oct. 17, 2011 GENERAL DESCRIPTION The is a nonvolatile 32,768-word x 8-bit ferroelectric random access memory (FeRAM)
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MM70C95 MM80C95 MM70C97 MM80C97 TRI-STATE Hex Buffers MM70C96 MM80C96 MM70C98 MM80C98 TRI-STATE Hex Inverters General Description These gates are monolithic complementary MOS (CMOS) integrated circuits
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
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CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
MM74HC374 3-STATE Octal D-Type Flip-Flop
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MC74AC244, MC74ACT244. Octal Buffer/Line Driver with 3 State Outputs
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SRAM with ZBT Feature Burst Counter and Pipelined Outputs
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DLA LAND AND MARITIME COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, CMOS SPDT SWITCH, MONOLITHIC SILICON REVISIONS
REVISIONS LTR DESCRIPTION DTE PPROVED Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/ PREPRED BY RICK OFFICER
DatasheetDirect.com. Visit to get your free datasheets. This datasheet has been downloaded by
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The 74LV08 provides a quad 2-input AND function.
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R1RW0416D Series. 4M High Speed SRAM (256-kword 16-bit) Description. Features. REJ03C Z Rev Mar
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Hex inverting Schmitt trigger with 5 V tolerant input
Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible
XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger
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SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
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NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register
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NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
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HN27C4096AHG/AHCC Series
262,144-word 16-bit CMOS UV Erasable and Programmable ROM ADE-203-247A(Z) Rev. 1.0 Apr. 4, 1997 Description HN27C4096AHG/AHCC is a 4-Mbit ultraviolet erasable and electrically programmable ROM, featuring
The 74HC21 provide the 4-input AND function.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
SN54HC151, SN74HC151 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SNH, SNH 8-Line to -Line Multiplexers an Perform as: oolean Function enerators Parallel-to-Serial onverters Data Source Selectors Package Options Include Plastic Small-Outline (D) and eramic Flat () Packages,
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. *MR for LS160A and LS161A *SR for LS162A and LS163A
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HB56A1636B/SB-6B/7B/8B
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Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
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DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS FEATURES:. Patented technology. Specified From 0 C to 12 C, C to 12 C. Operating frequency is faster than 600MHz. VCC Operates from 1.6V to 3.6V. Propagation
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N-Channel Enhancement-Mode Vertical DMOS FET Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability Integral
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128K x 16 SRAM & 512K x 16 FLASH SRAM / FLASH MEMORY ARRAY SRAM & FLASH PIN ASSIGNMENT (Top View) 68 Lead CQFP (QT) FEATURES Operation with single 5V supply High speed: 35ns SRAM, 90ns FLASH Built in decoupling
74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
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