74AUP1G95 TinyLogic Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

Transcription

1 74UPG9 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Features 0.8 V to.6 V V Supply Operation.6 V Over-Voltage Tolerant I/Os at V from 0.8V to.6 V Extremely High Speed tpd -. ns: Typical at. V Power-Off High-Impedance Inputs and Outputs Low Static Power onsumption - I =0.9 µ Maximum Low Dynamic Power onsumption - PD =.0 pf Typical at. V Ultra-Small MicroPak Packages Ordering Information Description September 0 The 74UPG9 is a universal, configurable, two-input logic gate with an open-drain output that provides a high-performance and low-power solution for batterypowered portable applications. This product is designed for a wide low voltage operating range (0.8 V to.6 V) and guarantees very low static and dynamic power consumption across the entire voltage range. ll inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. The 74UPG9 provides for multiple functions, as determined by various configurations of the three inputs. The potential logic functions provided are MUX, ND, OR, NND, NOR, inverter, and buffer (see Figure through Figure 8). Part Number Top Mark Package Packing Method 74UPG9L6X N 6-Lead, MicroPak,.0 mm Wide 000 Units on Tape & Reel 74UPG9FHX N 6-Lead, MicroPak, x mm ody,. mm Pitch 000 Units on Tape & Reel 74UPG9 Rev..0.

2 Pin onfiguration Pin Definitions Function Table Figure. 6 4 V MicroPak (Top Through View) Pin # Name Description Data Input Ground Data Input 4 Output (Open Drain) V Supply Voltage 6 Data Input Inputs =Output L L L L L L H L L H L H ( L H H H () H L L L H L H H () H H L L H H H H () H = HIGH Logic Level L = LOW Logic Level Note:. High impedance output state, open drain. Function Selection Table -Input Logic Function onnection onfiguration -to- MUX Figure -Input ND Gate Figure -Input OR Gate with One Inverted Input Figure 4 -Input NND Gate with One Inverted Input Figure 4 -Input ND Gate with One Inverted Input Figure -Input NOR Gate with One Inverted Input Figure -Input OR Gate Figure 6 Inverted Figure 7 uffer Figure 8 74UPG9 Rev..0.

3 Logic onfigurations Figure through Figure 8 show the logical functions that can be implemented using the 74UPG9. The diagrams show the DeMorgan s equivalent logic duals for a given two-input function. The logical V implementation is next to the board-level physical implementation of how the pins should be connected Notes:. When is L, =.. When is H, =. Figure. -to- MUX Figure. -Input ND Gate 6 4 V Figure 4. -Input OR Gate with One Inverted Input -Input NND Gate with One Inverted Input 6 4 V 6 4 V V Figure. -Input ND Gate with One Inverted Input -Input NOR Gate with One Inverted Input Figure 6. -Input OR Gate Figure 7. Inverter 6 4 V 6 4 V Figure 8. uffer 74UPG9 Rev..0.

4 bsolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V Supply Voltage V V IN D Input Voltage V V OUT () D Output Voltage V I IK D Input Diode urrent V IN < 0 V -0 m I OK D Output Diode urrent V OUT < 0 V -0 m I OL D Output Sink urrent +0 m I or I D V or Ground urrent per Supply Pin ±0 m T STG Storage Temperature Range T J Junction Temperature Under ias +0 T L Junction Lead Temperature, Soldering 0s +60 P D ESD Power Dissipation at +8 MicroPak -6 0 MicroPak -6 0 Human ody Model, JEDE:JESD harged Device Model, JEDE:JESD Note:. I O absolute maximum rating must be observed. Recommended Operating onditions () The Recommended Operating onditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to bsolute Maximum Ratings. Symbol Parameter ondition Min. Max. Unit V Supply Voltage V V IN Input Voltage 0.6 V V OUT Output Voltage 0.6 V I OL Output urrent V =.0 V to.6 V ±4.0 V =. V to.7 V ±. V =.6 V to.9 V ±.9 V =.4 V to.6 V ±.7 V =. V to. V ±. mw V =0.8 V ±0.0 µ T Operating Temperature, Free ir V m θ J Thermal Resistance MicroPak MicroPak Note:. Unused inputs must be held HIGH or LOW. They may not float. /W 74UPG9 Rev..0. 4

5 D Electrical haracteristics Symbol Parameter V ondition V P V N V H V OL I IN I OFF ΔI OFF I ΔI Positive Threshold Voltage Negative Threshold Voltage Hysteresis Voltage LOW Level Output Voltage Input Leakage urrent Power Off Leakage urrent dditional Power Off Leakage urrent Quiescent Supply urrent Increase in I per Input T = T =-40 to 8 Min. Max. Min. Max V.60 I OL =0 µ V.0 I OL =. m 0.0 x V 0.0 x V.40 V.60 I OL =.7 m V.9 I OL =.9 m V.70 I OL =. m V.60 I OL =4.0 m V to.6v 0 V IN.6 V ±0. ±0. µ 0V 0V to 0.V 0.8V to.6v 0 (V IN,V O ).6 V V IN or V O =0 V to.6 V Unit µ µ V IN - V or V V IN.6 V ±0.9.V V IN =V -0.6 V µ V V V V µ 74UPG9 Rev..0.

6 Electrical haracteristics T = T =-40 to 8 Symbol Parameter V ondition Unit Min. Typ. Max. Min. Max V L = pf, Propagation.40 V.60 R t PZL, t U =R D = KΩ PLZ Delay.6 V.9 V I = x (V ) (see Figure 9).0 V IN OUT PD Input apacitance Output apacitance Power Dissipation apacitance.00 V pf 0.7 pf V V.60 V IN =0 V or V,..6 V.9 f=0 MHz.4.0 V V pf 74UPG9 Rev..0. 6

7 Loadings and Waveforms Notes: 4. L includes load and stray capacitance.. Input PRR =.0 MHz, t W = 00 ns. Symbol Figure 9. Figure 0. Test ircuit Waveforms V. V ± 0. V. V ± 0. V.8 V ± 0. V. V ± 0.0 V. V ± 0.0 V 0.8 V V mi V / V / V / V / V / V / V mo V OL + 0. V V OL + 0. V V OL + 0. V V OL + 0. V V OL + 0. V V OL + 0. V 74UPG9 Rev..0. 7

8 Physical Dimensions X PIN IDENTIFIER DETIL (0.0) 6X 0.MX.4 TOP VIEW.0 0. OTTOM VIEW X Notes:. ONFORMS TO JEDE STNDRD M0- VRITION UD. DIMENSIONS RE IN MILLIMETERS. DRWING ONFORMS TO SME 4.M FILENME ND REVISION: M06REV4. PIN ONE IDENTIFIER IS X LENGTH OF N OTHER LINE IN THE MRK ODE LOUT. Figure. (0.4) 6X (0.49) X (0.) X PIN X X (0.) 4X 0.07 X 4 HMFER 6-Lead, MicroPak,.0 mm Wide () (0.0) 6X REOMMENED LND PTTERN X (0.7) DETIL PIN TERMINL Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section avity Number avity Status over Type Status Leader (Start End) (Typical) Empty Sealed L6X arrier 000 Filled Sealed Trailer (Hub End) 7 (Typical) Empty Sealed 74UPG9 Rev..0. 8

9 Physical Dimensions X X NOTES: 0.0 PIN MIN 0uM (0.08) 4X DETIL TOP VIEW SIDE VIEW 6 4 OTTOM VIEW.00. OMPLIES TO JEDE MO- STNDRD. DIMENSIONS RE IN MILLIMETERS.. DIMENSIONS ND TOLERNES PER SME 4.M, 994 D. LNDPTTERN REOMMENDTION IS SED ON FS DESIGN. E. DRWING FILENME ND REVISION: MGF06REV Figure. 0.MX (0.08) 4X X 0.0 6X X 0.40 X 0.4 X 0. X X4 HMFER (0.0) 6X X X 0.66 REOMMENDED LND PTTERN FOR SPE ONSTRINED P LTERNTIVE LND PTTERN FOR UNIVERSL PPLITION DETIL PIN LED SLE: X 6-Lead, MicroPak, x mm ody,. mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section avity Number avity Status over Type Status Leader (Start End) (Typical) Empty Sealed FHX arrier 000 Filled Sealed Trailer (Hub End) 7 (Typical) Empty Sealed 74UPG9 Rev..0. 9

10 74UPG9 Rev..0. 0