AKD4128A-A --- Evaluation board for AK4128A (A cable for connecting with USB port of IBM-AT compatible PC a control software are packed with this.

Transcription

1 [K8-] K8- K8- valuation oard Rev.0 GNRL SRIPTION The K8- is an evaluation board for K8, the digital sample rate converter. The K8- has the digital audio interface and can achieve the interface with digital audio system via optical or coaxial connector. Ordering guide K valuation board for K8 ( cable for connecting with US port of IM-T compatible P a control software are packed with this.) FUNTION IR/IT with optical or coaxial input/output 0pin Header for KM / evaluation board Opt In K (IR).V- V V V.V- OX 0pin Header Regu lator Regu lator Regu lator Opt In OX K (IR) K8 K (IT) Opt Out 0pin Header 0pin Header OX Opt In K (IR) OX 0pin Header Opt In K (IR) OX 0pin Header 0pin Header (I ) Figure. K8- lock iagram * ircuit diagram and P layout are attached at the end of this manual. [KM00] 0/0 - -

2 [K8-] Operation sequence Name of jack ) Set up the power supply lines. olor of jack Typ Voltage V Orange V Used for Open / onnect efault Setting Should be always connected When default setting. Regulator T,T,T: V and V of K8, K, igital Logic V Red.V V of K8 V Red.V V of K8.V- Red.V K, igital Logic.V- Red.V K, igital Logic lack 0V Ground Table. Set up the power supply lines Should be always connected when V of K8 is not supplied from regulator T. In this case JP is set to V side. Should be always connected when V of K8 is not supplied from regulator T. In this case JP is set to V side. Should be always connected when K and igital Logic is not supplied from regulator T. In this case JP is set to.v- side. Should be always connected when K and igital Logic is not supplied from regulator T. In this case JP is set to.v- side. Should be always connected V Open Open Open Open ach supply line should be distributed from the power supply unit. [KM00] 0/0 - -

3 [K8-] ) Set up the jumper pin of power supply unit. ().Setup the V of K8. a).when using V jack. JP V RG V-SL b).when using Regulator. JP V RG V-SL ().Setup the V of K8. a).when using V jack. JP RG V V-SL b).when using Regulator. JP RG V V-SL ().Setup the.v-(k and igital Logic). a).when using.v- jack. JP.V- RG.V- SL b).when using Regulator. JP.V- RG.V- SL (). Setup the.v-(k and igital Logic). a).when using.v- jack. JP RG.V-.V- SL b).when using Regulator. JP RG.V-.V- SL [KM00] 0/0 - -

4 [K8-] ) Set up the evaluation mode, jumper pins. (See the followings.) (). Setting for Input port ()-. When using IR function of K (U,U,U and U) ()-. When using all clocks are fed through the 0pin port (). Setting for Output port ()-. When using IT function of K (U) ()-. When using all clocks are fed through the 0pin port(port). (). Other jumper pins setup. ) Power on. The K8 should be reset once bringing SW (PN) L upon power-up. [KM00] 0/0 - -

5 [K8-] Set up the evaluation mode, jumper pins. (). Setting for Input port ()-. When using IR function of K (U,U,U and U) When using J-(OX) and PORT-9(OPT), nothing should be connected to PORT-. ()--. Setup the RX. (a) Select to Optical jack (efault) IN PU T x S L N O PT (b) Select to N jack IN PU T x S L N O P T * "x" contains a number ( - ). ()--. Setup the IIK-, ILRK- and STI-. When using J-(OX) and PORT-9(OPT), nothing should be connected to PORT-. JP IMLK-SL XT SP IR IIKx ILRKx STIx * "x" contains a number ( - ). [KM00] 0/0 - -

6 [K8-] ()--. Setup the STI, STI, STI and STI. Select to input signal for STI, STI, STI and STI of K8(U). (a). When using Mode (INS pin = L ). (efault) JP JP JP STI-SL STI-SL STI-SL JP8 STI-SL synchronous synchronous synchronous synchronous (b).when using synchronous Mode (INS pin = H ). JP JP JP STI-SL STI-SL STI-SL JP8 STI-SL synchronous synchronous synchronous synchronous (c). onnect to. JP STI-SL JP STI-SL JP STI-SL JP8 STI-SL synchronous synchronous synchronous synchronous [KM00] 0/0 - -

7 [K8-] ()-. When using all clocks are fed through the 0pin port ()--. Setup the RX. When using PORT-, nothing should be connected to J- (OX) and PORT-9 (OPT). ()--. Setup the IIK-, ILRK- and STI-. When using PORT-, nothing should be connected to J- (OX) and PORT-9 (OPT). JP IMLK-SL XT SP IR IIKx ILRKx STIx * "x" contains a number ( - ). ()--. Setup the STI, STI, STI and STI. Select to input signal for STI, STI, STI and STI of K8(U). (a). When using Mode (INS pin = L ). (efault) JP JP JP STI-SL STI-SL STI-SL JP8 STI-SL synchronous synchronous synchronous synchronous (b).when using synchronous Mode (INS pin = H ). JP JP JP STI-SL STI-SL STI-SL JP8 STI-SL synchronous synchronous synchronous synchronous (c). onnect to. JP STI-SL JP STI-SL JP STI-SL JP8 STI-SL synchronous synchronous synchronous synchronous [KM00] 0/0 - -

8 [K8-] (). Setting for Output port ()-. When using IT function of K (U) ()--. Setup the TX. (a) Select to Optical jack (efault) JP O U T PU T S L (b) Select to N jack J P O U TP U T S L N OPT N OPT ()--. Setup the TXI. Select to input signal for XTI/OMLK pin of K8(U) and XTI pin of K(U). (a) When using X Tal(X). In this case, X Tal(X) is open. JP IT-OMKO SL K8 XT JP XT-LK JP SL OMLK JP0 MKO JP IT-OMLK SL IT SP XT (b) When using X Tal(X). In this case, X Tal(X) is open. JP IT-OMKO SL K8 XT JP XT-LK JP SL OMLK JP0 MKO JP IT-OMLK SL IT SP XT (c) When using J8(XT-LK). In this case, X Tal(X and X) is open. JP IT-OMKO SL K8 XT JP XT-LK JP SL OMLK JP0 MKO JP IT-OMLK SL IT SP XT [KM00] 0/0-8 -

9 [K8-] ()--. Setup the OIK, OLRK and STO. ()---.When using OIK, OLRK of K(U), and STO of K8(U). JP 8 O I K JP 9 O L R K JP 0 S T O JP IT-OIK SL JP IT-OLRK SL IT-Slave IT-Master IT-Slave IT-Master JP8 K8-OIK SL JP9 K8-OLRK SL K8-Slave K8-Master K8-Slave K8-Master ()---.When using OIK, OLRK and STO of K8(U). JP 8 O I K JP 9 O L R K JP 0 S T O JP IT-OIK SL JP IT-OLRK SL IT-Slave IT-Master IT-Slave IT-Master JP8 K8-OIK SL JP9 K8-OLRK SL K8-Slave K8-Master K8-Slave K8-Master [KM00] 0/0-9 -

10 [K8-] ()--. Selection of STO, STO, STO and STO. (a) Select to STO(b)Select to STO (c)select to STO (d)select to STO JP J P J P J P S T O -S L S TO -S L S TO -S L S TO -S L 8 STO STO 8 STO 8 STO 8 ()-. When using all clocks are fed through the 0pin port(port). ()--.Setup TX. s Optical connector:port0(opt) and N connector:j(ox) are not used, please don t connect anything. ()--. Setup the OIK, OLRK and STO. ()---. When using OIK and OLRK of 0pin port, and STO of K8(U). JP 8 O I K JP 9 O L R K JP 0 S T O JP IT-OIK SL JP IT-OLRK SL IT-Slave IT-Master IT-Slave IT-Master JP 8 K8-O IK S L JP9 K8-OLRK S L K8-Slav e K8-M aster K 8-Slave K 8-Master [KM00] 0/0-0 -

11 [K8-] ()---. When using OIK, OLRK and STO of K8(U). JP 8 O I K JP 9 O L R K JP 0 S T O JP IT-OIK SL JP IT-OLRK SL IT-Slave IT-Master IT-Slave IT-Master JP 8 K8-O IK S L JP9 K8-OLRK S L K8-Slav e K8-M aster K 8-Slave K 8-Master ()---. Selection of STO, STO, STO and STO. (a) Select to STO (b)select to STO (c)select to STO (d)select to STO JP J P J P J P S T O -S L S TO -S L S TO -S L S TO -S L STO 8 STO 8 STO 8 STO 8 [KM00] 0/0 - -

12 [K8-] (). Other jumper pins setup. [ JP9 (SL) ]:The selection of input signal to IMLK pin. IMLK :onnect to MLK signal of IR or 0 pin PORT. :onnect to (efault) [ JP0 (ILRK-SL) ]:The selection of input signal to ILRK pin. ILRK:onnect to LRK signal of IR or 0 pin PORT. (efault) :onnect to [ JP (ILRK-SL) ]:The selection of input signal to ILRK pin. ILRK:onnect to LRK signal of IR or 0 pin PORT. (efault) :onnect to [ JP (IIK-SL) ]:The selection of input signal to IIK pin. IIK:onnect to IK signal of IR or 0 pin PORT. (efault) :onnect to [ JP (ILRK-SL) ]:The selection of input signal to ILRK pin. ILRK:onnect to LRK signal of IR or 0 pin PORT. (efault) :onnect to [ JP (IIK-SL) ]:The selection of input signal to IIK pin. IIK :onnect to IK signal of IR or 0 pin PORT. (efault) :onnect to [ JP (SL) ]:The selection of input signal to INS pin. INS :onnect to INS signal (efault) :onnect to [ JP (UNLOK) ]:The selection of connection to UNLOK pin and L. OPN :Unconnection. SHORT :onnection. (efault) [ JP (TST0) ]:The selection of connection to TST0 pin and SW(TST0). OPN :Unconnection. SHORT :onnection. (efault) [ JP (TST) ]:The selection of connection to TST pin and SW(TST). OPN :Unconnection. SHORT :onnection. (efault) [ JP (TST) ]:The selection of connection to TST pin and SW(TST). OPN :Unconnection. SHORT :onnection. (efault) [ JP (SL) ]:The selection of input signal to S pin. S :onnect to S signal of 0 pin PORT(PORT). (efault) :onnect to [ JP (TST) ]:The selection of connection to TST pin and SW(TST). OPN :Unconnection. SHORT :onnection. (efault) [KM00] 0/0 - -

13 [K8-] [ JP (XT-LK) ]:The selection of J(XT-LK) connector. OPN :J(XT-LK) connector is use. SHORT :J(XT-LK) connector is not use. (efault) * If JP(XT-LK) is set to OPN, JP is set to XT. [KM00] 0/0 - -

14 [K8-] Setup the IP SW. (). Setup the K8(U). ()-. SW setting Upper-side is H and lower-side is L. SW No. Name ON ( H ) OFF ( L ) efault IIF L udio Interface Format Setting for Input PORT IIF H Refer to Table IIF0 L SP Serial ontrol Mode Parallel ontrol Mode L TST TST Pin L TST Fixed to L L SMSMI Semi-auto Mode Manual Mode L 8 0 hip ddress 0 bit= hip ddress 0 bit= 0 L Table. SW Setting Mode IIF IIF IIF0 IIK STI- Format pin pin pin Freq 0 L L L bit, LS justified FSI L L H 0bit, LS justified 0FSI L H L bit, MS justified 8FSI (efault) L H H /bit, I 8FSI or S ompatible FSI H L L bit, LS justified 8FSI H L H H H H Reserved Table. K8 udio Interface Format Setting for Input PORT [KM00] 0/0 - -

15 [K8-] ()-. SW setting Upper-side is H and lower-side is L. SW No. Name ON ( H ) OFF ( L ) efault OIT Output PORT udio Interface Format Setting H OIT0 Refer to Table H TM TM mode Stereo mode L M H lock Select or Mode Select pin for Output PORT M L Refer to Table M0 L OIF Output PORT udio Interface Format Setting H 8 OIF0 Refer to Table L Table. SW Setting Mode TM OIF OIF0 pin pin pin STO- Format 0 L L LS justified L H (Reserved) L H L MS justified (efault) H H I S ompatible L L L H (Reserved) H H L TM mode bit MS justified H H TM mode bit I S ompatible Table. Output PORT udio Interface Format Setting Mode TM pin H Master / Slave setting OIT pin OIT0 pin STO - OLRK OIK OIK Frequency MS LS justified, I justified S FSO 0 Slave L L bit (M-0 = L H 8bit FSO Input Input FSO HLL or H L 0bit 0FSO HHL ) H H bit 8FSO (efault) L L L bit Master L H 8bit (Not M-0 = Output Output FSO HLL / HHL ) H L 0bit H H bit 8 Slave 9 TM (M-0 = * * mode Input Input FSO 0 HLL or bit HHL ) Master (Not M-0 = HLL / HHL ) * * TM mode bit Table. Output PORT udio Interface Format Setting Output Output FSO [KM00] 0/0 - -

16 [K8-] Mode M M M0 Master / OMLK/XTI MKO pin pin pin Slave Input Output FSO 0 L L L Master FSO FSO 8k 08kHz L L H Master 8FSO 8FSO 8k 9kHz L H L Master FSO FSO 8k khz L H H Master 8FSO 8FSO 8k 8kHz In xternal lock H L L Slave Mode, OMLK.0MHz~.8MHz. Input lock In X tal Mode, X tal 8k khz oscillation frequency. H L H Master 8FSO 8FSO 8k khz H H L Slave IMLK Not used. (note) H H H (ypass) Input lock 8k khz Table. Output PORT Master/Slave/ypass Mode ontrol Setting (efault) ()-. SW setting Upper-side is H and lower-side is L. SW No. Name ON ( H ) OFF ( L ) efault INS synchronous mode mode L ITHR ither ON ither OFF L SMT Soft Mute Timer Setting L SMT0 Refer to Table 9 L M0 e-emphasis Filter Setting H M Refer to Table 0 L PM hannel Mode Setting H 8 PM Refer to Table L Table 8. SW Setting SMTpin SMT0 pin Period FSO=8kHz FSO=9kHz FSO=9kHz L L 0/fso.ms 0.ms.ms (efault) L H 08/fso.ms.ms 0.ms H L 09/fso 8.ms.ms.ms H H 89/fso 0.ms 8.ms.ms Table 9. Soft Mute ycle Setting Mpin M0 pin Mode(STI-) L L.kHz L H OFF (efault) H L 8kHz H H khz Table 0. e-emphasis Filter Setting [KM00] 0/0 - -

17 [K8-] PM pin PM pin PN pin Mode X tal Oscillator Pull down to L L L -channel Power-down VSS- mode L L H Input Pull down to L H L -channel VSS- Power-down mode L H H Input H L L H L H 8-channel mode Power-down Normal operation XTI pin XTO pin MKO pin Pull down to VSS- Input Hi-z Hi-z Hi-z Output Hi-z L Normal operation H H L Not H H H available Table. hannel Mode Setting (efault) ()-. SW setting Upper-side is H and lower-side is L. SW No. Name ON ( H ) OFF ( L ) efault TST TST Pin L TST0 Fixed to L L Table. SW Setting [KM00] 0/0 - -

18 [K8-] (). Setup the K (U,U,U,U,U) ()-. SW(U), SW(U), SW8(U), SW9(U) setting. Upper-side is H and lower-side is L. SW No. Name ON ( H ) OFF ( L ) efault IR-OKS Master lock Frequency Setting H IR-OKS0 Refer to Table L IR-IF0 bit, I S ompatible bit, Left justified L Table. SW Setting SW No. Name ON ( H ) OFF ( L ) efault IR-OKS Master lock Frequency Setting H IR-OKS0 Refer to Table L IR-IF0 bit, I S ompatible bit, Left justified L Table. SW Setting SW8 No. Name ON ( H ) OFF ( L ) efault IR-OKS Master lock Frequency Setting H IR-OKS0 Refer to Table L IR-IF0 bit, I S ompatible bit, Left justified L Table. SW8 Setting SW9 No. Name ON ( H ) OFF ( L ) efault IR-OKS Master lock Frequency Setting H IR-OKS0 Refer to Table L IR-IF0 bit, I S ompatible bit, Left justified L Table. SW9 Setting Mode OKS pin OKS0 pin MKO fs (max) 0 L L fs 9 khz L H fs 9 khz H L fs 8 khz (efault) H H 8fs 9 khz Table. Master lock Frequency Setting [KM00] 0/0-8 -

19 [K8-] ()-. SW(U) setting. Upper-side is H and lower-side is L. SW No. Name ON ( H ) OFF ( L ) efault IT-OKS Master lock Frequency Setting H IT-OKS0 Refer to Table 8 L IT-IF H udio Interface Format Setting IT-IF L Refer to Table 9 IT-IF0 L Table. SW Setting Mode OKS pin OKS0 pin MKO fs (max) 0 L L fs 9 khz L H fs 9 khz H L fs 8 khz (efault) H H 8fs 9 khz Table 8. Master lock Frequency Setting Mode IF IF IF0 LRK IK UX Format pin pin pin I/O I/O 0 L L L bit, Left justified H/L O fs O L L H bit, Left justified H/L O fs O L H L bit, Left justified H/L O fs O L H H bit, Left justified H/L O fs O H L L bit, Left justified H/L O fs O (efault) H L H bit, I S ompatible L/H O fs O H H L bit, Left justified H/L I -8fs I H H H bit, I S ompatible L/H I -8fs I Table 9. udio Interface format Setting [KM00] 0/0-9 -

20 [K8-] The function of the toggle SW Upper-side is H and lower-side is L. [SW] (K8-SMUT) :Soft mute of K8. When using Soft mute function, SW is H. [SW] (K8-PN) [SW0] (IR-PN) [SW] (IR-PN) [SW] (IR-PN) [SW] (IR-PN) [SW] (IT-PN) :Resets the K8. Keep H during normal operation. The K8 should be resets once bringing L upon power-up. :Resets the K (U). Keep H during normal operation. The K (U) should be resets once bringing L upon power-up. Keep L when K (U) is not used. :Resets the K (U). Keep H during normal operation. The K (U) should be resets once bringing L upon power-up. Keep L when K (U) is not used. :Resets the K (U). Keep H during normal operation. The K (U) should be resets once bringing L upon power-up. Keep L when K (U) is not used. : Resets the K (U). Keep H during normal operation. The K (U) should be resets once bringing L upon power-up. Keep L when K (U) is not used. : Resets the K (U). Keep H during normal operation. The K (U) should be resets once bringing L upon power-up. Keep L when K (U) is not used. Indication for L [L] (UNLOK) :Monitor UNLOK pin of the K8 (U). L turns on when PN pin = L. [KM00] 0/0-0 -

21 [K8-] Serial ontrol The KUSIF- is connected to a P with a US cable and to an evaluation board with the 0pin flat cable installed in the KUSIF- (Note, Note ). Note. Only one KUSIF- can be connected to a P. It cannot operate when connecting more than two KUSIF- s. Note. The red line of the 0pin flat cable should be connected with the pin of the 0pin Header of an evaluation board. 0pin Flat able valuation oard KXXXX-YY P US able KUSIF- evice KXXXX US onnector Set Red line to No. pin side. Figure. onnection via the KUSIF- 0pin onnector valuation oard P KUSIF- Figure. KUSIF- [KM00] 0/0 - -

22 [K8-] valuation oard and ontrol Soft Settings ontrol Soft Manual. Set an evaluation board properly.. onnect a US control box (KUSIF-) and an evaluation board. Pay attention about direction of the 0pin header when connecting to an KUSIF-.. onnect a P (IM-T compatible) and the US control box (KUSIF-). The US control box is recognized as HI (Human Interface evice) on the P. It is not necessary to install a new driver.. Start up the control program. When the screen does not display KUSIF- at bottom left, reconnect the P and the US control box, and push the [Port Reset] button.. Proceed evaluation by following the process below. [Support OS] Windows XP / Vista / (bit) (XP compatible mode is recommended for Vista / ) bit OS s are not supported. [KM00] 0/0 - -

23 [K8-] Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. uttons which are frequently used such as register initializing button Write efault, are located outside of the switching tab window. Refer to the ialog oxes for details of each dialog box setting.. [Port Reset] : For when connecting to US I/F board (KUSIF-) lick this button after the control soft starts up when connecting US I/F board (KUSIF-).. [Write efault] : Register Initializing When the device is reset by a hardware reset, use this button to initialize the registers.. [ll Write] : xecuting write commands for all registers displayed.. [ll Read] : xecuting read commands for all registers displayed.. [Save] : Saving current register settings to a file.. [Load] : xecuting data write from a saved file.. [ll Req Write] : ll Req Write dialog box is popped up. 8. [ata R/W] : ata R/W dialog box is popped up. 9. [Sequence] : Sequence dialog box is popped up. 0. [Sequence(File)] : Sequence(File) dialog box is popped up.. [Read] : Reading current register settings and display on to the Register area (on the right of the main window). This is different from [ll Read] button, it does not reflect to a register map, only displaying hexadecimal. Figure. Window of [ FUNTION] [KM00] 0/0 - -

24 [K8-] ialog oxes [ll Req Write] lick [ll Reg Write] button in the main window to open register setting files. Register setting files saved by [SV] button can be applied. Figure. Window of [ ll Reg Write] [Open (left)] [Write] [Write ll] [Help] [Save] [Open (right)] [lose] : Selecting a register setting file (*.akr). : xecuting register writing. : xecuting all register writings. Writings are executed in descending order. : Help window is popped up. : Saving the register setting file assignment. The file name is *.mar. : Opening a saved register setting file assignment *. mar. : losing the dialog box and finish the process. *Operating Suggestions () Those files saved by [Save] button and opened by [Open] button on the right of the dialog *.mar should be stored in the same folder. () When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings. [KM00] 0/0 - -

25 [K8-] [ata R/W] lick the [ata R/W] button in the main window for data read/write dialog box. ata write is available to specified address. Figure. Window of [ ata R/W ] ddress ox : Input data address in hexadecimal numbers for data writing. ata ox : Input data in hexadecimal numbers. Mask ox : Input mask data in hexadecimal numbers. This is N processed input data. [Write] [lose] : Writing to the address specified by ddress box. : losing the dialog box and finish the process. ata writing can be cancelled by this button instead of [Write] button. *The register map will be updated after executing [Write] or [Read] commands. [KM00] 0/0 - -

26 [K8-] [Sequence] lick [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure. Window of [ Sequence ] Sequence Setting Set register sequence by following process bellow. ()Select a command Use [Select] pull-down box to choose commands. orresponding boxes will be valid. < Select Pull-down menu > No_use : Not using this address Register : Register writing Reg(Mask) : Register writing (Masked) Interval : Taking an interval Stop : Pausing the sequence nd : Finishing the sequence ()Input sequence [ddress] : ata address [ata] : Writing data [Mask] : Mask [ata] box data is Ned with [Mask] box data. This is the actual writing data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [ata] box is written. When Mask =0x0F, lower bit data which is set in the [ata] box is written. Upper bit is hold to current setting. [ Interval ] : Interval time [KM00] 0/0 - -

27 [K8-] Valid boxes for each process command are shown bellow. No_use : None Register : [ddress], [ata], [Interval] Reg(Mask) : [ddress], [ata], [Mask], [Interval] Interval : [Interval] Stop : None nd : None ontrol uttons The function of ontrol utton is shown bellow. [Start] : xecuting the sequence [Help] : Opening a help window [Save] : Saving sequence settings as a file. The file name is *.aks. [Open] : Opening a sequence setting file *.aks. [lose] : losing the dialog box and finish the process. Stop of the sequence When Stop is selected in the sequence, processing is paused and it starts again when [Start] button is clicked. Restarting step number is shown in the Start Step box. When finishing the process until the end of sequence, Start Step will return to. The sequence can be started from any step by writing the step number to the Start Step box. Write to the Start Step box and click [Start] button, when restarting the process from the beginning. [KM00] 0/0 - -

28 [K8-] [Sequence(File)] lick [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the Sequence setting dialog can be applied in this dialog. Figure 8. Window of [ Sequence(File) ] [Open (left)] : Opening a sequence setting file (*.aks). [Start] : xecuting the sequence setting. [Start ll] : xecuting all sequence settings. Sequences are executed in descending order. [Help] : Pop up the help window. [Save] : Saving sequence setting file assignment. The file name is *.mas. [Open(right)] : Opening a saved sequence setting file assignment *. mas. [lose] : losing the dialog box and finish the process. *Operating Suggestions () Those files saved by [Save] button and opened by [Open] button on the right of the dialog *.mas should be stored in the same folder. () When Stop is selected in the sequence the process will be paused and a pop-up message will appear. lick OK to continue the process. Figure 9. Window of [ Sequence Pause ] [KM00] 0/0-8 -

29 [K8-]. [RG]: Register Map This tab is for a register writing and reading. ach bit on the register map is a push-button switch. utton own indicates H or and the bit name is in red (when read only it is in deep red). utton Up indicates L or 0 and the bit name is in blue (when read only it is in gray) Grayout registers are Read Only registers. They can not be controlled. The registers which is not defined in the datasheet are indicated as ---. Figure 0. Window of [ RG] [KM00] 0/0-9 -

30 [K8-] [Write]: ata Writing ialog It is for when changing two or more bits on the same address at the same time. lick [Write] button located on the right of the each corresponded address for a pop-up dialog box. When checking the checkbox, the register will be H or, when not checking the register will be L or 0. lick [OK] to write setting value to the registers, or click [ancel] to cancel this setting. Figure. Window of [ Register Set ] [Read]: ata Read lick [Read] button located on the right of the each corresponded address to execute register reading. fter register reading, the display will be updated regarding to the register status. utton own indicates H or and the bit name is in red (when read only it is in deep red). utton Up indicates L or 0 and the bit name is in blue (when read only it is in gray) Please be aware that button statuses will be changed by Read command. [KM00] 0/0-0 -

31 [K8-].[Tool]: Testing Tools This tab screen is for evaluation testing tool. lick buttons for each testing tool. Figure. Window of [ Tool] [KM00] 0/0 - -

32 [K8-] [Repeat Test]: Repeat Test ialog lick [Repeat Test] button to open repeat test setting dialog box. Figure. Window of [ Repeat Test] [Loop Setting]: Loop Setting ialog lick [Loop Setting] button to open loop setting dialog box. Figure. Window of [ Loop] [KM00] 0/0 - -

33 [K8-] Measurement Results [Measurement condition] Measurement unit Power Supply and width INS pin OMLK/XTI Input Output PORT Temperature : udio Precision, System Two ascade : V=V=.V : 0Hz FSO/ : L ( Mode) : Use X Tal (X) : Slave Mode : Room [Measurement Result] SR haracteristics STO STO STO STO Lch Rch Lch Rch Lch Rch Lch Rch THN (Input = khz, 0dFS) FSO/FSI =.khz/8khz d FSO/FSI = 8kHz/.kHz d FSO/FSI = 8kHz/9kHz d FSO/FSI = 9kHz/8kHz d Worst ase (FSO/FSI = khz/.khz) d ynamic Range (Input = khz, 0dFS) FSO/FSI =.khz/8khz d FSO/FSI = 8kHz/.kHz d FSO/FSI = 8kHz/9kHz d FSO/FSI = 9kHz/8kHz d Worst ase(fso/fsi = 8kHz/kHz) d ynamic Range (Input = khz, 0dFS, -weighted) FSO/FSI =.khz/8khz d Unit [KM00] 0/0 - -

34 [K8-] [Plots] KM d F S K8 FFT V=V=.V, FSO/FSI=.kHz/8kHz, khz/0dfs Input k k k 0k 0k Hz Figure. FFT Plot (Input = 0dFS) KM d F S K8 FFT V=V=.V, FSO/FSI=.kHz/8kHz, khz/-0dfs Input k k k 0k 0k Hz Figure. FFT Plot (Input = -0dFS) [KM00] 0/0 - -

35 [K8-] KM -0 K8 THN vs. Input Level V=V=.V, FSO/FSI=.kHz/8kHz, fin=khz d F S dfs Figure. THN vs. Input Level KM -90 K8 THN vs. Input Frequency V=V=.V, FSO/FSI=.kHz/8kHz, 0dFS Input d F S k k k 0k 0k Hz Figure 8. THN vs. Input Frequency (Input = 0dFS) [KM00] 0/0 - -

36 [K8-] KM -90 K8 THN vs. Input Frequency V=V=.V, FSO/FSI=.kHz/8kHz, -0dFS Input d F S k k k 0k 0k Hz Figure 9. THN vs. Input Frequency (Input = -0dFS) KM 0-0 K8 Linearity V=V=.V, FSO/FSI=.kHz/8kHz, fin=khz d F S dfs Figure 0. Linearity [KM00] 0/0 - -

37 [K8-] KM 0. K8 Frequency Response (Yellow:FSI=.kHz, lue:fsi=8khz, Red:FSI=9kHz, Green:FSI=9kHz) V=V=.V, FSO=.kHz, 0dFS Input FSI=.kHz d F S FSI=9kHz FSI=9kHz FSI=8kHz -8 k k k k k k k 8k 9k 0k k k k k k k k 8k 9k 0k k Hz k Figure. Frequency Response (FSO=.kHz) KM K8 Frequency Response (lue:fsi=8khz, Red:FSI=9kHz, Green:FSI=9kHz) V=V=.V, FSO=8kHz, 0dFS Input d F S FSI=9kHz FSI=9kHz FSI=8kHz -8 k k k 8k 0k k k k 8k 0k k Hz k Figure. Frequency Response (FSO=8kHz) [KM00] 0/0 - -

38 [K8-] Revision History ate Manual oard Reason Page ontents (YY/MM/) Revision Revision 0/08/ KM000 0 First edition - 0/09/0 KM00 0 ddition - Measurement Results and Plots were added. /0/08 KM00 0 hange Serial ontrol was changed. - ontrol Soft Manual was changed. IMPORTNT NOTI These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of sahi Kasei Microdevices orporation (KM) or authorized distributors as to current status of the products. escriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. KM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. KM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ny export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. KM products are neither intended nor authorized for use as critical components Note) in any safety, life support, or other hazard related device or system Note), and KM assumes no responsibility for such use, except for the use approved with the express written consent by Representative irector of KM. s used here: Note) critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note) hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of KM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold KM harmless from any and all claims arising from the use of said product in the absence of such notification. [KM00] 0/0-8 -

39 ILRK TST V SP S SL TST SMSMI TST V 0 TST0 JP0 MKO K8-MKO ILRK JP0 ILRK-SL JP TST R short S JP SL JP TST JP TST R9 short JP TST0 N pin_ TP ILRK R TP TST TP VSS TP9 V8 TP V open R open u 00 0u 0.u TP VSS TP V 0u K8-V TP TST0 0.u IIK IMLK JP9 IMLK N R R TP IIK TP IMLK IIK IMLK ILRK TST VSS V8 V 0 SP 9 S 8 SL XTO 8 XTI/OMLK TP8 OMLK K8-OMLK ILRK IIK TP ILRK TP IIK ILRK IIK OLRK OIK TP0 OLRK TP9 OIK JP9 K8-OLRK SL K8-Slave K8-Master JP8 K8-OIK SL K8-Slave K8-Master K8-OLRK-S K8-OLRK-M K8-OIK-S K8-OIK-M K8-V 0.u V VSS V VSS 8 0u K8-V STI STI STI STI JP8 synchronous JP synchronous STI-SL JP synchronous STI-SL JP synchronous STI-SL R TP STI TP STI TP STI TP0 STI STI STI STI STI U K8 STO STO STO STO 0 9 TP STO TP STO TP STO TP STO STO STO STO STO K8-STO IIF0 IIF0 OIF0 8 OIF0 IIF IIF OIF OIF IIF IIF M0 M0 ILRK IIK ILRK JP ILRK JP IIK ILRK-SL JP ILRK IIK-SL ILRK-SL pin_ TP8 ILRK TP9 IIK TP ILRK ILRK IIK ILRK IIK INS UNLOK M M TM V VSS SMUT ITHR 8 PN 9 SMT0 SMT TST M0 M SMSMI PM OIT0 0 OIT PM M M TM TST VSS V 0 0 TST0 MKO 9 JP OMLK SL R R SL 0u 0 0.u R R STI-SL R8 R9 TP IIK TP0 UNLOK TP8 SMUT TP PN K8-V p X.9MHz 0p pin_ 8 R0 0 9 JP STO-SL 8 R N 0.u 0u R N pin_ JP IIK-SL JP SL JP UNLOK IIK INS IIK INS UNLOK SMUT ITHR K8-PN SMT0 SMT M0 M PM OIT0 OIT PM Title K8- K8 0 Size ocument Number Rev Tuesday, ugust, 00 ate: Sheet of 0

40 PORT L u.v- RX V OUT TORX 0.u 0u 0u.V- R0 0.u J N-R-P OX R 0 0.u JP OPT N INPUT SL 8 RX N RX TST RX N RX0 VSS VOM 0 0.u R 9 R 8k V 8 INT IPS0 INT0 N OKS0 IR-OKS0 IR-IF0 IF0 OKS IR-OKS TST M IF U M0 N K PN IR-PN IF XTI 0 8 IPS XTO 9 9 P/SN UX 8 0 XTL0 XTL MKO IK JP8 IIK R R9 R R PORT -0P-.S IMLK IIK ILRK STI SP VIN TV VSS TX0 TX OUT OUT UOUT VOUT V VSS MKO LRK STO JP0 STI R8 0k R 0k R 0k R 0k 0.u u JP9 ILRK 0u 0u.V- IR-MKO JP IR SP XT J N-R-P XT-LK IR-IK IMLK-SL JP R XT-LK IR-LRK IR-STI Title K8- IR 0 Size ocument Number Rev Tuesday, ugust, 00 ate: Sheet of 0

41 PORT L u.v- RX V OUT TORX 0.u 8 0u 0u.V- R 0.u J N-R-P OX R 0.u JP OPT N INPUT SL 8 RX N RX TST RX N RX0 VSS VOM 0 0.u R 9 R0 8k V 8 INT IPS0 INT0 N OKS0 IR-OKS0 IR-IF0 IF0 OKS IR-OKS TST M IF U M0 N K PN IR-PN IF XTI 0 8 IPS XTO 9 9 P/SN UX 8 0 XTL0 XTL MKO IK JP IIK R9 R R8 PORT -0P-.S IIK ILRK STI SP VIN TV VSS TX0 TX OUT OUT UOUT VOUT V VSS MKO LRK STO JP STI R 0k R 0k R 0k 8 0.u u JP ILRK 0 0u 9 0u.V- IR-IK IR-LRK IR-STI Title K8- IR 0 Size ocument Number Rev Tuesday, ugust, 00 ate: Sheet of 0

42 PORT8 L u.v- RX V OUT TORX 9 0.u 0u 0u.V- R 0.u J N-R-P OX R 0.u JP OPT N INPUT SL 8 RX N RX TST RX N RX0 VSS VOM u R 9 R 8k V 8 INT IPS0 INT0 N OKS0 IR-OKS0 IR-IF0 IF0 OKS IR-OKS TST M IF U M0 N K PN IR-PN IF XTI 0 8 IPS XTO 9 9 P/SN UX 8 0 XTL0 XTL MKO IK JP IIK R R R PORT -0P-.S IIK ILRK STI SP VIN TV VSS TX0 TX OUT OUT UOUT VOUT V VSS MKO LRK STO JP9 STI R0 0k R 0k R0 0k 0.u u JP8 ILRK 8 0u 0u.V- IR-IK IR-LRK IR-STI Title K8- IR 0 Size ocument Number Rev Tuesday, ugust, 00 ate: Sheet of 0

43 PORT9 L u.v- RX V OUT TORX 0.u 0u 9 0u.V- R 8 0.u J N-R-P OX R 0.u JP0 OPT N INPUT SL 8 RX N RX TST RX N RX0 VSS VOM 0 0.u R 9 R 8k V 8 INT IPS0 INT0 N OKS0 IR-OKS0 IR-IF0 IF0 OKS IR-OKS TST M IF U M0 N K PN IR-PN IF XTI 0 8 IPS XTO P/SN XTL0 XTL UX 8 MKO IK JP IIK R80 R8 R9 PORT -0P-.S IIK ILRK STI SP VIN TV VSS TX0 TX OUT OUT UOUT VOUT V VSS MKO LRK STO JP STI R 0k R 0k R 0k 0.u u JP ILRK 0u 0u.V- IR-IK IR-LRK IR-STI Title K8- IR 0 Size ocument Number Rev Tuesday, ugust, 00 ate: Sheet of 0

44 0 0u.V- 0.u 0.u RX 8 N RX TST RX N RX0 VSS VOM 0 R 9 V 8 INT IPS0 INT0 N OKS0 IT-OKS0 IT-IF0 IF0 OKS IT-OKS TST M IT-IF IT-IF 8 IF N IF IPS U K M0 PN XTI 0 XTO 9 0p X.9MHz 0p JP K8 XT IT-OMKO SL.V- IT-PN IT-MKO 9 P/SN UX 8 JP0 STO 0 XTL0 MKO XTL IK JP8 OIK VIN TV VSS TX0 TX OUT OUT UOUT VOUT V VSS MKO LRK STO 9 0.u u JP9.V- 8 0u 0u OLRK R8 R9 R90 R9 PORT -0P-.S OMLK OIK OLRK STO SP R9 0k R88 0k R8 0k R89 0k TX(OPT) PORT0 TOTX IN V 0.u.V- OPT J T N-R-P -0F TX(OX) R8 0 0.u N JP OUTPUT SL IT-OMLK JP IT SP XT J8 N-R-P XT-LK : R8 0 IT-OIK-S IT-OIK-M IT-OMLK SL JP IT-Slave IT-Master IT-OIK SL JP R9 XT-LK IT-OLRK-S IT-OLRK-M JP IT-Slave IT-Master IT-OLRK SL IT-STO Title K8- IT 0 Size ocument Number Rev Tuesday, ugust, 00 ate: Sheet of 0

45 IR-MKO 9 8 Y8 IMLK K8-MKO 9 8 Y8 IT-MKO 8 Y IT-OMLK 8 Y K8-OMLK IR-IK Y IIK Y IR-LRK IR-STI U LV Y Y ILRK STI K8-OIK-M IT-OIK-M U LV Y Y IT-OIK-S K8-OIK-S IR-STI Y STI K8-OLRK-M Y IT-OLRK-S IR-LRK Y ILRK IT-OLRK-M Y K8-OLRK-S IR-IK Y 8 IIK K8-STO Y 8 IT-STO 9 G G 0 V 0 0.u.V- 9 G G 0 V 0 0.u.V- IR-IK 9 8 Y8 IIK 8 Y IR-LRK Y ILRK IR-STI IR-STI U LV Y Y STI STI IR-LRK Y ILRK Y IR-IK Y 8 IIK 9 G G 0 0.u V 0.V- Title K8- Size ocument Number Rev uffer 0 ate: Tuesday, ugust, 00 Sheet of 0

46 .V- L SW T-M K8-SMUT.V- K K HSU9 H HSU9 R 0k 0.u R 0k U Y Y Y V Y Y 0 9 Y 8 H 0.u SMUT.V- K8-PN.V- PORT R R -0P-.S 0k 0k SL R 0 S R 0 S(K) R 0 up-i/f.v- 0.u.V- U0 9 V R8 R9 LS0 0k 0k Y Y Y Y 8 Y 0 Y R 00 R 00 SL S L SW T-M K8-PN H 0.u UNLOK L SML-0LT.V- UNLOK R k.v-.v- K HSU9 R8 0k IR-PN K HSU9 R0 0k IR-PN L SW0 T-M IR-PN.V- K H HSU9 0.u R 0k U8 Y Y Y V Y Y 0 9 Y 8 H 0.u.V- IR-PN L SW T-M IR-PN.V- K H HSU9 8 0.u R9 0k U9 Y Y Y V Y Y 0 9 Y 8 H 9 0.u.V- IT-PN IR-PN L SW T-M IR-PN H 0.u L SW T-M IR-PN H 0.u.V- K HSU9 R 0k L SW T-M IT-PN H 0 0.u Title K8- Size ocument Number Rev LOGI 0 ate: Tuesday, ugust, 00 Sheet 8 of 0

47 SP IIF0 IIF IIF.V- IR-OKS IR-OKS0 IR-IF0 TM M OIT OIT0.V- OIF OIF0 M M0 SMT0 ITHR SMT INS PM.V- M PM M0.V- 0 SMSMI TST TST.V- IR-OKS IR-OKS0 IR-IF0.V- IR-OKS IR-OKS0 IR-IF0.V- IR-OKS IR-OKS0 IR-IF0.V- IT-OKS IT-OKS0 IT-IF IT-IF IT-IF0.V- TST TST0 Title Size ocument Number Rev ate: Sheet of SW 0 K8-9 0 Tuesday, ugust, 00 Title Size ocument Number Rev ate: Sheet of SW 0 K8-9 0 Tuesday, ugust, 00 Title Size ocument Number Rev ate: Sheet of SW 0 K8-9 0 Tuesday, ugust, 00 IIF IR-IF0 IR-OKS0 IR-OKS OIT k TM OIF M M OIF0 M0 OIT0 INS PM K PM SMT ITHR M0 SMT0 M K 0 IIF0 SMSMI TST SP TST IIF IR-IF0 IR-OKS0 IR-OKS IR-IF0 IR-OKS0 IR-OKS IR-IF0 IR-OKS0 IR-OKS IT-IF0 IT-OKS0 IT-OKS IT-IF IT-IF TST0 TST RP9 k RP9 k RP RP 9 8 SW9-0 SW9-0 SW -0 SW -0 RP RP 9 8 RP k RP k SW -0 SW SW -80 SW RP k RP k RP k RP k SW -80 SW SW -0 SW -0 RP8 k RP8 k SW8-0 SW8-0 RP k RP k SW -0 SW -0 RP RP 9 8 SW -80 SW

48 V V T LT-. V JP V-SL V 8 u 9 0.u IN OUT 0.u 0 u RG V V JP V-SL V RG TP TP TP TP.V- T LT-..V- JP.V- SL.V- IN OUT RG u 0.u 0.u u.v- T LT-..V- JP.V- SL.V- IN OUT RG u 0.u 0.u u Title K8- Size ocument Number Rev Power Supply 0 ate: Tuesday, ugust, 00 Sheet 0 of 0

49 K8- Rev.0 valuation oard

50

51

52