Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs

Transcription

1 VR core and power 00v.0 Power supply, reset circuit, reference voltage and power indicator. Port 00v.0 nalogue and digital inputs with options for FET outputs Port 00v.0 igital inputs with optional FET outputs ( P0 to P ) and programming connector. PI and select lines. Port 00v.0 FET outputs with the option of digital inputs. Port 00v.0 erial communications. inputs. FET outputs. JE MIROPROE PTY LT ONI RO, ONI, VI, Ph (0) Fax (0) jed@jedmicro.com.au Title page PROJET NUMER 00v.ch VERION TE -Mar-00 HEET OF

2 W REET* < REET RUN > REET* R K REET* U U TMEG_IP REET* J POWER IN. IN_ Ja power L 0 The regulator is fitted with a heatsink # -- IN_ U LM0T-.0 0.UF IN OUT LM0T H HETINK TO0 HIZONTL /0 L L IN-00UH IN-00UH 0 /0 0.UF /0 LE POWER 0.UF PF PF _F _F L REF VOLT hort L if optional volt ref is NOT used. X X. X REF 0 0 XTL Tmega XTL Power & control REF U MXP VIN TEMP MX I I VOUT.0V OMP TRIM 0.0UF 0./0 R M W VR VM^ djust to.0 volts using VR R M OPTIONL HIGH REOLUTION REFERENE VOLTGE JE MIROPROE PTY LT ONI RO, ONI, VI, Ph (0) Fax (0) jed@jedmicro.com.au VR & POWER PROJET NUMER 00v.0 VERION TE -Mar-00 HEET OF

3 0K P MT0 G U TMEG_IP P0(0) P() P() 0 P0 P P L PT_0 L PT_ L PT_ resistor patch options PT_0 PT_ PT_ PT_ OUTIE WL J PT 0/. R R R PU P Tmega Port P() P() P() P() P() P P P P P L PT_ L PT_ L PT_ L0 PT_ L PT_ PT_ PT_ PT_ PT_ L 0 OUTIE WL J PT /. _P E R J PT 0/ Optional connectors to F R R P0/ INPUT 0/ LMPING J PT / nalogue and digital inputs. = FET output ( resistor P ensures that FET is off during reset ) = n active low digital input ( eg switch ) or for resistive transducer to ground. = n active high digital input or analogue termination resistor to ground (eg 00R for to 0m loop) = high impedance analogue input 0 to volts E = input filter F = voltage divider analogue input. Voltage to VR = R x Vinput/(R+R) Notes R is the input protection series protection typically k or 0k PU is a pull up resistor P is a pull down resistor REF TL REF TL 0 U TL 0 U TL P0 P INT P To.0 drawing JE MIROPROE PTY LT ONI RO, ONI, VI, Ph (0) Fax (0) jed@jedmicro.com.au PT PROJET NUMER 00v.0 VERION TE -Mar-00 HEET OF

4 From.0 drawing clamping devices Install RP only if P0/P used as outputs. RP XK^ INT If P0 to P are used as inputs install RP (in socket) & RP. RP can be installed as shown for pull down mode or reversed for pull up If used as outputs fit F, F, F & F & RP but do not fit RP & RP. Optional FETs F MT0VL F MT0VL F MT0VL F MT0VL RPa XK* FET FET FET FET RP way socket. RP can be installed J PT 0/ U TMEG_IP Tmega Port P0(XK/T0) P(T) P(INT/IN0) P(O0/IN) P(*) P(MOI) P(MIO) P0 P P P P P J 0 Prog Pins,, & 0 missing REET* To reset circuit on sheet 00v.0 Reset circuit to U RP XK RP XK RPa XK* RP way socket. J PT J PT / RP can be installed P(K) P J connector. Pins to match the standard tmel VR-IP/TK00 pin programming cable pinout. Z Z_V Z Z_V Z Z_V Z Z_V J PT / Use all of J for upstairs PI expandable I/O. ( pins to, P0 to P can be used as chip selects ) JE MIROPROE PTY LT ONI RO, ONI, VI, Ph (0) Fax (0) jed@jedmicro.com.au PT PROJET NUMER 00v.0 VERION TE -Mar-00 HEET OF

5 U TMEG_IP P0(L) P() P(TK) X XTL-KHZ R K Z Z_V R K L Z +V Z_V att+v -V U 0 X X TT QW,OUT 0 RT L Vertical TT lithium R/V battery L Q.WVE.INT INT RPa XK* RP J PT / J int I 0 L OLER_LINK L OLER_LINK us This connector is used for upstairs boards that require I interface (non buffered). uffered U I options uffered mode ( standard build ) L and L not joined. U installed. R & R0 (0R) installed. R & R are 0R Non buffered mode ( special build ) L and L are joined. U not installed. R & R0 not installed. R & R are 00R R 0R R0 0R R 0R R 0R L 0 L 0 L 0 /0 Note J connector can be either right angle or upright. 0 J OX0 Tmega Port P(TM) P(TO) RP X K F 0 F 0 F 0 FET FET FET. L 0 a P(TI) P(TO) P(TO) Use resistor pack to provide pull down for FETs Use Zeners in the resistor pack holes to provide spike protection for inputs. holes Z0ZZ Z:V Z:V Z Z:V Z:V Z Z:V Z:V These components only required if the output option is used RP XK Z F 0 F 0 These components only required if the output option is used Optional F0 0 RP XK RPa XK* RP XK RP FET FET FET0 J PT / RP can be installed J PT /. J PT / For outputs install :- F, F, F & RP For inputs install :- RP, RP & x v zeners in place of RP RP can be installed as shown for pull down or reversed for pull up. For outputs install :- F, F, F0 & RP For inputs install :- RP, RP & x v zeners in place of RP RP can be installed as shown for pull down or reversed for pull up. INT INT0 JE MIROPROE PTY LT ONI RO, ONI, VI, Ph (0) Fax (0) jed@jedmicro.com.au PT PROJET NUMER 00v.0 VERION TE -Mar-00 HEET OF

6 autionary note: ============= This schmatic shows the wiring as on the 00v P. The 00v0 Ps have the pins and of U ( H ) crossed over. This will not allow the R to work unless wire links are installed to correct this error. This does not affect the operation of the R in any way. UE TMEG_IP Tmega Port P0(RX) P(TX) P(INT0) P(INT) P(O) P(O) P(IP) 0 U H. / G RX TX H L L L P P P R connector set up U MX0E 0.UF RT_ TE E TE E 0.UF TX_ RX_ T R 0 Rd/Wr lines handshake no handshake T + G V R T_ 0.UF 0.UF 0.UF L L Use resistor pack to provide pull down for FETs Use Zeners in the resistor pack holes to provide spike protection for inputs. holes J F. J RX TX T RT ERIL U/ Z Z_V Z Z Z Z:V Z Z_V Z:V Z:V Z Z_V RP XK RP0 XK P P P RP can be installed RP XK RP XK F MT0VL F MT0VL F MT0VL INT INT0 T_ L L RP FET FET L FET L RPa XK* J0 PT J0 PT, &. J PT J PT, &. P(O) R K - L jumper options Jumper pins & gives control of or to P ( low = R high = R ) The next options release P for use as either an input or output. Jumper pins & selects R only. Leave open selects R only. If only R is required link L0 & L and omit U and U0. L / select P U H. transmit line Y H L0 UE H. Y H receive line 0 U L U H. Y H H. Y H R K J TTL/Radio erial comms U0 MX0EP Ja is an internal connection for a TTL level internal serial communication. an only be used if the R transceiver (U0) is not installed. Pin # Ground Pin # Tx Pin # Tx control Pin # Rx L 0 L 0 J R. Ja R Note that all components within this area are only used if a R option kit () is installed. Otherwise they are omitted and all communication is via the R port. JE MIROPROE PTY LT ONI RO, ONI, VI, Ph (0) PT PROJET NUMER 00v.0 Fax (0) jed@jedmicro.com.au VERION TE -Mar-00 HEET OF