VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD

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1 POWER ELETRONIS **- Switching Power Regulation** V and.v outputs are isolated from High Voltage, but not each other Isolated Power Supply power.sch FTI US URT FTI US URT ftdi_uart.sch Safety Loop Wiring SLOOP_TRL SFETY_TRL HRG_TRL FN_TRL HRGE_TRL FN_TRL safety_loop.sch S SL TX RX SFETY LOOP WIRING S SL RX TX _VR 0p VR MIROONTROLLER Maximum Frequency atasheet (Page ) Vsafe =./*(F-)+. X 0MHz _VR 0 0p 0 TK TMS TO TI RX TX VR ecoupling apacitors (U) 0.u XTL XTL PF0(0) 0 PF() PF() PF() PF(/TK) PF(/TMS) PF(/TO) PF(/TI) REF PG0(WR) PG(R) PG(LE) PG(TOS) PG(TOS) PE0(RX0/PI) PE(TX0/PO) PE(XK0/IN0) PE(O/IN) PE(O/INT) PE(O/INT) PE(T/INT) PE(IP/INT) V V +.V V VR Reset Switch U (0)P0 ()P 0 ()P ()P ()P ()P ()P ()P (SS)P0 0 (SK)P (MOSI)P (MISO)P (O)P (O)P (O)P (O0/O)P ()P0 ()P (0)P ()P ()P ()P 0 ()P (/LK0)P (SL/INT0)P0 (S/INT)P (RX/INT)P (TX/INT)P (IP)P (TXN/XK)P 0 (RXN/T)P (T0)P T0N-M SL S 0k R WTHOG P0 P NTX NRX SW +.V SLOOP_ET SLOOP_ET SLOOP_TRL HRG_TRL FN_TRL P0 P P P P P SW_SL SW_S GROUNE LOW VOLTGE SYSTEM STTUS LES +.V P P0 k R k R EXTERNL WTHOG +.V +V +.V +V _VR k R GREEN RE POWER FULT GREEN _VR SPRE N TRNEIVER NTX N Transceiver NTX +.V +.V +.V 0.u 0.u 0.u +.V 0k R _VR RST V +.V U M0 WTHOG MR WI NRX NRX can_xcvr.sch I PULLUP +.V +.V _VR Open rain reset pull-up resistor Threshold:. V Timeout: 00 ms Reset: 0 ms ONNETORS External onnectors EXTERNL ONNETORS connectors.sch S SL 0k R 0k R EVELOPMENT ONLY Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: / File: pacman-main.sch Title: attery Pack Management omputer Size: USLetter ate: Kiad E... kicad.0.-+ubuntu.0.-stable Rev: 0. Id: /

2 HIGH VOLTGE INTERFES TT+ PK+ PK- PK- LOW_ET HRG_ET S_HV SL_HV HV_ V_MPS URRENT_HV_ URRENT_HV_ PK- TT+ PK+ LOW_ET HRG_ET S_HV SL_HV V_MPS MPS_ MPS_ PWR_FLG PWR_FLG PK+ HV_ HIGH VOLTGE POWER This power supply is responsible for delivering non-isolated V power to the high voltage electronics. ll MS bus connected devices are powered from this regulator. Maximum current draw 0m. This Switcher was selected for its high efficiency even at light load. F SK0-LTP HV_PWR % R 0 0u PWR_FLG u 0u Vin SW RUN U VF LT OVLO SS 0 VPRG VPRG SK0-LTP MS_ L 0u HIGH VOLTGE R k 0u MS_ 0u HV_ LOW VOLTGE PWR_FLG PWR_FLG S SL +V S SL PK VOLTGE SENSOR N HRGE SENSOR PK % R TT+ V_MPS LERT VUS 0 IN+ IN- HRG_ET MS_ HIGH VOLTGE IGITL I/O PF 0 P0 P P P P P P P V VSS 0.u HV_ This I/O expander is responsible for relaying digital signals accross the HV-LV isolation barrier via the I bus. R0 0k VS U IN_ 0 S SL I ddress 0x (see datasheet page ) dditional documentation of the use of this component is req'd. RRR0P0TL Q LOW_ET 0k R ypass apacitor (U) 0.u S_HV SL_HV HV_ ypass apacitor (U) MPS_ MPS_ 0u U SL S 0 INT HV_ I ddress 0x (see datasheet page ) IN0 IN IN IN I ddress 0x0 (see datasheet page ) SL_HV S_HV HV_ HV_ HV_ V U S HV_ 0.u R RY S SL 0 HV_ HV_PWR HV_ ypass apacitor (U) HV_ S_HV SL_HV 0u I PULLUP HIGH VOLTGE S_HV SK0-LTP + EVELOPMENT ONLY Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /Isolated Power Supply/ File: power.sch Title: attery Pack Management omputer Size: USLetter ate: Kiad E... kicad.0.-+ubuntu.0.-stable m S_HV SL_HV R k R0 k VIN+ VIN+ The flyback regulator responsible for delivering V isolated power to low voltage systems has been replaced with an isolated / converter. This is due to the insufficient output current (00m) available when assembled. ost is comparable. I ISOLTOR 0.u 0.u 0.u SL_HV U NSS0 HV_ VIN- VIN- VOUT+ VOUT- m V S SL LOW VOLTGE N ISO U Si00 OPTO +V 0u +V 0.u V S SL Maximum urrent raw on V output:. NZHV m 0.V Linear Regulator VI U NPSTTG +.V S VO SL 0.u 0.u +.V Rev: 0. Id: / +.V

3 SFETY LOOP RELY GROUNE LOW VOLTGE +.V +V SFETY_TRL HRGE_TRL FN_TRL SLOOP_ET SLOOP_TRL HRG_TRL FN_TRL SLOOP_ET OPTO-ISOLTOR ON SL LOSE SIGNL This device provides a galvanically isolated signal to the microcontroller to let it know the safety loop is closed in all components. The HV current sensor is enabled as a result. This mean the IRs should be closed if functional. This relay is responsible for switching the PMN safety loop connection ON/OFF. The lights show the user at a glance if the safey loop is open or closed. This relay is capable of switching. The SLOOP_TRL signal is active low. SLOOP_TRL SLOOP_ SK0-LTP RLY GLE- RRR0P0TL Q +.V SLOOP_ and pins are shorted together only when the safety loop is not opened by this board. Voltage between and greater than 0 means the safety loop is not opened by any other component in the system. +.V +V SLOOP_ SLOOP_ SLOOP_ SLOOP_ FN+ k LE+ LE- R SLOOP_ SLOOP_ SLOOP_ SLOOP_ FN+ SLOOP_ SLOOP_ SLOOP_ 0k R U V Vo SLOOP_ET 0.u +.V FN ONTROL P-FET HRGE ONTROL P-FET This MOSFET is responsible for connecting the HRGE relays when the pack charger has been connected. Power is supplied from either the pack terminals, or US connector. SLOOP_ HIGH SIE P-FET RIVER This device is responsible for driving the high side p-fet switches. HRG_TRL FN_TRL TLP U0 Y Y SNLVG0 V HRG_TRL FN_TRL +.V This MOSFET is responsible for switching the charge fan ON/OFF. The fan will not come on automatically when charging begins, it is controlled by the software. Fan Output Voltage: V +V FN_TRL R 0k Q RRR0P0TL SK0-LTP FN+ oil Output Voltage: V HRG_TRL +V HRG_TRL R 0k k R Q RRR0P0TL GREEN SK0-LTP HRGE RLY PK+ TS- HRGE+ EVELOPMENT ONLY Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /Safety Loop Wiring/ File: safety_loop.sch Title: attery Pack Management omputer Size: USLetter ate: Kiad E... kicad.0.-+ubuntu.0.-stable Rev: 0. Id: /

4 GROUNE LOW VOLTGE +.V +V +.V +V NTX NTX NRX NRX N TRNEIVER +V +V 0.u NRX NTX k R U RX TX Vref Rs VSS V NH NL MP-I/SN 0 R NH NL NOTE: O NOT populate R. R provides the ability to use this board as a terminating N node in development only. EVELOPMENT ONLY Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /N Transceiver/ File: can_xcvr.sch Title: attery Pack Management omputer Size: USLetter ate: Kiad E... kicad.0.-+ubuntu.0.-stable Rev: 0. Id: /

5 GROUNE LOW VOLTGE +.V +V +.V +V VUS VUS US+ US+ US- US- US URT This is an FTI US Serial onverter I, it can be used to upload code, configure the device, or transfer debugging information if the software is configured properly. TX RX TX RX rivers available for Windows, Mac OS & Linux US OOTSTRP POWER This diode is used to power the PMN computer board when the battery pack has been fully discharged. If voltage is not present between PK+ and PK-, then this diode will allow the US port to supply up to 00m of sustained current. For periods less than 0. seconds, can be drawn. +V VUS VUS US- US+ 0 VIO V US- US+ OSI OSO VOUT U TX RX RTS TS TR R RI US0 US US US US 0 TX RX TR FTI Reset onnection 0.u TR SK0-LTP 0 0.u TEST FTRL EVELOPMENT ONLY Supervisor: hristopher Nadovich Fall Semester 0 Lafayette ollege Sheet: /FTI US URT/ File: ftdi_uart.sch Title: attery Pack Management omputer Size: USLetter ate: Kiad E... kicad.0.-+ubuntu.0.-stable Rev: 0. Id: /

6 POWER HIGH VOLTGE P HRGE+ TT+ PK- US URT US J GROUNE LOW VOLTGE +.V +V +.V +V LETET ETET EXT I P P P SHIEL_ SHIEL_ J RJ R R R R HV_ HRG_ET PK- LOW_ET PK- PK- S_HV PK- SL_HV MS_ jumper in the nderson charge connector pulls an input low on the HV I expander, corresponding to either charge or low current output. V_MPS HV_ URRENT_HV_ URRENT_HV_ URRENT_HV_ URRENT_HV_ This RJ (RJ with center four pins utilized) connected allows the M-0 current sensor to connect to the board. VUS VUS 0 Vbus Shield_ GPIO HEER 0." I onnector External User Interface oard SW_S SW_SL P P P P P P0 GPIO P + - Shield_ This connector contains pins for I communication with the L screen, input from control panel push buttons, and to illuminate the pack alile LE.. If, at a later time, more complicated Ls, or more I/O is required these pins can be utilized. US+ US+ US- US- PK WIRING HRNESS PPLITION NOTE Port J is a - backplane connector, which will be connected to the pack wiring harness via solder pot connections. The wiring of this connector, and its inputs/outputs are described in more detail in the pack wiring diagram. +V 0 0 LE+ LE- +.V SLOOP_ and SLOOP_ pins are shorted together only when the safety loop is closed. SFETY LOOP / SLOOP_ SLOOP_ SLOOP_ SLOOP_ SLOOP_ SLOOP_ SLOOP_ SLOOP_ Pins in these sections are connected to obsolete signals in the test stand. They may be used, but the test stand must be updated as well. FN GLV HRNESS FN+ NH NL J KPLNE ONNETOR VR EUGGING JTG Programming/ebug Header P TK TK TO +.V TO TMS _VR TMS _VR TI TI 0 JTG EVELOPMENT ONLY Supervisor: hristopher Nadovich Spring Semester 0 Lafayette ollege Sheet: /External onnectors/ File: connectors.sch Title: attery Pack Management omputer Size: USLetter ate: Kiad E... kicad.0.-+ubuntu.0.-stable Rev: 0. Id: /