AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index

Transcription

1 XM0-EV-RTLE- SMK0 emo oard Schematic Index Page : Schematic Index (This Page) Page : RTLE GigaPHY MHz rystal RJ- Transformer Page : Host Interface onnector Power Page : History Page : X0 EEPROM Note:.Please refer to X0 Gigabit Ethernet ontroller pplication esign Note for more X0 P layout design notes..please deliver us your X0 schematic and P layout files for further review..please refer to ppendix of the latest X0 datasheet (v.0 or later) for more details of X0 System Power Up Reference lock esign onsiderations..please contact RealTek's support guys to get the latest RTLE reference schematic, P Layout Guide and further suggestions before making your P board. SIX ELETRONIS ORPORTION Schematic Index Size ocument Number Rev XM0-EV-RTLE-.00 ate: Wednesday, September 0, 0 Sheet o f

2 S0 Host Interface onnectors VH VH *Note- VH J N,ON uf/v J HEER X SN HLK H H H H H H H H MU_OEN Power ircuit V to.v LO Regulator with 00m output current N,uF/V N, U J HEER X *Note- H H H H H0 H H WEN N,RT-PG VIN VOUT N,uF/0V H H H H H H H H H H H H H H H H N, J HEER X L L H0 H H H H H0 H H H H H0 H H H H H0 VH N,TI00U0 MV TI00U0 uf/0v R K LE R *Note-: The VH should be kept the trace wider than 00mil. The V power trace as short as possible with Regulator input pin and kept the trace over than 00mils as possible. *Note-: This power circuit is optional to provide separate.v power sources for X0 and RTLE. The,, and as close to Regulator (U) VIN/VOUT pins for good power efficiency and please kept the trace over than 0mils as possible. *Note-: The 0, as close to Regulator (U) VIN pin for good power regulation and kept the V trace wider than 00 mils. The L, and as close to U's LX pin for good power swiching. H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H H0 H H H H H SN MU_OEN WEN HLK H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H H0 H H H H H SN MU_OEN WEN HLK, Power ircuit VH 0 uf/v *Note- R.K V to.v Switching Regulator with 00m output current U RT00P VIN EN LX F L.uH pf R 00K % R K % uf/0v PHY_V MV PHY_V, MV PHY_V, R.K % SIX ELETRONIS ORPORTION Host onnector and Power Size ocument Number Rev XM0-EV-RTLE-.00 ate: Wednesday, September 0, 0 Sheet o f

3 , H 0 H H H H H H H H H H 0 H H H H H H H H H H 0 H H H H H H H H H H 0 H H H H H H H H H H H 0 H H H H H SN MU_OEN H LK H 0 H H H H H H H H H H 0 H H H H H H H H H H 0 H H H H H H H H H H 0 H H H H H H H H H H H 0 H H H H H SN MU_OEN H LK OR Logic Gate R 0 *Note- MV MV MV V R R R.K.K.K V V H LK 0 MV 0 MV R 0 V 0 N,.K H 0 H 0 0 R H 0 H H N,.K H H H R V H.K MV H 0 H H 0 V H H H H H R N,0 U V TEST V V HLK V V H H0 H H H H H WKEUP H V H V H H H0 V H H H H H R K V *Note- R.K V R.K R.K R.K V OL RS V RX RX RX RX0 V RX_LK RX_V TX_LK MTXK X0 R.K non-pi / bit Gigabit Ethernet ontroller MTX_EN MTX0 V N N N 0 TEST V TEST V TEST TEST V 0 OL RS V RX RX RX RX0 V RXLK 0 RXV TXLK TXX GTXLK TXEN TX0 V H H V H H H0 H H H H V H H H H H H0 V H H H H H H0 V H H H H H V TX TX TX 0 V MIO M V GPIO TEST TEST0 LK EEO 0 EEI EES EELK PHY SN WEN OEN H H 0 V REG_EN VOUT VR R V H H X0 MV R V MTX MTX MTX.K V MIO MM V GPIO MV LKMO R E EO E EI E ES EELK.K MINT SN R N,0 H OEN H R.K MV R EG_EN V Regulator.V Output MV Regulator.V Input V *Note- H H *Note- MV R 0 GPIO RGMII I/F *Note- MTXK MTX_EN MTX0 MTX MTX MTX MIO MM MINT Hardware onfiguration Setting RX RX RX RX0 RX_LK RX_V LKMO *Note- RX RX RX RX0 RX_LK RX_TL LKMO TX TX_TL TX0 TX TX TX MIO M MINT X0 RGMII -bit/little Endian Mode Unmount R: -bit mode Mount R: -bit mode R.K Unmount R0: Little-endian Mount R0: ig-endian R.K R R R R R 0 R R J P J P JUMPER J UMPER MV, I NTN MV MV MU_OEN SN U OEN MV H H V H H H 0 H H H H MV H H H H H H 0 V H H H H H H 0 V H H H H H R EG_EN.K R, ELMSHM N,.K EEPROM *Note- MV MV X0 Power.V and.v y Pass *Note- U R N,.K MV MV E ES EELK E EI E EO S SK I O V N ORG N, *Note- uf/0v N, V 0 uf/0v *Note- The OR logic gate circuit is necessary if the MU couldn't synchronously provide the host interface clock signals to X0 HLK while powering ON the system. Please refer to ppendix of the latest X0 datasheet (v.0 or later) for more details. If you need to by-pass the OR gate circuit, please remove U, and mount R with 0 ohm resistor. *Note- The VR signal should be wider than 0mils on regulator input trace and, as close to VR for good power regulation. The VOUT signal should be wider than 0mils and, as close to VOUT for good power regulation. *Note- The H pin should be connected to when the MU is set to the double-word boundary mode on X0 -bit mode applications. For X0 -bit mode applications, the H pin should be connected to a proper MU address pin. Please refer to ppendix of X0 datasheet for more details. *Note- Every by-pass capacitors should be as close to each power pin to reduce high freqency power noises. *Note-: The X0 supports -bit mode EEPROM. The EEPROM is optional if the M address can be stored on the Flash memory of your embedded system. *Note- These Ohm terminal resistors should be as close to X0's RGMII interface pins. *Note- The X0 GPIO 0/GPIO signals are pulled down by hardware default. SIX ELETRONIS ORPORTION X0 Size ocument Number R e v.00 XM0-EV-RTLE- Wednesday, September 0, 0 ate: Sheet o f

4 RX RX RX RX0 RX_LK RX_TL LKMO RX RX RX RX0 RX_LK RX_TL LKMO PHY Reset ircuit PHY _V R N,.K *Note- N,0pF R RX_LK RX RX RX RX0 RX_TL RTLE PHY Hardware onfiguration N0 N TXLY R XLY LE0_0 R.K R.K R 0.K R 0.K R.K PHY _V,,, TX TX_TL TX0 TX TX TX MIO M MINT PHY _V PHY _V PHY _V0 TX TX_TL TX0 TX TX TX MIO M MINT PHY _V PHY nalog power.v/.0v PHY Power.V and.0v y Pass L L TI00U0 0.uF/0V TI00U0.uF/0V *Note- XTL MHz +- 0ppm rystal 0 pf PHY_V PHY_V0 *Note- R 0 0 R N,M Y M RYSTL NSK NXH- SM N, PH YRST pf XTL PHY_V PHY _V R.K R N,0 TX TX TX_TL PHY _V0 PH YRST M MIO R XLY LE0_0 LE_ PHY _V0 On-hip Switching Regulator Setting R 0 R N, 0R *Note- ENS WREG On-hip Regulator Power Input.V 0 TX TX TXTL V0 PHYRST M MIO LE/RXLY LE0/PHY_0 LE/PHY_ V0 TX TX0 TX PHY _V MINT R R R N N0 TXLY PHY _V SELRGV PHY _ TX TX0 TX V 0 INT RX RX/N RX/N0 RX/TXLY V RX0/SELRGV RXTL/PHY_ RTLE-V-G V ENSWREG RSET V0 V KXTL KXTL VREG VREG LK REG_OUT 0 PHY _V ENS WREG RSET PHY _V0 PHY _V XTL XTL V REG V REG R.K % R R 0 REGOUT_V0 R _EP LKMO *Note- U N MI[]- 0 MI[]+ V0 MI[]- MI[]+ V MI[]- MI[]+ V0 MI[0]- MI[0]+ On-hip Regulator Power Output.0V L.uH *Note- uf/.v PHY _V0 LE_ PHY _ SELRGV Pull Low MI- MI+ MI0- MI0+ MI- MI+ MI- MI+ MI- MI+ PHY _V0 MI- MI+ PHY _V MI- MI+ PHY _V0 MI0- MI0+ R.K R.K N0 TXLY Pull Low N RXLY 0 SELREG RJ- onnector (with Ethernet magnetic) R.K 0 uf/0v Enable all Nway capabilities elay TXLK/RXLK ns PHY ddress=00 (0x0) Pull Up for.v GMII/RGMII J LS0 P0 P P P P P P P P P P P P P R M H SSIS PHY _V PH Y_V PHY _V0 PH Y_V0 PHY _V Ethernet LE ircuit *Note- uf/0v 0 LE0_0 N,00pF R 0R PHY _V LE Y TX/RX ctivity LE *Note- The 0,, and should be close to L and L as possible for reduce power noise. *Note- Those by-pass capacitors should be as close to every power input pins as possible. *Note- The R and are reserved for EMI, please close to PHY as possible. *Note-. Enable On-chip Switch Regulator: (efault) onnect ENSWREG to PHY_V (i.e. Mount Rand unmount R). isable On-chip Switch Regulator: onnect ENSWREG to (i.e. Mount R and unmount R) *Note- The.V power input VREG trace should be wider than 00mils (Keep floating while disabling on-chip switching regulator) The capacitors and as close to the VREG pin (within 00mils) for good power effeciency. must be a ceramic (XR) capacitor is recommended to be ceramic capacitor *Note- L (.uh) should be as close to RTLE REG_OUT pin (within 00mils). The.0V power output REG_OUT trace should be wider than 0 mils. The and capacitors as close to L if possible. (Keep floating while disabling on-chip switching regulator) must be a ceramic (XR) capacitor is recommended to be ceramic capacitor *Note- The Ethernet LE circuit is a reference circuit while the PHY ddress was set to 0h. (i.e. LE0_0 was pulled high and LE_ was pulled low) Please refer to Realtek's GigaPHY reference circuit for more details if necessary. The and are reserved for EMI that should be close to LE0_0 and LE_ pins. LE_ N,00pF L E G Link LE (ny speed) *Note:. The RTLE GigaPHY reference circuits are for customers' reference purpose. Please contact Realtek's support guys to get the latest RTLE reference schematic and Layout Guide before making your P board.. Please exactly follow up Realtek's RTLE Layout Guide to layout RTLE.V to.0v On-chip Switching Regulator and Ethernet magnetic circuits; otherwise,the RTLE might not work normally. Please refer to Realtek's layout guide for more details. SIX ELETRONIS ORPORTION RTLE R 0R Size ocument Number R e v.00 XM0-EV-RTLE- Wednesday, September 0, 0 ate: Sheet o f

5 Revision History Revision ate omment V.00 0/0/0 Initial release. SIX ELETRONIS ORPORTION History Size ocument Number Rev XM0-EV-RTLE-.00 ate: Wednesday, September 0, 0 Sheet o f