Pine64. Pine64. Pine64. Pine64. Pine64. Pine64. Pine64

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Ferdinand Gallagher
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1 Jack V TX Jack V TO.V V TO.V MI MI E E.V,.V,.V Pine Pine US* US* V TO.V V TO.V V TO.V V.V,.V,.V V TO.V V TO.V V TO.V V RJ M MI RTLN LQFP MI MI E E.V,.V,.V.V,.V,.V Pine Pine US* US* V TO.V V TO.V V TO.V V V TO.V V TO.V V TO.V V MI E.V,.V,.V Pine US* V TO.V V TO.V V TO.V V (Optional) EEPROM XTL M S SK n S SK n MI MI E E.V,.V,.V.V,.V,.V Pine Pine US* US* V TO.V V TO.V V TO.V V V TO.V V TO.V V TO.V V opyright, PINE LUSTER OR Size ocument Number Rev lock_iagram. Thursday, ecember, ate: Sheet of

2 VL_ VL VH VIO VV V V VV L uh VV PN IN_PSIT G Y L uh P P U RT U RT F P P P P.uF/V-XR R.K % _JK V E- uf pf uf.uf P pf J OMP OMP.K % R N N.uF R K.uF R K.nF R P V_uF PS_PXON_*. V_uF P P.uF/V-XR uf/v-yv.uf/v-yv uf.uf nf R K OOT nf SW R K uf/v-yv.uf/v-xr P uf uf uf P P R OOT SW.uF/V-YV.K %.uf/v-xr uf uf uf F GN uf/v-yv V PS_PXON_*..uF/V-XR E- uf F GN GN GN GN GN GN GN GN K %.nf GN GN GN GN GN GN GN N-pF/V-XR N-.uF/V-YV.uF/V-XR.uF N.uF N SSOP_W_PT SSOP_W_PT HEER 大 P 间间.mm PIN LE_K / PLE / SMI_SEL: ** Pull Up: EEPROM SMI interface. Pull own: MIO slave interface. VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO R J.V.V.V W PIN GPIO /PLE / _PHY: VIO.V -V VV VV J ** Pull Up: Enable embedded PHY Pull own: isable embedded PHY VIO PIN PLE / ISUTOLO ** Pull Low: Enable uto load EEPROM Pull High: isable uto load EEPROM R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% R.K/% Y MHz pf/v-npo R K/% OM OM N R.K V PS ON pf/v-npo OM OM HEER.uF/V-XR VV PIN PLE / IS_ Pull Low: Enable ** Pull High: isable VL VIO VL VIO VL R.K/% Q MMT VH uf/v-yv R.K/% V OM n OM OM R POWER ON K Power on N U VS V PLE PLE S SK PIN PLE / EEPROM_MO V WP SL S GN V V V SK S V V R ** Pull Low: ~.V OM U Pull High: ~ HEER x W PIN PLE: Must Pull High or Floating PIN PLE: Must Pull High or Floating VIO LE (R) PIN PLE / Must Pull Low PIN PLE Must Pull High PIN PLE: Must Pull High or Floating LE_K / PLE / LE_ / PLE / GPIO / PLE / PLE / RESERVE PLE / GPIO PLE / PLE / IS_ PLE / RESERVE PLE / RESERVE PLE / GPIO PLE / GPIO PLE / PLE / PLE / PLE / GPIO PLE / GPIO PLE / VH S SK n XTLI XTLO VH VL SMI_SEL PLE VL _PHY PLE RESERVE ISUTOLO EEPROM_MO GPIO VL VIO_ VL PLE RESERVE GPIO PLE PLE PLE PLE RESERVE RESERVE MI_ MI-_ MI_ MI-_ M VL MI_ MI-_ MI_ MI-_ GIT ETHERNET HOLE VIO M J Tap Up T MI-_G MI_G MI-_G MI_G MI_ MI-_ MI_ MI-_ RTLN (LQFP) MI-_G MI_G MI-_G MI_G MI_ MI-_ MI_ MI-_ MI-_F MI_F MI-_F MI_F MI_ MI-_ MI_ MI-_ PLLVL R N-/% MI_ R MI-_ MI_ MI-_ HOLE M RJ- MI_ MI-_ MI_ MI-_ HOLE M GN GN GN GN VH PMIN PMIP PMIN PMIP VL PMIN PMIP PMIN PMIP VH PMIN PMIP PMIN PMIP VL PMIN PMIP PMIN PMIP PLLVL PMIN PMIP PMIN PMIP VL PMIP PMIN PMIP PMIN VL PMIP PMIN PMIP PMIN VH PMIP PMIN PMIP PMIN VL PMIP PMIN PMIP PMIN PLLVL TESTK PMIP PMIN PMIP PMIN VL MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ MI-_G MI_G MI-_G MI_G MI_ MI-_ MI_ MI-_ MI MI- MI MI MI MI- MI MI- MI MI- MI MI-.uF P MI MI- MI MI- MI-_G MI_G MI-_G MI_G PLLVL MI-_F MI_F MI-_F MI_F.uF P VIO VL T G G- R R HOLE RTLN-G R R PLE Y Y- ST-JKWNL PMIP PMIN PMIP PMIN VH PMIP PMIN PMIP PMIN VL PMIP PMIN PMIP PMIN VH GN MIREF VL VH VL VL VL VL VH PMIP PMIN PMIP PMIN VL PMIP PMIN PMIP PMIN VH PMIP PMIN PMIP PMIN PLE EP hanged J from HY to ST-JKWNL VL VIO L.uH@ VL VIO PLLVL VL IN_PSIT MI_F MI-_F MI_F MI-_F MI_E MI-_E MI_E MI-_E MI_E MI-_E MI_E MI-_E R MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ VIO MI-_F MI_F MI-_F MI_F MI-_E MI_E MI-_E MI_E MI-_E MI_E MI-_E MI_E VL_ MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ R VIO.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR uf/v-yv pf/v-xr.k/% R R K/%.uF U LVT V Y Y Y Y Y Y GN R R/% _F _F R R/% R R/% _E _E RST R R/% R R/% VIO VL L.uH@ R R/% PLLVL _ VL SW T-TS-L IN_PSIT _.uf/v-xr R R/% _G _G R VIO.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR.uF/V-XR pf/v-xr _ V R R/% _ Y _ Y R R/% _ Y Y Y GN Y Reset opyright, uf/v-yv.uf/v-xr IP H=mm/xmm U LVT.uF PINE LUSTER OR Size ocument Number Rev RTLN. ate: Thursday, ecember, Sheet of

3 PS_ VV V_ USVUS_ Place filter network close to RX_LK. VV VV VV VV VV Note : The Trace length from, to Pin,(VREG) must be within. cm. The trace width from V to Pin, should>mils V_ RTL: =uf(xr) RTLE: =./uf(xr) VREG MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only) V_V_ PHY only for RTLE V_ V_ onnect SWREG to V_ to enable Switching regulator or connect SWREG to GN to disable Switching regulator. Enable/isable SWREG VV VV RTL: L=.uH RTLE: L=./.uH RTL:= uf(xr) RTLE:=./uF(XR) L.uH@ _ R.K R for RTL R for RTLE For wake on LN function, please keep PHYRST pin to high. R,R: onfig for all capability R,R: PHY ddress=(rtl) R,R,R: PHY ddress=(rtle) R,R: Without TX/RX elay onfiguration Setting VOUT=.*(R/R) VOUT=.*(R/R) V_V_.V Power V_ V_ R for EMI Note : The Trace length between L and PHY's Pin must be within. cm. and to L must be within.cm. V_./.V/./.V RGMII Power V_ V_ VOUT=.*(R/R) V_V_ R for.v RGMII I R for.v RGMII (From.-.V LO) R for./.v RGMII (RTLE-VL only) PHY_V_ VV U PHY_V/_ ST OUT J GN V_ PHY_V_ PHY_V/_ K % R JU LOK P_ URT_TX_ S_ TXTL_ P_ RX_N_ M_ P_ P_ RX_N_ URT_RX_ TXLK_ RX_N_ TX_ RXTL_N_ RX_LK_N_ T T T T T US-P_ US-M_ HGLE _ PS_ PS_ PS_.uF ONN SOKET x/sm KEY_ PL_ P_ RX_N_ P_ SL_ LK_N_ MIO_ TX_ TX_ TX_ T RSTN T RLK M T US-P_ US-M_ PWR_ON_ VV USVUS_ USVUS_ USVUS_ T_SSOR_ V_ V_ V_ R R LE (R) T T T LOK T RSTN RLK uf(xr).uf RX_N_ RX_N_ RX_N_ RX_N_ RXTL_N_ LK_N_ RX_LK_N_ VV HGLE_ PWR_ON_ P_ URT_TX_ P_ P_ VV SL_.uF J uf R R HEER x/sm J HEER X Z ZH-. IN OUT VR GN uf.uf R R R R R R R uf(xr) RX_N_ RX_N_ RX_TXLY_ RX_SELRGV_ RXTL LK_ RX_LK_ T.uF pf-n.uf.uf MI[] MI[]- V MI[] MI[]- V MI[] MI[]- V MI[] MI[]- N pf.k R R.K Y MHz XTL_ pf R.K(%) R R GN(EP) GN LK VREG VREG KXTL KXTL V V SWREG V RTL RTLE RXTL/PHY RX/SELRGV V RX/TXLY RX/N RX/N RX INT V TX TX TX.K R R.K R.K R.K U V LE/PHY LE/PHY PME LE_RXLY MIO M PHYRST V TXTL TX TX.uF R R R S.nF XR V R.K R.K R.K U ST OUT J GN U ST OUT J GN.K(N).K/N K R K % R.K % R K % uf uf(xr) uf(xr) uf(xr).uf.uf R R.uF.uF.K(N) R.K.uF uf(xr) IN_PSIT.K(N).uF.uF U-XR U-XR c.uf.uf.uf.uf.uf.uf.uf R.K % uf(xr) R uf(xr) R R R.uF.uF R R.uF.uF N N R R LE (g) LE (y) K % R T T T M PL P_ KEY_ URT_RX_ P_ P_ S_ MI_ MI-_ V_ MI_ MI-_ V_ MI_ MI-_ V_ MI_ MI-_ VREG_ GN XTL GN LK_ VREG_ VREG_ XTL_ V_ V SWREG_ V_ RXTL RX_SELRGV_ V_V_ RX_TXLY_ RX_N_ RX_N_ RX_LK_ INT_ V_V_ TXLK_ TX_ TX_ V_ LE LE PME_ LE_RXLY_ MIO_ M_ PHYRST_ V_ TXTL_ TX_ TX_.uF LE LE LE_RXLY_ LE LE PL_ T J HEER V_ T_SSOR_ R K/N PS-.V PS_ uf(xr).uf OL.uH OU GN MT SOT- LX N F SS Vout =. x ( R/R) Imax = O R K-% R M-% VV uf(xr).uf Reserve for.v RGMII power (If M support.v RGMII) VV USVUS_ VV R K.uF nf U NP uf/v USVUS_ IN OUT US-M_ FLG ON/OFF GN US-P_ PWG- US. HOST- P J US--R U VUS IN OUT M FLG P ON/OFF GN GN PWG- S S R K.uF nf NP uf/v US-P_ US-M_ MIRO US J VUS - GN GN nc nc micro US TYPE opyright, PINE LUSTER OR Size ocument Number Rev PHY. Thursday, ecember, ate: Sheet of

4 JU _ PS_ P_ URT_TX_ S_ TXTL_ P_ RX_N_ M_ P_ P_ RX_N_ URT_RX_.uF ONN SOKET x/sm KEY_ PL_ P_ RX_N_ P_ SL_ LK_N_ MIO_ TX_ TX_ TX_ US-P_ US-M_ PWR_ON_ VV VV USVUS_ USVUS_ USVUS_ T_SSOR_ V_ V_ USVUS_ R Place filter network close to RX_LK. VV VV R VV uf.uf R R J HEER X LE (g) R R R R R R R Note : The Trace length from, to Pin,(VREG) must be within. cm. The trace width from V to Pin, should>mils V_ RTL: =uf(xr) RTLE: =./uf(xr) VREG MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only).uf.uf MI[] MI[]- V MI[] MI[]- V MI[] MI[]- V MI[] MI[]- N V_V_ PHY only for RTLE V_ V_ R.K(%) R R GN(EP) GN LK VREG VREG KXTL KXTL V V SWREG V RTL RTLE RXTL/PHY RX/SELRGV V RX/TXLY RX/N RX/N RX INT V TX TX TX.K R R.K Y MHz onnect SWREG to V_ to enable Switching regulator or connect SWREG to GN to disable Switching regulator. Enable/isable SWREG U V LE/PHY LE/PHY PME LE_RXLY MIO M PHYRST V TXTL TX TX VV VV VOUT=.*(R/R) VOUT=.*(R/R) RTL: L=.uH RTLE: L=./.uH RTL:= uf(xr) RTLE:=./uF(XR) L.uH@ _ R.K R for RTL R for RTLE V_V_ For wake on LN function, please keep PHYRST pin to high. U ST OUT J GN U ST OUT J GN R,R: onfig for all capability R,R: PHY ddress=(rtl) R,R,R: PHY ddress=(rtle) R,R: Without TX/RX elay onfiguration Setting./.V/./.V RGMII Power PHY_V_ V_ R.K VV VOUT=.*(R/R).V Power V_ V_.uF R for EMI Note : The Trace length between L and PHY's Pin must be within. cm. and to L must be within.cm. V_ V_V_ V_.uF.uF R for.v RGMII I R for.v RGMII (From.-.V LO) R for./.v RGMII (RTLE-VL only) R.K % R PHY_V/_.uF N R R V_ PHY_V_ PHY_V/_ K % R.K R R.K R.K XTL_ pf R.K.uF.uF R R S.nF XR V R.K R uf uf(xr).k/n K uf(xr).k(n) uf(xr).uf.uf uf(xr) R.uF IN_PSIT.K(N) U ST OUT J GN U-XR U-XR.uF R R.uF R N K % R TXLK_ RX_N_ TX_ RXTL_N_ RX_LK_N_ US-P_ US-M_ HGLE PS_ PS_ PS_ RX_N_ RX_N_ RX_N_ RX_N_ RXTL_N_ LK_N_ RX_LK_N_ VV HGLE_ PWR_ON_ P_ URT_TX_ P_ P_ VV SL_ uf PL_ RX_N_ RX_N_ RX_TXLY_ RX_SELRGV_ RXTL LK_ RX_LK_ PL P_ KEY_ URT_RX_ P_ P_ S_ pf-n MI_ MI-_ V_ MI_ MI-_ V_ MI_ MI-_ V_ MI_ MI-_ VREG_ GN XTL_ pf _ GN LK_ VREG_ VREG_ XTL_ V_ V SWREG_ V_ RXTL RX_SELRGV_ V_V_ RX_TXLY_ RX_N_ RX_N_ RX_LK_ INT_ V_V_ TXLK_ TX_ TX_ V_ LE LE PME_ LE_RXLY_ MIO_ M_ PHYRST_ V_ TXTL_ TX_ TX_ R.K R.K R K % R.K % R K %.uf.uf LE LE LE_RXLY_.uF.uF R.K(N).uF uf(xr) uf(xr).uf.uf LE R.uF.uF R LE (g) LE (y) LE J HEER V_ T_SSOR_ R K/N PS-V PS_ uf(xr).uf OL.uH OU GN MT LX N F SOT- Vout=.(Rtop/Rbottom) SS Vout =. x ( R/R) Imax = O R K % R M % uf(xr) VV.uF VV.uF U IN OUT FLG ON/OFF GN PWG- R K Reserve for.v RGMII power (If M support.v RGMII) VV USVUS_.uF nf US. HOST- P J U NP US--R uf/vusvus_ IN OUT US-M_ VUS FLG M ON/OFF GN US-P_ P PWG- GN S S R K nf NP uf/v US-P_ US-M_ MIRO US J VUS - GN GN nc nc micro US TYPE opyright, PINE LUSTER OR Size ocument Number Rev PHY. Thursday, ecember, ate: Sheet of

5 JU _ PS_ P_ URT_TX_ S_ TXTL_ P_ RX_N_ M_ P_ P_ RX_N_ URT_RX_ TXLK_ RX_N_ TX_ RXTL_N_ RX_LK_N_ US-P_ US-M_ HGLE KEY_ PL_ P_ RX_N_ P_ SL_ LK_N_ MIO_ TX_ TX_ TX_ US-P_ US-M_ PWR_ON_ VV VV USVUS_ USVUS_ USVUS_ T_SSOR_ V_ V_ USVUS_ Place filter network close to RX_LK. VV VV VV uf R R R Note : The Trace length from, to Pin,(VREG) must be within. cm. The trace width from V to Pin, should>mils V_ RTL: =uf(xr) RTLE: =./uf(xr) VREG MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only) V_V_ PHY only for RTLE V_ V_ onnect SWREG to V_ to enable Switching regulator or connect SWREG to GN to disable Switching regulator. Enable/isable SWREG VV VV VOUT=.*(R/R) VOUT=.*(R/R) R.K RTL: L=.uH RTLE: L=./.uH RTL:= uf(xr) RTLE:=./uF(XR) L.uH@ _ R for RTL R for RTLE V_V_ For wake on LN function, please keep PHYRST pin to high. R,R: onfig for all capability R,R: PHY ddress=(rtl) R,R,R: PHY ddress=(rtle) R,R: Without TX/RX elay onfiguration Setting./.V/./.V RGMII Power PHY_V_ V_ VV VOUT=.*(R/R).V Power V_ V_ R for EMI Note : The Trace length between L and PHY's Pin must be within. cm. and to L must be within.cm. V_ V_V_ V_ R R for.v RGMII I R for.v RGMII (From.-.V LO) R for./.v RGMII (RTLE-VL only) PHY_V/_ N V_ PHY_V_ PHY_V/_ K % R R MI[] MI[]- V MI[] MI[]- V MI[] MI[]- V MI[] MI[]- N GN(EP) GN LK VREG VREG KXTL KXTL V V SWREG V RTL RTLE RXTL/PHY RX/SELRGV V RX/TXLY RX/N RX/N RX INT V TX TX TX.K R R.K R.K U V LE/PHY LE/PHY PME LE_RXLY MIO M PHYRST V TXTL TX TX U-XR R K % R.K %.uf PS_ PS_ PS_ ONN SOKET x/sm R uf RX_N_ RX_N_ RX_N_ RX_N_ RXTL_N_ LK_N_ RX_LK_N_ R VV HGLE_ PWR_ON_ P_ URT_TX_ P_ P_ VV SL_.uF R J HEER X LE (g) R R R R PL_ RX_N_ RX_N_ RX_TXLY_ RX_SELRGV_ RXTL LK_ RX_LK_ PL P_ KEY_ URT_RX_ P_ P_ S_ pf-n MI_ MI-_ V_ MI_ MI-_ V_ MI_ MI-_ V_ MI_ MI-_ VREG_.uF.uF GN XTL_ pf.k R R.K Y MHz _ GN LK_ VREG_ VREG_ XTL_ XTL_ pf R.K R.K(%) R R V_ V SWREG_ V_ RXTL RX_SELRGV_ V_V_ RX_TXLY_ RX_N_ RX_N_ RX_LK_ INT_ V_V_ TXLK_ TX_ TX_.uF.uF V_ LE LE PME_ LE_RXLY_ MIO_ M_ PHYRST_ V_ TXTL_ TX_ TX_ U ST OUT J GN U ST OUT J GN R.K R R.K R.K R R S.nF XR V R K % R.K % R K % uf uf(xr) uf(xr).k/n K uf(xr).k(n).uf.uf.uf.uf LE LE LE_RXLY_.uF uf(xr).uf.uf R R.K R IN_PSIT.K(N).K(N) U ST OUT J GN.uF U-XR.uF.uF uf(xr).uf uf(xr).uf.uf R.uF.uF R.uF LE R N R R.uF.uF R R LE (g) LE (y) LE J HEER V_ T_SSOR_ R K/N PS-V PS_ uf(xr).uf OL.uH OU GN MT LX N F SOT- Vout=.(Rtop/Rbottom) SS O Vout =. x ( R/R) Imax = R K % R M % uf(xr) VV.uF VV.uF U IN OUT FLG ON/OFF GN PWG- R K Reserve for.v RGMII power (If M support.v RGMII) VV USVUS_.uF nf US. HOST- P J U NP US--R uf/vusvus_ IN OUT US-M_ VUS FLG US-P_ M ON/OFF GN P PWG- GN S S R K nf NP uf/v US-P_ US-M_ MIRO US J VUS - GN GN nc nc micro US TYPE opyright, PINE LUSTER OR Size ocument Number Rev PHY. Thursday, ecember, ate: Sheet of

6 JU _ PS_ P_ URT_TX_ S_ TXTL_ P_ RX_N_ M_ P_ P_ RX_N_ URT_RX_ TXLK_ RX_N_ TX_ RXTL_N_ RX_LK_N_ US-P_ US-M_ HGLE.uF PS_ PS_ PS_ ONN SOKET x/sm KEY_ PL_ P_ RX_N_ P_ SL_ LK_N_ MIO_ TX_ TX_ TX_ US-P_ US-M_ PWR_ON_ VV VV USVUS_ USVUS_ USVUS_ T_SSOR_ V_ V_ USVUS_ R Place filter network close to RX_LK. VV VV VV uf uf RX_N_ RX_N_ RX_N_ RX_N_ RXTL_N_ LK_N_ R.uF R J HEER X LE (g) R R R R R pf-n Note : The Trace length from, to Pin,(VREG) must be within. cm. The trace width from V to Pin, should>mils V_ RTL: =uf(xr) RTLE: =./uf(xr) VREG MI_ MI-_ MI_ MI-_ MI_ MI-_ MI_ MI-_ Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only).uf.uf V_V_ PHY only for RTLE pf.k R R.K Y MHz.K R R.K R.K XTL_ pf R.K V_ V_ R.K(%) R R onnect SWREG to V_E to enable Switching regulator or connect SWREG to GN to disable Switching regulator. Enable/isable SWREG VV.uF VV.uF VOUT=.*(R/R) VOUT=.*(R/R) RTL: L=.uH RTLE: L=./.uH RTL:= uf(xr) RTLE:=./uF(XR) L.uH@ _ R.K R for RTL R for RTLE R R S.nF XR V V_V_ For wake on LN function, please keep PHYRST pin to high. R,R: onfig for all capability R,R: PHY ddress=(rtl) R,R,R: PHY ddress=(rtle) R,R: Without TX/RX elay onfiguration Setting U ST OUT J GN U ST OUT J GN R.K R R.K R.K R K % R.K % R K %.K/N K.V Power V_ V_./.V/./.V RGMII Power uf uf(xr).k(n) uf(xr) uf(xr).uf PHY_V_.uF.uF.uF V_ uf(xr) R R.uF VV.uF IN_PSIT.K(N) R.K.K(N) U-XR U ST OUT J GN VOUT=.*(R/R) U-XR R for EMI Note : The Trace length between L and PHY's Pin must be within. cm. and to L must be within.cm. V_ V_ V_V_.uF.uF.uF R for.v RGMII I R for.v RGMII (From.-.V LO) R for./.v RGMII (RTLE-VL only) R.K %.uf uf(xr).uf.uf.uf R PHY_V/_ uf(xr).uf R R R.uF N N R.uF.uF R LE (g) LE (y) V_ PHY_V_ PHY_V/_ K % R RX_LK_N_ VV HGLE_ PWR_ON_ P_ URT_TX_ P_ P_ VV SL_ R R R PL_ RX_N_ RX_N_ MI[] MI[]- V MI[] MI[]- V MI[] MI[]- V MI[] MI[]- N GN(EP) GN LK VREG VREG KXTL KXTL V V SWREG V RTL RTLE RXTL/PHY RX/SELRGV V RX/TXLY RX/N RX/N RX INT V TX TX TX U V LE/PHY LE/PHY PME LE_RXLY MIO M PHYRST V TXTL TX TX R R K % R RX_TXLY_ RX_SELRGV_ RXTL LK_ RX_LK_ PL P_ KEY_ URT_RX_ P_ P_ S_ MI_ MI-_ V_ MI_ MI-_ V_ MI_ MI-_ V_ MI_ MI-_ VREG_ GN XTL GN LK_ VREG_ VREG_ XTL_ V_ V SWREG_ V_ RXTL RX_SELRGV_ V_V_ RX_TXLY_ RX_N_ RX_N_ RX_LK_ INT_ V_V_ TXLK_ TX_ TX_ V_ LE LE PME_ LE_RXLY_ MIO_ M_ PHYRST_ V_ TXTL_ TX_ TX_ LE LE LE_RXLY_.uF LE LE J HEER V_ T_SSOR_ R K/N PS-V PS_ uf(xr).uf OL.uH OU GN MT LX N F SOT- Vout=.(Rtop/Rbottom) SS Vout =. x ( R/R) Imax = O R K % R M % uf(xr) VV.uF VV.uF U IN OUT FLG ON/OFF GN PWG- R K Reserve for.v RGMII power (If M support.v RGMII) VV USVUS_.uF nf US. HOST- P J U NP US--R uf/vusvus_ IN OUT US-M_ VUS FLG M ON/OFF GN US-P_ P PWG- GN S S R K nf NP uf/v US-P_ US-M_ MIRO US J VUS - GN GN nc nc micro US TYPE opyright, PINE LUSTER OR Size ocument Number Rev PHY. Thursday, ecember, ate: Sheet of

7 JU _E P_E URT_TX_E S_E KEY_E PL_E P_E RX_N_E P_E SL_E LK_N_E MIO_E TX_E TX_E TX_E US-P_E US-M_E PWR_ON_E VV VV USVUS_E USVUS_E USVUS_E T_SSOR_E V_E V_E USVUS_E Place filter network close to RX_LK. VV VV VV.uF R R R Note : The Trace length from, to Pin,(VREG) must be within. cm. The trace width from V to Pin, should>mils V_E RTL: =uf(xr) RTLE: =./uf(xr) VREG MI_E MI-_E MI_E MI-_E MI_E MI-_E MI_E MI-_E Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only) V_V_E PHY only for RTLE pf R.K V_E V_E onnect SWREG to V_E to enable Switching regulator or connect SWREG to GN to disable Switching regulator. Enable/isable SWREG VV VV.uF For wake on LN function, please keep PHYRST pin to high. VOUT=.*(R/R) VOUT=.*(R/R) R.K R.K RTL: L=.uH RTLE: L=./.uH RTL:= uf(xr) RTLE:=./uF(XR) L.uH@ _E R.K R for RTL R for RTLE V_V_E R,R: onfig for all capability R,R: PHY ddress=(rtl) R,R,R: PHY ddress=(rtle) R,R: Without TX/RX elay onfiguration Setting U ST OUT J GN R.K %.V Power V_E V_E./.V/./.V RGMII Power uf(xr) uf(xr) PHY_V_E R.K V_E.uF VV VOUT=.*(R/R) R for EMI Note : The Trace length between L and PHY's Pin must be within. cm. and to L must be within.cm. V_E V_E V_V_E R R for.v RGMII I R for.v RGMII (From.-.V LO) R for./.v RGMII (RTLE-VL only) uf(xr).uf.uf R PHY_V/_E.uF R N.uF V_E PHY_V_E PHY_V/_E K % R TXTL_E P_E RX_N_E M_E P_E P_E RX_N_E URT_RX_E TXLK_E RX_N_E TX_E RXTL_N_E RX_LK_N_E US-P_E US-M_E HGLE_E _E R R R MI[] MI[]- V MI[] MI[]- V MI[] MI[]- V MI[] MI[]- N GN(EP) GN LK VREG VREG KXTL KXTL V V SWREG V RTL RTLE RXTL/PHY RX/SELRGV V RX/TXLY RX/N RX/N RX INT V TX TX TX.K R R.K R.K U V LE/PHY LE/PHY PME LE_RXLY MIO M PHYRST V TXTL TX TX R R K %.K/N R.K(N) K % R.uF ONN SOKET x/sm R uf RX_N_E RX_N_E RX_N_E RX_N_E RXTL_N_E LK_N_E RX_LK_N_E R uf VV HGLE_E PWR_ON_E P_E URT_TX_E P_E P_E VV SL_E J HEER X LE (g) R R R PL_E RX_N_E RX_N_E RX_TXLY_E RX_SELRGV_E RXTL E LK_E RX_LK_E PL_E _E P_E KEY_E URT_RX_E P_E P_E S_E pf-n MI_E MI-_E V_E MI_E MI-_E V_E MI_E MI-_E V_E MI_E MI-_E VREG_E.uF.uF GN XTL_E.K R R.K Y MHz _E GN LK_E VREG_E VREG_E XTL_E pf R.K(%) R R V_E V_E _E SWREG_E V_E RXTL E RX_SELRGV_E V_V_E RX_TXLY_E RX_N_E RX_N_E RX_LK_E INT_E V_V_E TXLK_E TX_E TX_E V_E LE E LE E PME_E LE_RXLY_E MIO_E M_E PHYRST_E V_E TXTL_E TX_E TX_E.uF U ST OUT J GN R R.K R S.nF XR V R K % uf K.K(N).uF.uF uf(xr) LE E LE E LE_RXLY_E.uF.uF.uF uf(xr) R.uF IN_PSIT.K(N) U-XR U ST OUT J GN U-XR.uF.uF.uF R.K %.uf uf(xr).uf LE E R.uF R R N R R.uF LE (g) LE (y) LE E Reserve for.v RGMII power (If M support.v RGMII) J HEER V_E T_SSOR_E R K/N PS-V uf(xr).uf OL.uH OU GN MT LX N F SOT- Vout=.(Rtop/Rbottom) SS O Vout =. x ( R/R) Imax = R K % R M % uf(xr) VV.uF VV.uF U IN OUT FLG ON/OFF GN PWG- R K nf USVUS_E NP uf/v US-M_E US-P_E US. HOST- P J US--R VUS M P GN S S VV.uF U IN OUT FLG ON/OFF GN PWG- R K nf NP uf/v US-P_E US-M_E MIRO US J VUS - GN GN nc nc micro US TYPE opyright, PINE LUSTER OR Size ocument Number Rev PHY. Thursday, ecember, ate: Sheet of

8 JU _F P_F URT_TX_F S_F TXTL_F P_F RX_N_F M_F P_F P_F RX_N_F URT_RX_F.uF ONN SOKET x/sm KEY_F PL_F P_F RX_N_F P_F SL_F LK_N_F MIO_F TX_F TX_F TX_F US-P_F US-M_F PWR_ON_F VV VV USVUS_F USVUS_F USVUS_F T_SSOR_F V_F V_F USVUS_F R Place filter network close to RX_LK. VV VV VV uf uf R.uF R R J HEER X LE (g) R R R R R pf-n Note : The Trace length from, to Pin,(VREG) must be within. cm. The trace width from V to Pin, should>mils V_F RTL: =uf(xr) RTLE: =./uf(xr) VREG MI_F MI-_F MI_F MI-_F MI_F MI-_F MI_F MI-_F Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only).uf.uf V_V_F PHY only for RTLE pf.k R R.K Y MHz.K R R.K R.K XTL_F pf R.K V_F V_F R.K(%) R R onnect SWREG to V_F to enable Switching regulator or connect SWREG to GN to disable Switching regulator. Enable/isable SWREG VV.uF VV.uF For wake on LN function, please keep PHYRST pin to high. VOUT=.*(R/R) VOUT=.*(R/R) R S.nF XR V RTL: L=.uH RTLE: L=./.uH RTL:= uf(xr) RTLE:=./uF(XR) L.uH@ _F R for RTL R for RTLE V_V_F R,R: onfig for all capability R,R: PHY ddress=(rtl) R,R,R: PHY ddress=(rtle) R,R: Without TX/RX elay onfiguration Setting U ST OUT J GN U ST OUT J GN R.K R R.K R.K R K %.V Power V_F V_F./.V/./.V RGMII Power uf uf(xr).k(n) uf(xr) uf(xr) uf(xr) PHY_V_F.uF.uF.uF R.K R V_F.uF VV.uF IN_PSIT.K(N) U-XR U ST OUT J GN VOUT=.*(R/R) U-XR.uF.uF.K % R.uF.uF uf(xr).uf uf(xr).uf.uf.uf.uf R for EMI Note : The Trace length between L and PHY's Pin must be within. cm. and to L must be within.cm. V_F V_F V_V_F R R for.v RGMII I R for.v RGMII (From.-.V LO) R for./.v RGMII (RTLE-VL only) PHY_V/_F R R R R N N.uF R R LE (g) LE (y) V_F PHY_V_F PHY_V/_F K % R R.K R R.K %.K/N R.K(N) R K % R TXLK_F RX_N_F TX_F RXTL_N_F RX_LK_N_F US-P_F US-M_F HGLE_F _F RX_N_F RX_N_F RX_N_F RX_N_F RXTL_N_F LK_N_F RX_LK_N_F VV HGLE_F PWR_ON_F P_F URT_TX_F P_F P_F VV SL_F R R PL_F RX_N_F RX_N_F RX_TXLY_F RX_SELRGV_F RXTL F LK_F RX_LK_F PL_F _F P_F KEY_F URT_RX_F P_F P_F S_F MI_F MI-_F V_F MI_F MI-_F V_F MI_F MI-_F V_F MI_F MI-_F VREG_F MI[] MI[]- V MI[] MI[]- V MI[] MI[]- V MI[] MI[]- N GN XTL_F _F GN LK_F VREG_F VREG_F V_F V_F _F SWREG_F V_F GN(EP) GN LK VREG VREG KXTL KXTL V V SWREG V RTL RTLE RXTL/PHY RX/SELRGV V RX/TXLY RX/N RX/N RX INT V TX TX TX RXTL F RX_SELRGV_F V_V_F RX_TXLY_F RX_N_F RX_N_F RX_LK_F INT_F V_V_F TXLK_F TX_F TX_F U V LE/PHY LE/PHY PME LE_RXLY MIO M PHYRST V TXTL TX TX V_F LE F LE F PME_F LE_RXLY_F MIO_F M_F PHYRST_F V_F TXTL_F TX_F TX_F R K % K.uF LE F LE F LE_RXLY_F.uF LE F.uF LE F J HEER V_F T_SSOR_F R K/N PS-V uf(xr).uf OL.uH OU GN MT LX N F SOT- Vout=.(Rtop/Rbottom) SS O Vout =. x ( R/R) Imax = R K % R M % uf(xr) VV.uF VV.uF U IN OUT FLG ON/OFF GN PWG- R K Reserve for.v RGMII power (If M support.v RGMII) VV USVUS_F.uF nf US. HOST- P J U NP US--R uf/v IN OUT US-M_F VUS FLG M ON/OFF GN US-P_F P PWG- GN S S R K nf NP uf/v US-P_F US-M_F MIRO US J VUS - GN GN nc nc micro US TYPE opyright, PINE LUSTER OR Size ocument Number Rev PHY. Thursday, ecember, ate: Sheet of

9 JU _G ONN SOKET x/sm KEY_G PL_G P_G RX_N_G P_G SL_G LK_N_G MIO_G TX_G TX_G TX_G US-P_G US-M_G PWR_ON_G VV VV USVUS_G USVUS_G USVUS_G T_SSOR_G V_G V_G USVUS_G Place filter network close to RX_LK. VV VV VV uf J HEER X LE (g) pf-n Note : The Trace length from, to Pin,(VREG) must be within. cm. The trace width from V to Pin, should>mils V_G RTL: =uf(xr) RTLE: =./uf(xr) VREG MI_G MI-_G MI_G MI-_G MI_G MI-_G MI_G MI-_G Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only).uf.uf V_V_G PHY only for RTLE pf.k R R.K Y MHz.K R R.K R.K XTL_G pf V_G V_G R.K(%) R R onnect SWREG to V_F to enable Switching regulator or connect SWREG to GN to disable Switching regulator. Enable/isable SWREG VV VV For wake on LN function, please keep PHYRST pin to high. VOUT=.*(R/R) VOUT=.*(R/R) RTL: L=.uH RTLE: L=./.uH RTL:= uf(xr) RTLE:=./uF(XR) L.uH@ _G R.K R for RTL R for RTLE V_V_G R,R: onfig for all capability R,R: PHY ddress=(rtl) R,R,R: PHY ddress=(rtle) R,R: Without TX/RX elay onfiguration Setting U ST OUT J GN R.K R R.K.K(N) R.K R K %.V Power V_G V_G./.V/./.V RGMII Power uf uf(xr) uf(xr).uf.uf PHY_V_G V_G uf(xr) R.K R.uF VV.uF.K(N) U-XR U ST OUT J GN VOUT=.*(R/R).uF R for EMI Note : The Trace length between L and PHY's Pin must be within. cm. and to L must be within.cm. V_G V_G V_V_G.uF.uF R R for.v RGMII I R for.v RGMII (From.-.V LO) R for./.v RGMII (RTLE-VL only) uf(xr) R PHY_V/_G uf(xr) N.uF V_G PHY_V_G PHY_V/_G K % R P_G URT_TX_G S_G TXTL_G P_G RX_N_G M_G P_G P_G RX_N_G URT_RX_G TXLK_G RX_N_G TX_G uf R R R R.K.uF U ST OUT J GN R.K(N) K % R RXTL_N_G RX_LK_N_G US-P_G US-M_G HGLE_G _G.uF R RX_N_G RX_N_G RX_N_G RX_N_G RXTL_N_G LK_N_G RX_LK_N_G R VV HGLE_G PWR_ON_G P_G URT_TX_G P_G P_G VV SL_G.uF R R R R R R PL_G RX_N_G RX_N_G RX_TXLY_G RX_SELRGV_G RXTL G LK_G RX_LK_G PL_G _G P_G KEY_G URT_RX_G P_G P_G S_G MI_G MI-_G V_G MI_G MI-_G V_G MI_G MI-_G V_G MI_G MI-_G VREG_G MI[] MI[]- V MI[] MI[]- V MI[] MI[]- V MI[] MI[]- N GN XTL_G _G GN LK_G VREG_G VREG_G V_G V_G _G SWREG_G V_G GN(EP) GN LK VREG VREG KXTL KXTL V V SWREG V RTL RTLE RXTL/PHY RX/SELRGV V RX/TXLY RX/N RX/N RX INT V TX TX TX RXTL G RX_SELRGV_G V_V_G RX_TXLY_G RX_N_G RX_N_G RX_LK_G INT_G V_V_G TXLK_G TX_G TX_G U V LE/PHY LE/PHY PME LE_RXLY MIO M PHYRST V TXTL TX TX V_G LE G LE G PME_G LE_RXLY_G MIO_G M_G PHYRST_G V_G TXTL_G TX_G TX_G.uF R R S.nF XR V R.K % R K %.K/N K uf(xr).uf LE G LE G LE_RXLY_G.uF.uF IN_PSIT U-XR.uF.uF R.K %.uf.uf LE G R.uF.uF R N R R.uF R R LE (g) LE (y) LE G Reserve for.v RGMII power (If M support.v RGMII) J HEER V_G T_SSOR_G R K/N PS-V uf(xr).uf OL.uH OU GN MT LX N F SOT- Vout=.(Rtop/Rbottom) SS Vout =. x ( R/R) Imax = O R K % R M % uf(xr) VV.uF VV.uF U IN OUT FLG ON/OFF GN PWG- R K nf USVUS_G NP uf/v US-M_G US-P_G US. HOST- P J US--R VUS M P GN S S VV.uF U IN OUT FLG ON/OFF GN PWG- R K nf NP uf/v US-P_G US-M_G MIRO US J VUS - GN GN nc nc micro US TYPE opyright, PINE LUSTER OR Size ocument Number Rev PHY. Thursday, ecember, ate: Sheet of

RTL8211DG-VB/8211EG-VB Schematic

RTL8211DG-VB/8211EG-VB Schematic RTL8G-V/8EG-V Schematic REV..8 Page Index. Page. PHY. MI. M. Power. History RTL8G/8EG Size ocument Number Rev.8 TITLE PGE ate: Sheet of External clock and rystal RTL8G/8EG GMII/RGMII Interface LK_M ENSWREG