Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0

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1 Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of

2 ,, /ISGPIOSTP TS# T0 URTTX URTRX S SL LE/LE/LEMOE0 LEK/LE/LEMOE RESET RESET TEST XTL XTL V U M V 0 /ISGPIOSTP 0 V V 0 N N URTTX URTRX V S SL LE/LE/LEMOE[0] LEK/LE/LEMOE[] VIO 0 RESET# VPLL RSV VSSPLL XTL XTL V GN V EP R NI_K R NI_K R NI_K /0FRQ0 /0FRQ /0FRQ RTT RTT TEST MI_REF /0FRQ0 0 /0FRQ 0 /0FRQ 00 V 0/ISSN RSV /MMOE0 /MMOE /0MOE0 /0MOE 0 V /MMOE0 /MMOE /0MOE0 /0MOE P0MIP P0MIN R.K % P0MIP P0MIN /FWMOE0 /FWMOE P0MIP P0MIN /S0MOE 0/ENEEPROM P0MIP P0MIN 0 LE0/GPIO0/ENLT_P0P LE/GPIO/ENLINKTRN LE/GPIO/ENS0_TEST LE/GPIO/ENS_TEST LE/GPIO/IS_S LE/ENGREEN TRIGUTOL RTLM RTT RTT TEST MI_REF GN V V P0MIP P0MIN GN P0MIP P0MIN V V P0MIP P0MIN GN GN P0MIP P0MIN V V V PMIP PMIN GN GN PMIP PMIN V V PMIP PMIN GN PMIP PMIN V V V 0 /FWMOE0 /FWMOE V 0/ENEEPROM 0 V 0 V LE0/GPIO0/ENLT_P0P LE/GPIO/ENLINKTRN V 0 LE/GPIO LE/GPIO LE/GPIO/IS_S LE/ENGREEN TRIGUTOL NT_TERML# V S# V OE#/LESPSEL 0 WE#/FSTLO V INT0 PWRMON N SRXP SRXN SV STXP STXN 0 SGN SV SGN STXN0 STXP0 SV LKIN SGN 0 SREGO NT_TERML#/T S0# OE#/LESPSEL INT0 PWRMON SRXP SRXN STXP STXN LKIN K R SV V V PWRMON 0.uF c00 SREGO 0uF TEST TS# T0 /ISGPIOSTP /0FRQ0 /0FRQ /0FRQ 0/ISSN /MMOE0 /MMOE /0MOE0 /0MOE /FWMOE0 /FWMOE /S0MOE 0/ENEEPROM XTL pf 0 LE0/GPIO0/ENLT_P0P LE/GPIO/ENLINKTRN LE/GPIO/ENS0_TEST LE/GPIO/ENS_TEST LE/GPIO/IS_S LE/ENGREEN NT_TERML#/T S0# OE#/LESPSEL INT0 TRIGUTOL LE/LE/LEMOE0 LEK/LE/LEMOE S SL URTRX URTTX lk R NI_K RYSTL Y TS# T0 URTRX URTTX XTL pf /ISGPIOSTP, /0FRQ0, /0FRQ, /0FRQ, 0/ISSN, /MMOE0 /MMOE /0MOE0, /0MOE, /FWMOE0, /FWMOE, /S0MOE, 0/ENEEPROM, 0 LE0/GPIO0/ENLT_P0P LE/GPIO/ENLINKTRN LE/GPIO/ENS0_TEST LE/GPIO/ENS_TEST, LE/GPIO/IS_S, LE/ENGREEN NT_TERML#/T, S0# OE#/LESPSEL,, INT0 TRIGUTOL LE/LE/LEMOE0 LEK/LE/LEMOE S SL 0uF (t) V 0 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF c00 c00 c00 c00 c00 c00 V 0uF (t) 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF c00 c00 c00 c00 c00 c00 c00 SV 0 0uF (t) 0.uF 0.uF 0.uF c00 c00 c00 Mdi P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN Serdes SRXP SRXN STXP STXN SRXP SRXN STXP STXN V V 0uF (t) 0 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF c00 c00 c00 c00 c00 c00 c00 0uF (t) 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF c00 c00 c00 c00 c00 c00 c00 Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev M.0 ate: Tuesday, November, 00 Sheet of

3 0 0.0uF c00 P0MIN TT P0MIP X T+ T T- TX+ T TX- P0MI- MT P0MI+ R r00 000pF/Kv c0 P0MI- P0MI+ P0MI- P0MI- P0MI+ P0MI+ P0MI- P0MI+ PHJ 0 P PHJ-SHIE N N 0.0uF c00 P0MIN TT P0MIP N R+ T R- N RX+ T 0 RX- P0MI- MT P0MI+ R r00 000pF/Kv c0 000pF/Kv c0 H0 X 0.0uF c00 0.0uF c00 P0MIN TT P0MIP P0MIN TT P0MIP TX+ P0MI- MT P0MI+ P0MI- MT P0MI+ T+ T T- N N R+ T R- T TX- N N RX+ T 0 RX- R0 r00 R r00 P0MI- MT P0MI+ P0MI- MT P0MI+ R 0 r00 R 0 r00 R 0 r00 R 0 r00 H0 Mdi P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN P0MIP P0MIN Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev Rj.0 ate: Tuesday, November, 00 Sheet of

4 V_Fiber_TX SFP_T+ SFP_T- R 0 % R 0 % R 0 % FX_T+ FX_T- R 0 % V_Fiber_RX R 0 % R 0 % FX_TXOP FX_TXON R0 0 % R 0 % FX_RXIN V_Fiber_TX 0.uF FX_TXOP FX_TXON RX_S FX_RXIN FX_RXIP V_Fiber_RX 0.uF U Tx_GN Tx+ Tx- Tx_V Rx_V RxS Rx- Rx+ Rx_GN Fiber_Transceiver Serdes SRXP SRXN STXP STXN LE/GPIO/ENS_TEST LE/GPIO/IS_S R R SRXP SRXN STXP STXN LE/GPIO/ENS_TEST, LE/GPIO/IS_S, K r00 K r00 SRXN SRXP 00nF FX_R- 0 00nF FX_R+ Near the transceiver R 0 % FX_RXIP R 0 % RX_S R R NI NI V_Fiber_RX R K R0 NI X_S R NI R NI_.K Q NI_N0 V V L E (0) V V V L E (0) L E (0) V_Fiber_RX + 0uF (0) 0.uF V_Fiber_TX L E (0) + 0.uF 0uF (0) R R.K.K r00 R.K R.K R.K F_MO F_MO F_MO0 LOS R R NI_.K 0 TX_FULT SFP_R- SFP_R+ SFP_T+ SFP_T- TX_IS U VEET TX_FULT TX_ISLE MO_EF MO_EF MO_EF0 RTE_SEL LOS VEER 0 VEER VEER R- R+ VEER VR VT VEET T+ T- 0 VEET GI_ U 0 N0 N GN_E GN_E GN_E GN_E GN_E GI_ N N N GN_E N N N N N N TXPWR_IS V R 0 R K R0 0 R 0 R K Q R 0 N0 U S S S G EM V_Fiber_TX + 0uF (0) 0.uF STXP STXN 00nF 00nF LE/GPIO/IS_S LE/GPIO/ENS_TEST 0 R 0 R TX_IS LOS Near the I SRXN SRXP 0 00nF 00nF SFP_R- SFP_R+ LE/GPIO/IS_S LE/GPIO/ENS_TEST R 0 R 0 TXPWR_IS X_S Near the transceiver L NI_E (0) L NI_E (0) Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev ustom Fiber.0 ate: Friday, ecember, 00 Sheet of

5 V /ISGPIOSTP R.K If LE mode is serial mode(ledspsel=0), When ISGPIOSTP=0: GPIO[:0] pins can be used as strapping pin When ISGPIOSTP=: GPIO[:0] pins can not be used as strapping pin. 0/ENEEPROM R V NI_.K V OE#/LESPSEL R NI_.K Serial or parallel LE mode selection. 0:serial :parallel /0FRQ0 /0FRQ /0FRQ 0FRQ[:0] 000:.M 00:.M 00:.M 0: M 00: 0.M Other: reserved 0/ISSN /S0MOE R0 V R R NI_.K R NI_.K NI_.K V NI_.K V R NI_.K /0MOE0 /0MOE R0 R NI_.K 0 mode. NI_.K 00: 0+flash mode, for web smart. (default) 0: 0+P_EEPROM mode, program is in EEPROM. 0: no 0 mode. : Reserved /FWMOE0 R /FWMOE R NI_.K Switch forward mode. NI_.K 00: store and forward mode (default) 0: modified cut through mode 0: smart pass through mode : pass through mode V NT_TERML#/T LEK/LE/LEMOE R LE/LE/LEMOE0 R R R.K NI_.K V V NI_.K V NI_.K LE Mode Select. These pins are used to configure LE operation mode. The state of this pin is latched during power-up or reset. There are four LE display modes: : Mode 0. : Mode. : Mode. V 0: Mode. /ISGPIOSTP /0FRQ0 /0FRQ /0FRQ 0/ISSN /MMOE0 /MMOE /0MOE0 /0MOE /FWMOE0 /FWMOE /S0MOE 0/ENEEPROM LE0/GPIO0/ENLT_P0P LE/GPIO/ENLINKTRN LE/GPIO/ENS0_TEST LE/GPIO/ENS_TEST LE/GPIO/IS_S LE/ENGREEN OE#/LESPSEL NT_TERML#/T LE/LE/LEMOE0 LEK/LE/LEMOE Pad pull high default POWER LE:S_link/ct LE:UP LE0:UTP0_SP000 LE:UTP0_Link/ct LE:UTP0_SP00 LE:LinkTran LE:S_OMLOOP LE:N /ISGPIOSTP, /0FRQ0, /0FRQ, /0FRQ, 0/ISSN, /MMOE0, /MMOE, /0MOE0, /0MOE, /FWMOE0, /FWMOE, /S0MOE, 0/ENEEPROM, LE0/GPIO0/ENLT_P0P LE/GPIO/ENLINKTRN LE/GPIO/ENS0_TEST LE/GPIO/ENS_TEST, LE/GPIO/IS_S, LE/ENGREEN OE#/LESPSEL,, NT_TERML#/T, LE/LE/LEMOE0 LEK/LE/LEMOE LE0/GPIO0/ENLT_P0P R LE/GPIO/ENLINKTRN R LE/GPIO/ENS0_TEST R V NI_.K V NI_.K V NI_.K LE/GPIO/ENS_TEST R LE/GPIO/IS_S LE/ENGREEN R0 R V NI_.K V NI_.K V NI_.K LE/LE/LEMOE0 SLE SLE SLE SLE U Q Q Q Q GN 0.uF V QH QG QF QE 0 LER LK L(SM) SLE0 SLE SLE SLE LEK/LE/LEMOE RESET,, SLE SLE LE LEX (IP) LE 0 R 0 R 0 R V SLE0 0 R GPIOS & /T Select SLE 0 R V R IP R R R 0 R R 0/ISSN NI_.KLE/GPIO/IS_S NI_.K NI_K LE/GPIO/ENS_TEST NI_K LE/GPIO/ENS0_TEST NI_K LE/GPIO/ENLINKTRN NI_K LE0/GPIO0/ENLT_P0P R0 R R R NI_0K NI_0K NI_0K NI_0K SLE 0 R LEX (IP) LE SLE 0 R R.K NT_TERML#/T SLE 0 R IPX enter M or terminal M selection. 0= terminal M. (default) = enter M. SLE 0 R0 LEX (IP) 管理机独有 Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev Strapping&LE.0 ate: Tuesday, November, 00 Sheet of

6 EEPROM & SMI T XPIN INT0 INT0 V S SL R.K pf pf T XPIN Mark on board M GN MIO V S SL S SL TRIGUTOL V R 0K TRIGUTOL T XPIN 0uF Mark on board R.K U V V TRIGUTOL Trigger OM auto loop back test progress for center M.(input pin) 0: disable auto loop back : trigger auto loop back 0 GN V SLK S L SOKET U V SL S R 0K R NI_0K Mark on board V GN Mark on board System Reset V URT 0 GN L SOP V SLK S SL S,, RESET R K RESET T XPIN 0uF N URTTX URTRX + 0.uF + 0.uF U T in 0 T in R out R out MX V URTTX URTRX URTTX URTRX (SM) Vcc Reserved test. U P 0.uF 0.uF PHJ-SHIE P_TX RESET V+ GN RESET V PHJ + 0 P_RX R 0.uF 00K MX0S V- SOT PU_TX=>P_RX P_RX T out T out PU_RX<=P_TX P_TX R in R in + 0 Realtek Semiconductor orp. RTL(M)_FHG_V.0 GN V 0.uF Size ocument Number Rev SMI.0 ate: Tuesday, November, 00 Sheet of

7 NOTE: FLSH address space = 0x00000 ~ 0xffff KXbit SRM address space = 0x0000 ~ 0xfff KXbit U0 V /0FRQ0 /0FRQ /0MOE0 /0MOE /FWMOE0 /FWMOE /S0MOE 0/ENEEPROM 0 SF# R0 0 Mark on the board: SRM S0# 0 U 0 0 GN ISLVL U Y Y GN 00 0.u V WE OE 0 E 0 V Y 0 Y V /0FRQ,, /MMOE /MMOE0 OE#/LESPSEL 0/ISSN V SS# R0.k V SS#$ 0.uF R0 0 R0 NI_.k /ISGPIOSTP /0FRQ0 /0FRQ /0FRQ 0/ISSN /MMOE0 T0 R NI_0 NT_TERML#/T R00 RESET RESET #/ V R0.k R0 0 /MMOE /0MOE0 /0MOE /FWMOE0 /FWMOE #/ R0 NI_.k V NI_0 Mark on the board: FLSH WE RST N N RY/Y MXLV00/00 YTE GN Q/- Q Q Q Q Q 0 Q Q V Q Q Q0 Q Q Q Q 0 Q0 OE GN E 0 R.k 0/ENEEPROM 0 0 OE#/LESPSEL /S0MOE V SF# /ISGPIOSTP /0FRQ0 /0FRQ /0FRQ 0/ISSN /MMOE0 /MMOE /0MOE0 /0MOE /FWMOE0 /FWMOE /S0MOE 0/ENEEPROM S0# OE#/LESPSEL 0.u R0.k V 0uF (0) /ISGPIOSTP, /0FRQ0, /0FRQ, /0FRQ, 0/ISSN, /MMOE0 /MMOE /0MOE0, /0MOE, /FWMOE0, /FWMOE, /S0MOE, 0/ENEEPROM, S0# OE#/LESPSEL,, For internal tsest! SS#$ R0 0 SS# TS# S0# R0 0 SF# T0 TS# 0 R SS# NT_TERML#/T Realtek Semiconductor orp. RTL(M)_FHG_V.0 TS# T0 NT_TERML#/T, Size ocument Number Rev Sram&Flash.0 ate: Tuesday, November, 00 Sheet of

8 U U Vin Vout dj - V 0uF (0) + V + uf (0) N PV uF 000pF c00 V _JK PV V R NI_0 V.uF(00) U N EN VIN RT00 GN F/OUT GN LX L GN.uH GN 0 V pf R00K % R 00K % GN 0uF(0) PV R NI_0 R 00 r00 V V.uF(00) U N EN VIN RT00 GN F/OUT GN LX GN L.uH V pf R 0K % R K % 0uF(0) ZXV.. R 0 r00 R0 0 r00 R NI_0K PWRMON PWRMON For Test V L V HOKE (0) H SV V V H H H 000pf 000pf 000pf HOKE (0) HOKE (0) 000pf 0 000pf 000pf L0 L 000pf 000pf 000pf 000pf 000pf 000pf Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev Power.0 ate: Tuesday, November, 00 Sheet of

Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.

Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds. lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January,