PTN3356 Evaluation and Applicaiton Board Rev. 0.10
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1 E PTN Evaluation and pplicaiton oard Rev. 0.0 REVISION STORY : June 0, 0 - ase on PTN_ONLY_REV.SN 0. July, 0 - OM changes due to long lead time items, LEs 0. July, 0 - hange US J 0. July, 0 - hange U to Johnstech ROL 00 Series - hange U to TI part 0. July, 0 - hange 0,, singal names - Swap U, to un-twist H/V sync - change U to SSOP - dd TP, TP 0. July, 0 - Remove 0. July, 0 - Remove U and caps around it. 0. July, 0 - dd caps for P lanes 0. July, 0 - orrect P signal name 0.0 ug. 0, 0 - U library is wrong - Re-work U connection Page# Page Index PTN VG P & Power JTG & ONFIG NXP Semiconductors E. Plumeria rive, San Jose, INEX ocument Name PTN PVG Size ocument Number Rev 0.0 ate: Monday, ugust 0, 0 Sheet of E
2 J V_I V_V L F.uF_0V V_I V_PWR V JP HEER 0.uF TO MESURE I POWER PPLY EXTERNL PWR TO PIN NORML OP: PIN-PIN V_I TP_RE V_I TP V_V TP_RE V_V REMOVE L, PLE URRENT METER ROSS V_I N V_V 0.uF TP 0.0uF PLE NER PIN V_V V_V TP_RE TP V_V V_V 0.uF L F.uF_0V VUK_V PLE NER PIN V_V 0 0.0uF SH[] REMOVE L, PLE URRENT METER ROSS L TESTMOE PTN.uF U uf 0.uF.uH L P SWOUT SWOUT VUK_V V_V 0 PV TESTMOE TESTMOE V V_ OS_OUT OS_OUT OS_IN OS_IN PLE NER PIN 0.uF Y MHz PLE NER PIN 0.uF Y MHz-pF pf J ON pf ON OS_OUT OS_IN V_PWR V_PWR TP_RE TP SH[] SH[] SH[] SH[] SH[] SH[] SH[] SH[] SH[] SH[] SH[] SH[] UX_P UX_N ML_P ML_N HP FG_TO FG_TK MS_SL/TI ML_P ML_N HP UX_P UX_N FG_TO FG_TK MS_SL/TI OULE FOOTPRINT FOR U HVQFN & SOKET V_V 0.uF V_NW UX_P UX_N V_P ML_P ML_N PTN_SKT VE_IO 0 HP HP FG_SL/TI FG/TK FG_TK FG_TO _SL RE RSET GRN LU HSYN VSYN _S R.0K % V_V PLE NER PIN RE SH[] GRN SH[] LU SH[] HSYN SH[] VSYN SH[] _S SH[,] FG/TO FG_S/TMS _SL RE RSET GRN LU HSYN VSYN _S 0 VE_IO 0 0.uF SW J0 ON PLE NER PIN uf _SL _SL SH[,] P-SPST-MOM RST SW INTERNL PULL UP MS_SL/TI HP PTN PVG emo oard with Socket Size ocument Number Rev 0. ate: Monday, ugust 0, 0 Sheet of
3 VG PIN SSIGNMENT ON P (OTTOM SIE): VUS_ K ROW (G_RTN) (G) (HS) (SL) FRONT ROW (R_RTN) (R) (S) (_RTN) () (VS) 0 V_ONN_V _PU T PESV0UT PESV0UT VUS_ V_ONN_V J 0uF_V SH[] SH[] SH[] SH[] SH[] RE GRN LU HSYN VSYN R R R R R.K R.K R _PU L Ohm 00m HSYN_VG VSYN_VG.pF.pF L Ohm 00m.pF.pF L Ohm 00m.pF.pF HS_V VS_V RE_VG GRN_VG PESV0UT LU_VG T 0pF 0pF 0 RE_RTN N RE GREEN_RTN S GREEN LUE_RTN HS LUE V VS N SL VG_ONN SH[,] SH[,] _S _SL _S _SL OPTION ESIGN: Install U to support V H/V for legacy projector and RTs. VUS_ P P P P P P P P P P PLESE TEST P IN THE MILE OF THE TRE P P P P 0.uF HSYN_VG HS_V VSYN_VG LVGP U VS_V HSYN_VG VSYN_VG R 0 R 0 HS_V VS_V LVGP U PTN PVG emo oard Size ocument Number Rev 0. ate: Monday, ugust 0, 0 Sheet of
4 P ONN SINK J LNEn LNEp LNEn LNEp LNEn LNEp 0 LNE0n LNE0p ONFIG ONFIG UXp G_ UXn G_ HP G_ RTN G_ P_PWR 0 MLN MLP ML0N ML0P UXP UXN HP ML_N ML_P 0.uF UX_P UX_N ML_N ML_P UX_P UX_N HP SH[] SH[] SH[] SH[] SH[] SH[] SH[] ONLY WITH P.0 LE P_PWR V_US V_F JP- to J-: P_PWR JP- to JP-: US JP- to JP-: EXT PWR V_EXT V P-REEPTLE HP pull-down is integrated into silicon (00K) R M R0 M J ON HEER JP L F 0uF_V uf_v V TP_LK P_PWR V_US V_EXT P_PWR V_US V_EXT V V P_PWR P_PWR V ON: LE OFF JUMPER ON TO TURN ON LE JUMPER OFF TO MESURE POWER ONSUMPTION JP HEER VUS_ V_US R 0 TP TP_YEL TP TP_ORNGE TP TP_RE TP_RE VUK_V PWR_LE PWR ON HP LE ON HP_ON VUS_LE US V USV_LE US V VUK_V TP 0 RE_LE TP_WTE 0.uF 0.uF 0.uF 0.uF 0.uF 0 uf_0v 0.uF 0.0uF 00K R R M R M TP_LK TP_LK TP_LK R 0 R 0 TP TP TP TP_LK TP TP_LK TP TP_LK TP MER_LE TP0 GRN_LE TP_LK TP TP_LK TP MER_LE.uF_0V R 0 TP VUS_ VUS_ J US Micro Receptacle VUS MNT - MNT MNT I MNT VUS_.uF_0V 0 0.uF TLV-YR VIN VOUT VOUT U V_US VUS_ VUS_ TP mtg-hole mtg-hole mtg-hole mtg-hole MTG MTG MTG MTG US.uF_0V 0.uF TP_ORNGE PTN PVG emo oard Size ocument Number Rev 0.0 ate: Monday, ugust 0, 0 Sheet of
5 V V V V FG/TK HEER R 0K FG_TK R0 0K V FG_TK SH[] TESTMOE HEER JP R 0K R 0K R 0K R 0K TESTMOE TESTMOE = PIN -, FG[:] = JTG PINS = PIN -, FG[:] = ONFIG PINS, I RESS = 0h OPEN: FG[:] = ONFIG PINS, I RESS = 0h SH[] JP JUMPER -, GH, MHZ XTL IS USE OPEN: MHZ XTL IS USE JUMPER -, W, MHZ XTL IS USE FG-MS_SL/TI FG- HEER HEER JP JP MS_SL/TI MS_SL/TI SH[,] FG FG: : OMPLINT HP EHVIOR, MS US IS USE 0: NON-OMPLINT HP EHVIOR 0: NON-OMPLINT HP EHVIOR 00: OMPLINT HP EHVIOR SH[,] FG-SPRE HEER JP0 R 0K R 0K R 0K R 0K FG_TO FG_TO SH[] SH[] FOR PTN WITH FLSH ONLY SH[,] SH[,] MS_SL/TI MS_SL/TI J MS_I FG_TK FG_TO MS_SL/TI JTG HEER I IR PIN OUT 00pF JTG J HEER x V 0 R K SH[,] SH[,] _SL _S _SL _S J _I MOUNT J ON THE TOP SIE WITH RIGHT NGLE ONNETOR HEER I IR PIN OUT PTN ONFIG N JTG Size ocument Number Rev 0. ate: Monday, ugust 0, 0 Sheet of
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SI_x_NLG_H_[:] P P SI_x_SPI_MISO SI_x_SPI_MOSI SI_x_SPI_LK SI_x_SPI_S FE/SI_OM_ FE/SI_OM_ FE/SI_OM_ FE/SI_OM_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_
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V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V
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THIS RWING IS THE PROPERTY OF NLOG EVIES IN. IT IS NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR USE IN FURNISHING INFORMTION TO OTHERS, OR FOR NY OTHER PURPOSE ETRIMENTL TO THE INTERESTS OF NLOG EVIES.
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PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE - Power us and Switches
More informationPOWER Size Document Number Rev Date: Friday, December 13, 2002
R0 [ /W 0 0.00uF/00V - D0 KP0M L0 L D0 N 0 00uF/00V 0 0.uF R0 M [ /W R0 M [ /W R0 M [ /W R0 M [ /W 0 0.00uF/KV D0 PS0R 0 0uF R0 00K [ W D0 FR0 R0 0 [ /W O O T0 O,, POWER X'FMR 0, D0 DQ0 R [ /W 0.00uF/00V
More informationNOTE: please place R8 close to J1
Sheets, & /M_RESET PST T T0 +.V_MU R 0K /M_RESET PST T T0 +.V_MU 0.uF NOTE: please place J close to the edge of the P so that the debug cable is clear of the P when attached to the board J 0 0 M Header
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INPUT V INPUT V PGE PGE OMMUNITIONS OMMUNITIONS PGE INPUT V INPUT V PGE INPUT V INPUT V PGE POWER ISTRIUTION POWER ISTRIUTION PGE INPUT V INPUT V PGE LOK ISTRIUTION LOK ISTRIUTION PGE USF USF.prj 0th ve.
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Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM
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00 Wesbrook Mall Vancouver,.., anada VT - 0 -Nov-000 :: H:\0\sheet_.SH wg. No.: ate: File: Revision: Sheet of Time: 0 hannel V/F onverter wg List: rawn y: P. ennett isk: 0 0 0 J IN+ IN- IN+ IN- IN+ IN-
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PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.
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Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT
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THIS RWING IS THE PROPERTY OF NLOG EVIES IN. IT IS NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR USE IN FURNISHING INFORMTION TO OTHERS, OR FOR NY OTHER PURPOSE ETRIMTL TO THE INTERESTS OF NLOG EVIES.
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ON V_US M P GN SH SH US _WURTH_ R ZERO.JTN R US US R n N.K_P.KLTN Q U_, V_N TP SISTETN INRUSH IRUIT x Header_KN n N R ZERO.JTN ZERO.JTN Notes: o not install R if URT Vcc_Reg is connected to V (Vcc_US),.Uf,.V,
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R 0K0 RST U S_ PF/0V PF/0V 0FS FS T T 0SLK N SOT N SOT Y mhz U LS0 debug port 0 do not stuff R WR S PS X/Y IN/IN IR 0IR MO J R M R 0K0 R0 K00 R 0K0 dsck dr dsi dso / G 0 U LS0 R 0K0 SI_RX SI_TX SI_LK TFS
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THI RWING I THE PROPERTY OF NLOG EVIE IN. IT I NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR UE IN FURNIHING INFORMTION TO OTHER, OR FOR NY OTHER PURPOE ETRIMTL TO THE INTERET OF NLOG EVIE. THE EQUIPMT
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