Power-Conscious Interconnect Buffer Optimization with Improved Modeling of Driver MOSFET and Its Implications to Bulk and SOI CMOS Technology

Transcription

1 ower-onscious Inerconnec Buffer Oimizaion wih Imroved Modeling of Driver MOSFE and Is Imlicaions o Bul and SOI MOS echnology Koichi Nose and aayasu Saurai Insiue of Indusrial Science, Universiy of oyo, 4-6- Komaba, Meguro-u, oyo, 3-8 Jaan hone: , FAX: , {nose, saurai}@iis.u-oyo.ac.j ABSA losed-form formulas for oimum buffer inserion where he juncion caaciance is aen ino accoun are roosed. In order o use he derived formulas, an aroriae choice of he effecive linear resisance of he driving ransisor is also clarified. Using he roosed formulas, he oimum inerconnec delay and ower comarison beween bul and SOI MOS echnology are discussed. he calculaion resuls show ha boh he oimum delay and ower wih SOI can be reduced by % comared wih he bul MOSFE whose juncion caaciance is assumed o be equal o he gae caaciance. aegories & Subjec / General erms B.7. Inegraed circuis / erformance, design. Inroducion Inerconnec delay oimizaion by buffer inserion is an indisensable echnique for dee submicron VSI's. models for MOSFE's have been used o oimize he buffered inerconnec. As for he resisor, he ransisor has been aroximaed as a linear resisor wihou deailed consideraion on he non-linear feaure of MOS I-V curves. As for he caaciance, he juncion caaciance, J, has ofen been negleced [] or even if J is aen ino accoun, he delay formula including J is no sufficienly accurae. Moreover, he exising heories for buffered inerconnec oimizaion are lacing in he rade-off beween he delay and he ower consumion alhough he ower is one of he mos imoran index in fuure giga-scale inegraion. In order o overcome he shorcomings of he convenional aroach, in his aer, aroximaion of MOSFE as a linear resisor is invesigaed and he delay formula including J is roosed. ermission o mae digial or hard coies of all or ar of his wor for ersonal or classroom use is graned wihou fee rovided ha coies are no made or disribued for rofi or commercial advanage and ha coies bear his noice and he full ciaion on he firs age. o coy oherwise, or reublish, o os on servers or o redisribue o liss, requires rior secific ermission and/or a fee. ISED, Augus -4,, Monerey, alifornia, USA. oyrigh AM //8 $.. J (a wihou buffers (b wih buffers sages Size : h Figure Disribued inerconnec model he aer also gives aenion o he ower consumion inhe oimizaion rocess and derives closed-form formulas for oimum buffer inserion. he resuls have been alied o bul and SOI echnologies and imlicaions of buffered inerconnec on echnologies are discussed.. Analyical Model for Buffer Oimizaion Figure shows a basic configuraion of buffered inerconnec. he inducive effec is negleced in his aer since he effec on oimum buffer insered lines will diminish and become negligible for global inerconnecs in he fuure []. In order o minimize he delay, uniform buffers are insered [3]. he delay formula wihou buffers can be aroximaed as (. Suffix signifies quaniy er uni size or lengh. his exression is newly derived and he relaive error of he delay of ( and he SIE simulaion resuls is shown in able I. he relaive error is wihin 3% when J and wihin 8% when J is equal o or less han, which is he inu caaciance of a ransisor. When he buffers are insered lie in Fig. (b, he oimum size of he buffers and he oimum number of he buffers can be derived analyically as 4

2 able I elaive error of d of ( and SIE simulaion resuls (a J / V IN V X V OU d h h d /.. /.. O O / (b J / / * Errors are in ercen., ( ( + J. (3 h O is he oimum size of he buffers and O is he oimum number of he buffers. is he inerconnec lengh. Subsiuing h O ( and O (3 ino (, he oimum delay ( do can be exressed as do.4. + MOS MOS + J ( when ( when J J MOS. (4 is he ime consan of inerconnec ( and MOS is he ime consan of a buffer ( ( + J which corresonds o he inverer delay wih fanou of. he oimum delay is roorional o a geomeric mean of he Volage V DD V DD / V IN V X / 3/4 V OU ime Figure Signal waveforms when buffers are insered inerconnec delay ( and he gae delay ( MOS. his means ha he delay of oimally buffered inerconnec is aroximaely scaled as s where s is a scaling variable. I is also shown ha he oimal condiion is me when insered buffer delay is aroximaely equal o he inerconnec delay. In order o use he derived formulas, he effecive linear resisance of he uni-sized ransisor ( has o be deermined from device characerisics. Here, an aroriae choice of he effecive consan resisance is o be discussed. he waveform of he inu volage (V IN, driver ouu volage (V X and inerconnec ouu volage (V OU are shown in Fig.. he waveforms can be considered as he ram waveforms and -ower model [4] is used as he drain curren model. In order o derive, one secion of buffered inerconnec is aroximaed by one-se π circui conneced o [], deiced in Fig.3. I and I are he inerconnec resisance and inerconnec caaciance of one secion, resecively. X is he sum of J and I / and OU is he sum of G and I /. he exression for is calculaed firs assuming he following oins and hen evaluaed using rigorous simulaions. (a Fanou is se o, since secions are reeaed. (b V X and V OU are sar o fall a / simulaneously as in Fig.. (c he ime consan of V OU ( OU is wice as large as ha of V X ( X, as in Fig.. (d X OU d + ( + + J + h( h + + J + h + h ( where.377 and.693

3 J I V IN V X V OU G I Q X VDD + IVDD 4. (9 3 VDD + VDD VDD From he viewoin of he drain curren which is exressed as se inu V X X I V OU OU Figure 3 Simle model for deviaion of effecive linear resisance Drain curren : I I DSA 3 Figure 4 Definiion of and 3 X and OU are described as V DS V GS V DD V DD X ( X + OU ( OU ( X + OU + I OU X (6 V X is exressed as he funcion of X. V X X VDD e (7 V X is V DD a / and falls o V DD / a 3/4 as is shown in Fig.. hen, can be derived from Eq.7. / 4 e X (8 (4ln ( X + OU (4ln where ( X + OU. he oal charge which is discharged during / 3/4 is wrien as I β ( V GS VH, ( he oal charge sulied from he inu buffer beween / and 3/ ( Q can be calculaed. Q 3 / 4 β ( VGS VH d / 3V V DD / 4 β ( V / GS VH DD V dvgs DD + + βv DD 3 v v + 4 ( where v V H /V DD., which is he ransisor resisance when V DS V GS V DD (see Fig. 4, is wrien as VDD. ( β ( VDD VH βvdd ( v Subsiuing (8, (9 and ( ino (, following equaion is derived. VDD Q v v ( + ( v 4 (4ln V + + DD 3 v v ( + ( v 4 3 VDD 8 (3 From (3, he effecive linear resisance can be solved as he funcion of. η 3 ( + 3 ln (3 / 4 v ( v + (/ v +. (4 where v is V H /V DD. In order o give insigh ino he arameric deendence of η, (4 is simlified as η / h.7 +.v VDD / I D. ( 6

4 /, η /, η µm.3 / (SIE η(alculaed v V H /V DD.6.4..µm.3 / (SIE η(alculaed v V H /V DD Figure / and η deendence on v his exression acs as a bridge beween he effecive ransisor resisance and device characerisics. In Fig., he SIE simulaion resuls are comared wih (. Differen echnology models and various inerconnec widh and heigh are used for his simulaion and he validiy of ( is confirmed. Figure 6 shows he oimum delay comarison beween he roosed mehod where he effecive linear resisance ( is used and he convenional mehod in [] where he linear resisance is chosen as he 3 (/(maximum drain conducance as is shown in Fig. 4. he discreancy beween he delay simulaed by SIE wih real buffers and a disribued line and he calculaed delay wih he effecive linear resisance ( is wihin 3%. On he oher hand, he discreancy beween SIE simulaed delay and he delay calculaed wih he convenional 3 is more han 3%. On he oher hand, he discreancy in ower beween hese mehods is wihin 6% (see Fig.7. he oimum buffer size (h O is roorional o and he oimum number of buffers ( O is roorional o /. his is why he oal ower wih buffers, which is roorional o h O O, is unchanged even if he effecive linear resisance is changed. hen, in order o confirm he validiy of he roosed formulas for h O, O and do, heoreical calculaions and SIE resuls are comared. he model arameer se for SIE simulaion and for roosed formulas are exraced from measured daa wih.µm D-SOI echnology whose es chi is shown in Fig. 8. he SIE model agrees well wih he measured resuls as in Fig. 9. Figure shows he h O, O and do comarison beween rigorous oimizaion resuls wih SIE and he Oimum delay wih linear resisance [s] 3 3.7µm.3 (alculaed Oimum delay wih real buffer [s] Figure 6 Oimum delay comarison beween and 3 ower wih linear resisance [W/mm]...7µm.3 (alculaed 3 Delay oimized.. ower wih real buffer [W/mm] Figure 7 ower comarison beween and 3 Figure 8 Microhoograh of es chi fabricaed by.µm D SOI rocess I D [A] SIE measured.µm D-SOI (body conac.. V GS [V] Figure 9 Drain curren comarison beween SIE model and measured daa 7

5 calculaed resuls. Figure shows he ower deendence on he J /. When he juncion caaciance is negligible, boh he oimum delay and he ower wih buffers are suressed by % comared wih he MOSFE wih J. I is shown from (, (3 and (4 ha he % reducion on ower and delay is indeenden from he echnology node. 3. Inerconnec Delay and ower omarison Beween Bul and SOI echnology Exending he analysis, he oimum inerconnec delay comarison among bul, D-SOI, FD-SOI and double-gae srucure [6] is discussed using he simle model. he characerisics of hese models are lised in able II. We se he leaage curren of hese srucures equal o mae he comarison fair. hen, V H of FD-SOI and double-gae can be lowered since he S-facor is smaller han oher srucures. J / and V H /V DD are he measured daa of five differen echnologies. J / of convenional bul rocess are.7.3. his value does no change drasically over generaions. he calculaed resuls are shown in Fig.. D-SOI wih body conac is % faser han bul MOS echnology due o he small juncion caaciance. I is ofen discussed ha SOI echnology does no give seed and ower imrovemen over bul MOS echnology in dee submicron designs, since seed and ower are deermined by inerconnecs and SOI echnology does no change inerconnec layers. I is no necessarily rue because dee submicron inerconnec sysems need relaively large buffers and due o he imrovemen hrough buffers, SOI echnology sill enjoys advanage over bul MOS. he delay can be furher decreased by using D-SOI wih a floaing body or FD-SOI since he drain curren is enhanced by he in effec and he lower hreshold volage. If lower J is achievable wih bul MOS echnology, he bul echnology aroaches SOI resuls. In he oimally buffered inerconnec, he ower dissiaion increases due o he buffers. Here, he rade-off beween ower and delay is discussed. e us inroduce he arameer,, which is he raio of he oal ower (buffers and inerconnec, OA, o he ower consumed by ure inerconnec,. ( OA h + + J (6 If is fixed, he oimum buffer size, h, he number of he secions,, and he delay, d, can be exressed as follows. h O O do [ns].µm D-SOI 34.6mm (Global V DD.V SIE alculaed. J /..µm D-SOI 34.6mm (Global V DD.V SIE alculaed. J / % delay decrease.µm D-SOI 34.6mm (Global V DD.V SIE alculaed. J / Figure h O, O and do comarison beween calculaed resuls and SIE simulaions Normalized ower ((w/o buffer..8 % ower decrease.6. J / Figure ower deendence on J / 8

6 able II Bul and SOI srucure J / V H /V DD Bul.9.8 D-SOI.3.8 (body conac D-SOI.3.8 I ON. (in (floaing FD-SOI.3.3 S6mV/decade Double-gae [].3.3 S6mV/decade I ON, Bul ( J D-SOI (body conac D-SOI (floaing FD-SOI (S6mV/dec Double gae (S6mV/dec Normalized oimum delay (Bul Figure Delay comarison beween bul and SOI h h O O d do where ( ( + ( ( + + ( J (7 (8 he delay deendence on he oal ower is calculaed using he roosed formulas. he resul is shown in Fig. 3. I can be seen from he figure ha he ower can be reduced by % if delay is allowed o increase by %. 4. onclusion losed-form formulas for oimum buffer inserion wih he juncion caaciance effec aen ino accoun are roosed and an aroximaion of MOSFE as a linear resisor is invesigaed. d / do.8.. J / J /. J / OA / Figure 3 Delay deendence on oal ower Using hese formulas, he oimum inerconnec delay comarison among bul, D-SOI, FD-SOI and double-gae srucure is discussed. If he juncion caaciance can be negligible, he oimum inerconnec delay is % smaller han he delay when J. MOSFE wih small juncion caaciance, lie SOI, can suress he inerconnec delay by % comared wih MOSFE wih J, lie convenional bul MOSFE. Acnowledgemen he wor has been suored by oshiba ororaion. eferences [] Y. I. Ismail and E. G. Friedman, Effecs of inducance on he roagaion delay and reeaer inserion in VSI circuis, IEEE rans. VSI sysems, vol. 8, No.,.9-6, Ar.. [] K. Banerjee and A. Mehrora, Accurae analysis of on-chi inducance effecs and imlicaions for oimal reeaer inserion and echnology scaling, Symosium on VSI ircuis, Dig. of ech. aers,.9-98,. [3] V. Adler and E. G. Friedman, eeaer design o reduce delay and ower in resisive inerconnec, IEEE rans. ircuis and Sysems II, vol. 4,.67-66, May, 998. [4]. Saurai and A.. Newon, Alha-ower law MOSFE model and is alicaion o MOS inverer delay and oher formulas, IEEE Journal of Solid-Sae ircuis, vol.,.84-93, Ar., 99. []. Saurai, Aroximaion of wiring delay in MOSFE SI, IEEE Journal of Solid-Sae ircuis, vol.s-8, no.4,.48-46, Aug., 983. [6]. anaa, H. Horie, S. Ando and S. Hijiya, Analysis of + oly Si double-gae hin-film SOI MOSFEs, IEEE Inernaional Elecron Device Meeing (IEDM, , 99. 9