AND8321/D. Compensation of a PFC Stage Driven by the NCP1654/5

Transcription

1 AND8/D Compensation of a PFC Stage Driven by the NCP654/5 Prepared by Joel Turchi ON Semiconductor Circuits for power factor correction have to shape the line current that is a low frequency signal. Hence, they are in essence extremely slow systems. That is why, the compensation of the PFC loop is generally not considered as a critical step when designing a power supply: wildly shrink your bandwidth, that s it!. Still however, a PFC stage must be compensated and this unavoidable step should be properly performed for an optimized operation of the downstream converter and a satisfactory power factor. This application note shows how a NCP654 or NCP655 driven PFC can be compensated by the means of a systematic method. Reusable for other circuits, this process is practically illustrated through a wide mains, 00 W application. Introduction The NCP654 and the NCP655 are upgraded versions of the NCP65. With their father, they share the control scheme that led to a major leap towards implementation of PFC boost converters operating in continuous conduction mode. Practically, like the NCP65, they directly control the power switch conduction time (PWM) as a function of the coil current. Housed in a SO8 package and available in 65 khz, the NCP654 and the NCP655 integrate all the features for a compact and rugged PFC stage. Ultimately, as well as the NCP65, they lead to an eased and compact PFC implementation. It is worth noting that they have also inherited the NCP65 current sensing technique and its associated merits. More specifically, this function can be associated to very low impedance current sense resistors for reduced losses and a significant improvement of the efficiency. Compared to traditional solutions, the efficiency increase can be as high as almost %. Finally, with respect to the NCP65, the NCP654 and the NCP655 further incorporate a brown out detection block to disable the PFC stage when the line magnitude is too low. Also, the voltage regulation is made more accurate and a dynamic response enhancer dramatically minimizes the large deviation of the output voltage that a sharp line/load step would otherwise produce. The NCP654 pinout is intended to ease the replacement of industry existing circuits. The NCP655 is pin to pin compatible to the NCP65. PFC Stage Control to Output Transfer Function First, we have to compute the control to output transfer function ( /V control ), where is the output voltage of the PFC stage and V control, the output of the error amplifier (that is, our control signal) To do so, we need to:. Derive a large signal model of our system. Such a representation takes into account the dc and ac components of the signals. The result is a non linear representation in particular due to the multiplication of time varying signals.. Linearize this system and for this, to consider little variations of each signal around the dc values (obtained in steady state) to derive the small signal model. Practically it models the system response to a perturbation applied to the two input signals (V in,rms and V control ) or to the output ( ). This is exactly what our compensation will have to control. In PFC applications, a good way to build the large signal model, is probably to inspire of the loss free network method developed by Dr Robert Erickson [] and:. Derive an equation of the power delivered by the PFC stage as a function as the parameters that modulate it, practically, the line magnitude and V control. To do so, this power will be averaged over a line period. (Note ). Represent our system as a current source that under provides the computed power.. This approximation (constant power while it has actually a squared sinusoidal characteristics) is acceptable since the PFC regulation bandwidth is below the line frequency. Semiconductor Components Industries, LLC, 008 June, 008 Rev. 0 Publication Order Number: AND8/D

2 AND8/D The average power delivered by the NCP654 is given by the following formula (refer to the data sheet): K (V control V control(min) ) V in,rms R CS (R bou R bol ) V REF P in,avg with: K (eq. ) RM R bol R SENSE V in,rms is the RMS line voltage V control is the output voltage of the NCP654/5 error amplifier V control(min) is the minimum output voltage of the error amplifier. is the PFC output voltage V REF is the internal.5 V reference voltage R SENSE is the current sense resistor R CS is the resistor that sets the current limitation R M is the V m pin resistor R bou, R bol are the upper and lower brown out sensing resistors respectively. Please note that R bou is practically spit into two or several resistors for safety reasons (due to its connection to the input high voltage rail) (See Figure 7). Our system can then be represented by a current source (I out = (P in,avg / )) that charges the bulk capacitor. C which is loaded by a resistor R that simulates the load. This leads to the following large signal model: P in,avg I out K V control V control(min) V in,rms V out r C C R Figure. Large signal model of the PFC stage (R is the Load Equivalent Resistance and C and r C are Respectively the Capacitance and the Series Resistor of the PFC Output Capacitor Bulk Capacitor) Considering small variations for V control, V in,rms and, one can derive the following small signal equivalent schematic: r C I I r C R Figure. Small Signal Model of the PFC Stage (R is the Load Equivalent Resistance and C is the PFC Output Capacitor Bulk Capacitor)

3 AND8/D In Figure : I is a current source that models the I out variation produced by small V control variation v control. dl K I in,rms v v (eq. ) dv control control V control out I models the I out variation that results from a small variation of V in,rms. dl K control V control(min) I v v (eq. ) dv in,rms in,rms in,rms r models the I out variation that results from a small variation of (Note ). V out r R P in,avg Here, we do not consider the input voltage variations. Hence, ( v in,rms = 0) and the current source I cancels. If in addition, we note that R/ is the resistance equivalent to that of R wired in parallel with R/, Figure simplifies as follows: (eq. 4) I r C C R/ Figure. Small Signal Model Where the Line Variations are Not Taken Into Account The bulk capacitor (including the series resistor r C ) in parallel to the load ( R ) leads to the following impedance: Z C rc R R s rc C s rc R C As the capacitor series resistor ( r C ) is small compared to R, the precedent formula simplifies as follows: Z R s rc C src Hence, the transfer function is: V K R in,rms Z I V control V out Thus, we have: The following pole: f RC R C A zero due to the series resistor of the bulk capacitor: f ESR r C C A static gain that is dependent on the line and load levels: G0 0 db log K R V in,rms V out s rc C src (eq. 5) (eq. 6) (eq. 7). When we compute: I di out d v out K (V control V control(min) ) v out I v out out v out R we note that I is simply the current of the resistor (R/) places across ( v out ). That is why a resistor r = (R/) simulates the impact of variations on the bulk capacitor charge current.

4 AND8/D Output to Control Transfer Function The NCP654 embeds a transconductance error amplifier (OTA). Hence, the OTA output current (I control ) is: I control G EA R fbl V R out V R fbl R REF fbu fbl Vout,nom G EA (eq. 8) R fbl R fbu R fbu is the feed back upper resistor. Please note that R fbu is practically spit into two or several resistors for safety reasons (due to its connection to a high voltage rail) (See Figure 7). R fbl is the feed back lower resistor.,nom is the regulation level of the output voltage. G EA is the trans conductance gain of the error amplifier (00 S typically) The precedent section shows that the power stage exhibits one pole and one zero that we have to compensate. A type compensator that brings two poles and one zero (as portrayed by Figure 4) is the recommended solution. R fbu Error Amplifier R fbl V ref V control C R C I control Figure 4. Type Compensation One can calculate the control function of our type compensator: V control s R C I control Hence, substitution of the I control expression into the precedent equation leads to: V control R fbl R fbl R fbu s(c C) s RCC CC (eq. 9) s (CC) G EA s R C s RCC CC (eq. 0) R fbl and R fbu are the feedback resistors that scale down the output voltage for regulation. Hence, in steady state: V REF R fbl,nom (eq. ) R fbl R fbu V REF is the NCP654/5.5 V reference voltage.,nom is the output regulation level. Finally, if C << C, Equation 0 simplifies as follows: s fz V control s f p0 s fp 4

5 AND8/D f z R C f p R C f p0 R 0 C,nom R 0 V REF G EA Closing the Loop We need then to position the poles and zeroes of the compensator so that the open loop gain crosses zero db at the crossover frequency f c with a ( ) slope and the wished phase margin. We have the choice between several techniques to define our compensation network like the k factor method from Dean Venable or the manual placement presented in Christophe Basso book [5]. Here, we propose to simply compensate our PFC stage by systematically forcing a ( ) slope for the open loop gain up to the crossover frequency. It can be done as follows:. Select the crossover frequency f c, that is, the frequency at which the open loop gain drops to 0 db. It is generally admitted that it should be in the range of half the line frequency at high line (we will see that the crossover frequency peaks at high line). Actually f c must be as low as possible to obtain a near unity power factor. This is because any ripple on the error amplifier output generates some distortion of the line current. On the other hand, a low crossover frequency leads to a slow response to load or line variations. So, if your power factor specification is not very stringent, it is wise to increase f c with the benefit of better dynamic performance. Generally speaking, f c equal to half the line frequency at high line is a good starting point.. Position the zero of your compensation at the frequency of the pole: (f z = f RC ) so that they cancel each other.. Place f p so that it cancels the zero produced by the ESR of the bulk capacitor: (f p = f ESR ). If (f ESR ) is a very high frequency zero, you should clamp (f p ) to half the switching frequency for a good filtering of the switching noise. This pole filters the high frequency noise: f SW f p 4. The poles and zeroes of the power stage are cancelled by the zero and pole of the compensator. Hence, the open loop gain only depends on the pole at the origin f p0 that forces a ( ) slope and on the static gain. In other words, the gain equates: (G(f)) db (G 0 ) db 0 log f f p0 To obtain the wish crossover frequency, we then need to choose (f p0 ) so that: 0 (G 0 ) db 0 log f c f p0 Ultimately, this leads to the following equation giving f p0 as a function of f c and G 0 : f p0 f c 0 (G 0 )db 0 Please note that using this method, the phase margin asymptotically tends towards 90, which must ensure a very stable operation. Now, if you want to shorten the recovery time of the output voltage after a load step, you can decrease the phase margin to for instance 75, for an optimized performance. To do so, you can play with the high frequency pole following the procedure shown in [4]. Practically, this pole is placed at a lower frequency so that the phase shift it produces can alter the phase margin measured at: f p f c tan( m ) Where is the desired phase margin. 5

6 AND8/D At which load and line voltage should we compensate our PFC stage? As shown in section, there are two parameters that depend on the load and line conditions: The static gain (G 0 ) is proportional to line magnitude (V in,rms ) and to the load equivalent resistance (R) The pole f RC of the power stage is inversely dependent on: Rf RC R C The compensation method that is proposed, suppose: The pole f RC is canceled by the compensator zero The pole at the origin by the compensator is set as a function of the static gain. Let s assume that we design our compensator for full load conditions: R = R min. The compensator zero (f z ) is then computed for R = R min. At this load, f z perfectly cancels the power stage pole (f RC ). At any other load, its frequency is too high to cancel f RC. As a consequence, the loop gain will be attenuated as follows: On the other hand, we know that the static gain is increased as follows: G db 0 log f RC f z 0 log R R min (eq. ) G0 db 0 log K R V in,rms 0 log K R min V in,rms 0 log R R min (eq. ) Finally the two gain variations cancel! Simply, we switch from Figures 5 and 6. A change in the load does not shift the crossover frequency. So, for instance, we can choose to make the computation at full load. Gain (db) Gain (db) 40 db/dec 0 db/dec G G 0 db/dec 0 db 0 db f RC f z f ESR f p f f RC f z f ESR f p f Figure 5. Figure 6. As for the input voltage, it also changes the static gain but there is no change in the poles and zeroes position. So, the open loop gain is (G 0 ) shifted and the crossover frequency f c is higher at high line than low line: (V in,rms ) HL (f c ) HL (f c ) (V in,rms ) LL (eq. 4) LL (f c ) HL is the high line crossover frequency. (f c ) LL is the low line crossover frequency. (V in,rms ) LL is the lowest line RMS voltage. (V in,rms ) HL is the highest line RMS voltage. As the ratio is generally between low and high line levels in a wide mains application, with the NCP654/5, we can expect a ratio of between the corresponding crossover frequencies: (f c ) HL (f c ) LL (eq. 5) Finally, it seems reasonable to choose the crossover frequency to be targeted at high line and based on this selection, compute the compensation network for high line, full load. 6

7 AND8/D Example Let s illustrate the process in the following application: Universal Mains: V in,rms varying from 90 to 65 V. Line Frequency: 50 Hz or 60 Hz Output Voltage Wished Level (,nom ): 90 V dc Output Power: 00 W Output Capacitor: 80 F / 450 V, ESR resistance: 500 m Switching frequency: 65 khz The way of designing such a PFC stage is discussed in AND8/D []. From it, we can deduce the following: At high line and full load (R = 500 ), R CS (R bou R bol) V REF.6k 668.k.5 K 689 A (eq. 6) RM R bol R SENSE 47k 8.5k 0. (G 0 ) db 0 log K R (V in,rms ) HL V out 0 log 46dB 90 (eq. 7) Then, we can start the above presented process to close the loop:. Crossover Frequency at High Line: Let s choose it in the range of half the line frequency. As the specification indicates two line options (50 Hz or 60 Hz), let s use the lowest one: (f c = f line / = 5 Hz). We will then compute the compensation network with (f c = 5 Hz) at high line.. Position the zero of your compensation at the frequency of the pole of the power stage: f z = f RC so that they cancel each other. Practically, f z R C f RC (eq. 8) R C Hence: R C R C R R C (eq. 9) C. The frequency of the zero resulting from the bulk capacitor ESR is: f ESR = (()/( r c C)) = (()/( 500m 80).8 khz, This frequency is far below the switching frequency so we simply have to place f p so that it cancels f ESR without any clamp below ((f SW )/()) consideration: f p = (()/( R C)) = (()/( r c C), where r c is the ESR of the bulk capacitor. Then: R C = r c C C = ((r c C)/(R)) 4. The poles and zeroes of the power stage are cancelled by the zero and pole of the compensator. Hence, the open loop gain only depends on the pole at the origin f p0 that forces a ( ) slope and on the static gain. In other words, as previously explained, to obtain the wished crossover frequency, we need to choose (f p0 ) so that G 0 : Hence: f p0 f c 0 (G 0 )db 0 Where as previously indicated: Finally in our application: Let s choose C =.5 F: R 0 (G 0 )db C 0 f c R 0 (G 0 ) db C 0 0 (eq. 0) f c R 0,nom k (eq. ) V REF G EA F (eq. ) 5 780k R R C k (eq. ) C.5 7

8 Let s choose R = 0 k: AND8/D C r c C 500m nf (eq. 4) R 0k Let s choose C = 4.7 nf: With the computed C, the phase margin is in the range of 90. If you target a lower one for a faster recovery of the output voltage after a load step, you can position the high frequency pole at a lower frequency level. Practically, the high frequency pole must meet the following equation: f p f c tan( m ) (eq. 5) And then: C (eq. 6) f c R tan( m ) For instance, if you target a 45 phase margin: C 0. F (eq. 7) f c R tan(45) A 0 nf capacitor would then be a good choice. 8

9 AND8/D Summary The following table summarizes the main equations useful to compensate a NCP654/5 driven PFC stage. Refer to Figure 7 for the meaning of the computed components. Components Formulae Comments NCP654/5 CHARACTERISTICS Power delivered by the PFC stage Error Amplifier Transconductance Internal Voltage reference for Regulation K (V control V control(min) ) V in,rms P in,avg R CS (R bou R bol) V ref K RM R bol R SENSE G EA 00 s V REF.5 V V REF is the internal.5 V PWM reference, R CS is the resistor that dictates the maximum coil current together with R SENSE (current sense resistor), R bou and R bol are the upper and lower brownout resistors respectively, R M is the resistor that sets the maximum power of the PFC stage. AND8/D shows how to compute these elements. POWER STAGE GAIN Static Gain at Full Load, High Line (db) Pole Zero COMPENSATION NETWORK Crossover Frequency at High Line Variation of f c with respect to the line amplitude R0 C (G 0 ) db 0 logk R min V in,rms HL f RC R C f ESR r c C f fc line HL (V in,rms)hl (f c ) HL (f c ) (V in,rms ) LL LL,nom R 0 V REF G EA (G 0 ) FB db C 0 0 fc R Feedback pin 0 The static gain is line and load dependent. In PFCs that unlike the NCP65/4/5, do not feature any feed forward, G 0 even varies as a function of the square of the line RMS level. The static gain is calculated at full and high line as as necessary to compute our compensation network. Pole resulting from the bulk capacitor and the PFC load equivalent resistor. Zero produced by the series resistor (ESR) of the bulk capacitor. The crossover frequency moves as a function of the line amplitude (see below). Subscript HL stands for high line. Subscript LL stands for Low line. In wide mains application, we have a ratio in the range of between (f c ) HL and (f c ) LL. Equivalent resistor that sets the pole at the origin (f p0 ) together with C.,nom is the regulation level of the output voltage (90 V typically). V control R R R C C V ref C Cz C C r c C R or C f c R tan( m ) C leads to 90 phase margin, C to a lower one ( m ) if wished. C must be higher than C. 9

10 AND8/D V in L D C filter IN R fbu C R SENSE 0k EMI Filter R bou R CS R g NCP654 R fbu R bou GND DRV 8 V CC VM VCC 7 CS FB 6 4 BO Vcontrol 5 L N R bol C BO C M R M C C R C FB R fbl CVCC Figure 7. Generic Application Schematic (with NCP654) In this schematic, for the sake of a realistic representation, the brown out and feedback upper resistors are split into two parts: (R bou = R bou R bou ) and (R fbu = R fbu R fbu ). Conclusions The paper presents a systematic approach to compensate your NCP654/5 PFC stage. Such a process is useful to optimize your PFC stage particularly when you seek for the best trade off between power factor quality and dynamic performance. Ultimately, it must ease and improve design of the whole power supply. References. Fundamentals of Power Electronics by Robert W. Erickson. Venable, H. Dean. The K Factor: A New Mathematical Tool for Stability Analysis and Synthesis. Proceeding Powercon. 0 March 98. AND8/D, Four Key Steps to Design a Continuous Conduction Mode PFC Stage Using the NCP654, by Patrick Wang, 4. AND84, Key steps to design a post regulator driven by the NCP4, by Joel Turchi, 5. Switch Mode Power Supplies Spice Simulations and Practical Designs, by Christophe Basso, McGraw Hill ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 56, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative AND8/D