Pixel Capacitance Planar and DNW-Sensors. Hans Krüger, Bonn University

Transcription

1 Pixel Capacitance Planar and D-Sensors Hans Krüger, Bonn University

2 Planar Pixel Sensor Capacitance Total sensor capacitance C d = C a + C a + C p A Capacitance to backplane C a ε r d (parallel plate capacitor) Capacitance to FE chip C a (similar to C a with different ε r and d) Capacitance to neighbor pixels C p ( perimeter length) (fringe capacitance 2D/3D field solver) Front-end chip d C a C a n-implant n-implant P+ P+ P+ d C a C p p-substrate C a P+ 12/17/2013 H. Krüger, Bonn University 2

3 Planar Pixel Sensor Capacitance Measurement data for 250 x 50 µm 2 pixel Si planar sensor, 230µm thick: C d = ± 3. 8 ff C parallel plate = 5.6 ff Diamond sensor, 750µm thick: C d = 21.4 ± 0.1 ff C a = 1.9 ff (C parallel plate = 0.84 ff) C a = 4 ff (C parallel plate = 5.5 ff) C p = 13.1 ff + 2 ff (2nd neighbors) Measured capacitance values for a 250 x 50 µm 2 pixelated CVD Diamond sensor, 750µm thick M. Havránek et al., Measurement of pixel sensor capacitances with sub-femtofarad precision, NIM A 714 (2013) /17/2013 H. Krüger, Bonn University 3

4 Planar Sensor Inter-pixel Capacitance Pixel-to-pixel capacitance C p is dominating (rather than pixel to backplane) Pixel perimeter: 2 (p 1 + p 2 ) Gap between pixels: g = p w Ratio of pixel pitch to implant width (w/p) fill factor p 2 p 1 g w 4 Inter-pixel capacitance C p measured on a 400 x 50 µm 2 n-on-n Si pixel sensor G. Gorfine et al. / Nuclear Instruments and Methods in Physics Research A 465 (2001) /17/2013 H. Krüger, Bonn University

5 Pixel Scaling: FE-I3 FE-I4 FE-x FE-I3 FE-I4 FE-x Pixel geometry p1, p2 400 x 50 µm x 50 µm x 25 µm 2 Pixel area A p µm µm µm 2 Pixel perimeter L p 900 µm 600 µm 300 µm Pixel density [#pixels/cm 2 ] X Perimeter length per cm 2 P T 45 m 48 m 96 m Pixel capacitance C d 150 ff (meas.) 110 ff (meas.) 52 ff (estim.) Capacitance per cm 2 C area 7.5 nf 8.8 nf X 2 17 nf (estim.) Planar pixel capacitance dominated by capacitance to neighbor pixels C perimeter Estimated perimeter capacitance (20µm gap between implants): 0.16 ff /µm Total capacitance per area scales approx. with ppppp ddddddd 12/17/2013 H. Krüger, Bonn University 5

6 D Junction Capacitance Two contributions to the total capacitance D to substrate junction Depends on substrate resistivity Area capacitance D/SUB Outer side wall capacitance: D/SUB + /SUB D to P-well junction PW and D both strongly doped Gap between PW and reduces side wall capacitance, but reduces electronics area Area capacitance PW/D Inner side wall capacitance: /SUB (or /PW, which would be higher) P+ PW C P+ sw d C a D C p C p d C a p-sub P+ 12/17/2013 H. Krüger, Bonn University 6

7 D Junction Capacitance Example A 130nm CMOS technology with D (T3) 1 Ω cm substrate Large pixel: 225 x 22 µm 2 D size = 220 x 17 µm 2 (pixel pitch 5µm) PW size = 218 x 15 µm 2 (D size 2 µm) SPICE model C Total C Area C Perimeter Total capacitance C d (Ub = 12V) = 962 ff ff = 1.6 pf D/PW cap., technology dependent, scales with PW area D/SUB capacitance, decreases with higher substrate resistivity Same size planar sensor: ~80 ff (estimated) 12/17/2013 H. Krüger, Bonn University 7

8 D Junction Capacitance Example B 130nm CMOS technology with D (T3) 1 Ω cm substrate Small pixel: 10 x 10 µm 2 + D No PW inside SPICE model Implant capacitance C d (U b = 12V)= 44 ff 12/17/2013 H. Krüger, Bonn University 8

9 D Junction Capacitance Example C 150nm CMOS technology with (deeper) D on high resistivity substrate 2 kω cm substrate CCPD like layout Pixel: 125 x 33 µm 2 D: 107 x 15 µm 2, small PW/PSUB area TCAD Simulation Inner area capacitance NISO PW P+ P+ C NISO sw d NISO PSUB C a C p D C p d C a p-bulk PW NISO D-PW D-PSUB P+ Total D capacitance: ~100 ff D-PW/PSUB: ~35fF + 16fF area + fringe capacitance 5V D to neighbor pixels: ~50fF based on estimation of planar sensors C P could be higher due to deeper n implant D to high ohmic bulk: negligible ~3 50µm depletion, U b ~20 V D-PSUB, 6µm gap Inner fringe capacitance D-PW/PSUB, 3µm gap 12/17/2013 H. Krüger, Bonn University 9

10 Conclusion Planar sensors Detector capacitance dominated by coupling to neighbors (perimeter) Total capacitance per area scales approx. with ppppp ddddddd Active CMOS sensors with high fill factor (HV-CMOS, T3 MAPS...) Capacitance to substrate + neighbor pixels (outer capacitance), can be reduced with higher bulk resistivity ( similar or slightly higher capacitance as with planar sensors) Capacitance to electronics (inner capacitance to p-well), can only be reduced with smaller PW area (less electronics) or deeper D or both Planar sensor hard to beat when it comes to input capacitance Consider the power budget needed to compensate for higher C d Higher input capacitance requires higher g m for not only SNR but also rise time requirements Minimize inner D capacitance Careful optimization of the D/PW layout Use multiple small D-only contacts (without inner PW) per pixel to make a compromise between fill factor and capacitance 12/17/2013 H. Krüger, Bonn University 10

11 Backup 12/17/2013 H. Krüger, Bonn University 11

12 Planar Pixel Sensor Capacitance Simple model for pixel capacitance estimation C d = A ppppp CC pppppppp ppppp + L ppppppppp CC ppppppppp A piiii, pixel area L ppppppppp = 2 pp + 2 pp, pixel perimeter length A ppppp C pppppppp ppppp, specific area capacitance [ff/µm 2 ] CC peeeeeeee, specific perimeter capacitance [ff/µm] p 1 p 2 g A pixel Total capacitance per area as a function of pixel density (#pixel/area) C aaaa #ppppp/aaaa = #ppppp aaaa C d = ccccc. + A ppppp aaaa #ppppp L ppppppppp A ppppp = aaaa #ppppp b depends on the pixel aspect ratio Parallel plate capacitor #ppppp/aaaa b C ppppppppp Perimeter capacitance Total capacitance per area scales with ppppp ddddddd Example: FE-I4 planar pixel sensor C d = 110 ff Parallel plate capacitor per pixel (to back plane and ASIC): ~12 ff (250 x 50µm 2 pixel) CC ppppppppp = (C d 12fF)/L p = 0.16 ff/µm 12/17/2013 H. Krüger, Bonn University 12

13 pn-junction Capacitance Model SPICE-Model for junction capacitance per unit area at reverse bias C j = CC 0 1 U bbbb V pp mm C j0 zero bias junction capacitance per µm 2 V bp build in potential U bias < 0, reverse bias m j grading exponent (abrupt step: 0.5, linear gradient: 0.33) Different of coefficients for area and perimeter (side wall) contributions Equals C j = ε 0 ε r d with d = 2ε 0 ε r q N a +N d N a N d (V bb + U bbbb ) for m j = /17/2013 H. Krüger, Bonn University 13

14 Doping Profiles, Resistivity & Depletion Example: 130nm CMOS technology with D, 3 kω cm substrate ~0.8µm U D_PW = 20V P+ PW PW PW ρ pw ~ 0.05 Ω cm D ρ dnw ~ 0.1 Ω cm P + - PW - D P-SUB ρ psub ~ 3k Ω cm Doping profile ~150µm depletion U bias = 100V H. Krüger, Bonn University 14

15 Noise Pixel Capacitance Noise, Rise Time, CCE EEE ttttttt Rise time ( time walk) τ r = C d C o g m 1 C f Charge collection efficiency 1 g m τ sssssss (C d +C f ) CCC = C f A 0 C d +C f A 0 Note: If CSA rise time τ r defines shaping time EEE ttttttt C d Depends only little on g m (I bias ) 12/17/2013 H. Krüger, Bonn University 15