Logical Analysis of. The Importance of Being Constructive.
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1 Logical Analysis of Synchronous Distributed Systems: The Importance of Being Constructive. Michael Mendler, Bamberg University (based on joint work with Tom Shiple and Gérard Berry) M. Mendler, Bamberg University HDT 2017 Vienna,
2 The Logical Paradox of Synchronisation Synchronisation algorithms/hardware pretend to achieve global event ordering and common knowledge simply by localcausalinteractions However, correctness proofs merely reduce the problem, by pushing it into the assumptions are not constructive since they use reasoning by contradiction in classical logic To illustrate this, take constructive logician s perspective on asynchronous hardware... M. Mendler, Bamberg University HDT 2017 Vienna,
3 Overview 1. Synchronous Reactions 2. Constructive Logic 3. Intuitionistic Theory of Intervals 4. Modalities for Causality 5. Ideal Inertiality is not Constructive 6. Regaining Constructiveness 7. Conclusion M. Mendler, Bamberg University HDT 2017 Vienna,
4 1 SYNCHRONOUS REACTIONS
5 Synchronous Programming input stimulus clock barrier clock barrier output response Synchronous Algorithm = synchronous interaction of Mealy machines (hierarchy + concurrency + preemption) M. Mendler, Bamberg University HDT 2017 Vienna,
6 Synchronous Programming input stimulus clock barrier clock barrier deterministic bounded functional output response Synchronous Programming = macro step reaction is a deterministic, time bounded function of inputs M. Mendler, Bamberg University HDT 2017 Vienna,
7 Pure Signals & Transitions positive triggers negative triggers only positive actions "if a present and b absent, then c and d are present" M. Mendler, Bamberg University HDT 2017 Vienna,
8 Example: Synchronous Reactive Modelling Synchronous Distributed Algorithm = synchronous interaction of Mealy machines (hierarchy + concurrency + preemption) s11 s13 s1 money /roses t2 s clock barrier Clark Completion roses /money kiss/ s21 s22 s4 t4 t5 s2 t3 s31 s32 s3 money,roses /kiss Unique Boolean Solution M. Mendler, Bamberg University HDT 2017 Vienna,
9 Boolean Reactions Unstable... t2 roses t5 t4 kiss t3 money Inertial Delay General Multiple Winner (GMW) Model [Huffman 54, Muller 56, Brzozowski/Yoeli 79] t2 roses t5 money t3 kiss t4 Oscillation! M. Mendler, Bamberg University HDT 2017 Vienna,
10 Classical Logic is Reactively Inadequate constructively distinct classically equivalent M. Mendler, Bamberg University HDT 2017 Vienna,
11 2 CONSTRUCTIVE LOGIC
12 What is Constructive Logic? Classical Logic Excluded Middle: Double Negation: Constructive Logic Disjunction Property: Existential Property: Note: Instead of validity can also use provability Constructive proofs have computational meaning M. Mendler, Bamberg University HDT 2017 Vienna,
13 What does constructiveness buy us? constructive reaction of network N under input Disjunction Property (s stabilises to 0) (s stabilises to 1) s stabilises to 0 or s stabilises to 1 Existential Property t. s stabilises at time t for some delay bound D, s stabilises at time D Constructive reactions are always deterministic and bounded! M. Mendler, Bamberg University HDT 2017 Vienna,
14 Constructive Logic Brief Brower, Heyting [1956]: intuitionistic logic, pseudoboolean algebra Kripke [1965], Beth [1959]: truth value semantics on frames of construction ( creative mathematician ) Rasiowa, Sikorski [1963]: topological models Brouwer, Heyting, [1954] Kreisel [1965]: BHK or realisability interpretation 1980s: Type Theory (Martin Löf, Girard s Calculus of Construction) Propositions as Types, program extraction M. Mendler, Bamberg University HDT 2017 Vienna,
15 Digression WHAT ABOUT TERNARY ALGEBRA?
16 Ternary Algebra Recursion Theory [Kleene 52] Asynchronous Circuits (hazards, races, oscillation) [Yoeli/Rinon 64, Eichelberger 65, Roth 66] [Bryant 87] CMOS transistor level Ternary Simulation [Yoeli/Brzozowski 77, Brzozowski/Seger 95] Analysis of Cyclic Combinational Circuits [Burch/et.al. 93, Malik 93, Shiple 96] [Huang/Parng/Shyu 91] Timed D calculus [Fairtlough/Mendler 96] Real time interpretation [Namjoshi/Kurshan 99, Backes/Fett /Riedel 08] Refined algorithm Synchronous Programming [Berry 99, Schneider/Brandt/Schuele 04, ] M. Mendler, Bamberg University HDT 2017 Vienna,
17 Folklore Ternary Algebra is like a logic of truth values unknown, undefined, non determinism, oscillation, deadlock, metastability, unstable, transient, don t care,... x not quite discrete Scott domain... avoids dangerous classical equalities :... avoids equalities altogether! Ternary logic has no theorems at all, M. Mendler, Bamberg University HDT 2017 Vienna,
18 3 CGMW LOGIC 1: INTUITIONISTIC THEORY ON TIME INTERVALS
19 Intuitionistic Semantics of UI Logic Let, be a time interval and a boolean expression. at every M. Mendler, Bamberg University HDT 2017 Vienna,
20 Example h roses love kiss roses and always love or kiss M. Mendler, Bamberg University HDT 2017 Vienna,
21 Example h roses love kiss love or kiss do not persist M. Mendler, Bamberg University HDT 2017 Vienna,
22 Example h roses love kiss while without roses, no change in love M. Mendler, Bamberg University HDT 2017 Vienna,
23 Basic Properties Equivalence Validity Entailment Extension of Boolean Algebra Let be a free or negated proposition. Then, iff at every M. Mendler, Bamberg University HDT 2017 Vienna,
24 4 CGMW LOGIC 2: MODALITIES FOR UPBOUNDED INERTIAL DELAYS
25 Extension for Delay and Causality for any formula Intuitionism alone doesn t help, we must axiomatise delays (causality), too! S is equivalent to logically inconsistent M. Mendler, Bamberg University HDT 2017 Vienna,
26 Inertial Up bounded Delay [Huffman 54, Miller 65, Brzozowski/Seger 89] D,d D=2 Up bounded Propagation (Setup): An unstable delay must change output if it was unstable for longer than D time. M. Mendler, Bamberg University HDT 2017 Vienna,
![Inertial Up bounded Delay [Huffman 54, Miller 65, Brzozowski/Seger 89] inertiality = glitch swallowed D,d d Up bounded Propagation (Setup): An unstable delay must change output if it was unstable](/docs-images/91/107566285/images/27-2.jpg "for longer than D time. Inertiality (Hold): A stable delay must not change output if it has been stable for d time (only d = 0 and d = ). M. Mendler, Bamberg University HDT 2017 Vienna, 20.10.")
27 Inertial Up bounded Delay [Huffman 54, Miller 65, Brzozowski/Seger 89] inertiality = glitch swallowed D,d d Up bounded Propagation (Setup): An unstable delay must change output if it was unstable for longer than D time. Inertiality (Hold): A stable delay must not change output if it has been stable for d time (only d = 0 and d = ). M. Mendler, Bamberg University HDT 2017 Vienna,
28 Modality for Propagation Delay ( Set up ) h roses love kiss M. Mendler, Bamberg University HDT 2017 Vienna,
29 Modality for Propagation Delay ( Set up ) M. Mendler, Bamberg University HDT 2017 Vienna,
30 Modality for Inertiality ( Hold ) h roses love kiss M. Mendler, Bamberg University HDT 2017 Vienna,
31 Modality for Inertiality ( Hold ) M. Mendler, Bamberg University HDT 2017 Vienna,
32 Inertial Delay Specification abbreviate the formula D,d e 2 e 1 M. Mendler, Bamberg University HDT 2017 Vienna,
33 Negative Feedback is Consistent s D,d s oscillates with maximal period D M. Mendler, Bamberg University HDT 2017 Vienna,
34 UI Network Specifications [Brzozowski & Seger 1995] d 1 d 2 N M. Mendler, Bamberg University HDT 2017 Vienna,
35 5 INERTIALITY (d = 0) IS NOT CONSTRUCTIVE
36 The Switching Rule for The Switching Rule (SR) for the inertiality modality... If a proposition is attractive, and its complement is transient, then eventually will prevail.... embodies essentially classical reasoning: remove simplify M. Mendler, Bamberg University HDT 2017 Vienna,
37 Metastability free Consensus with Inertial Delays System trajectories in the General Multiple Winner (GMW) model of inertial delay operation. [GMW: Huffman 54, Muller 56, Brzozowski/Yoeli 79] M A 11 1*1*1* 11 1*0*0* [RS Latch: Mendler, Shiple, Berry, 2006] B * 11 00* All fair system trajectories converge in bounded time, i.e., no unbounded oscillation, no metastability M. Mendler, Bamberg University HDT 2017 Vienna,
38 Metastability free Consensus with Inertial Delays M [RS Latch: Mendler, Shiple, Berry, 2006] A B SR M. Mendler, Bamberg University HDT 2017 Vienna,
![Yet, Metastability Seems Physically Unavoidable req 1 1 0/1/0/ ack 1 1 req 2 1 0/1/0/ ack 1 2 [Chaney, Molnar 1973]? L. Lamport, R. Palais: On the glitch phenomenon.](/docs-images/91/107566285/images/39-0.jpg "SRI, CA 7611 0811, Nov. 1976. L.R. Marino: General theory of metastability. IEEE TC 30, 2(1981). L. Lamport: Buridan s Principle, 1984 (revised 2012) L. Kleeman, A.")
39 Yet, Metastability Seems Physically Unavoidable req 1 1 0/1/0/ ack 1 1 req 2 1 0/1/0/ ack 1 2 [Chaney, Molnar 1973]? L. Lamport, R. Palais: On the glitch phenomenon. SRI, CA , Nov L.R. Marino: General theory of metastability. IEEE TC 30, 2(1981). L. Lamport: Buridan s Principle, 1984 (revised 2012) L. Kleeman, A. Cantoni: On the unavoidability of metastable behavior in digital systems. IEEE TC 36, 1(1987). R. Ginosar: Fourteen ways to fool your synchronizer. Proc. IEEE ASIC D. J. Kinniment: Synchronization and Arbitration in Digital Systems. Wiley,2007. Th. J. Chaney: My Work on all Things Metastable OR: (Me and My Glitch), M. Mendler, Bamberg University HDT 2017 Vienna,
40 Metastability free Consensus is Not Constructive 1. Termination 2. Agreement 3. Validity Incompatible with constructiveness! by Constructiveness : 5.a or 5.b by 1. and 2. by properties of either choice contradicts Validity! M. Mendler, Bamberg University HDT 2017 Vienna,
41 Inertial Delays Express Sequentiality Synchronisation (e.g., Peterson s Algorithm) based on readwrite registers depend on strict sequentiality of execution. + go y - x = 1 go x + x - y = 1 go y k0 M. Mendler, Bamberg University HDT 2017 Vienna,
42 Inertial Delays Express Sequentiality Without sequentiality we have a logical causality cycle. go go x y + y - go x x = 1 go x + x - y = 1 go y 0 go y k0 0 M. Mendler, Bamberg University HDT 2017 Vienna, k0
43 + y - x = 1 Inertial Delays Express Sequentiality Without sequentiality we have a logical causality cycle. This can can be broken by inertial delays: go go x go x y ; go x d=0 + x - y = 1 go y 0 go y k0 0 M. Mendler, Bamberg University HDT 2017 Vienna, k0
44 6 REGAINING CONSTRUCTIVENESS
45 Constructiveness Regained Definition: A network is non inertial if all system equations have hold me d =. Definition: An network is complete if (equivalently) all gate inputs and gate outputs have a delay the system equations form a bipartite dependency graph. M m A B M. Mendler, Bamberg University HDT 2017 Vienna,
46 Regaining Constructivity Observation: For non inertial networks and for complete networks the switching rule SR becomes redundant (inapplicable). Theorem: For every non inertial network N the theory is constructive. Conjecture: For every complete network N the theory is constructive. (This does not follow from exactness of ternary analysis for complete networks by [Brzozowski, Seger 94] ) M. Mendler, Bamberg University HDT 2017 Vienna,
47 Observation Non inertial Delays (d = ) trivialise d = eliminates the hold constraint: M. Mendler, Bamberg University HDT 2017 Vienna,
48 In Complete Networks Oscillation is Unobservable A, B may jointly switch together with high frequency without w ever becoming unstable 11 11*1* 11 10*0* 1 1 M m A B SR M. Mendler, Bamberg University HDT 2017 Vienna,
49 7 CONCLUSION
50 Conclusion Summary 1. Intuitionistic CGMW logic with and provide causalitysensitive abstraction from continuous boolean signals 2. Synchronisation (mutex, consensus, sequentiality,...) is not implementable with non inertial or complete networks 3. Synchronisation is not constructive and an artefact of discrete time/value abstraction Open Problems Complete axiomatisation of cgmw Logic (for network theories) Proof of constructivity for complete networks Logical account of existing design styles (SI, DI,...) M. Mendler, Bamberg University HDT 2017 Vienna,
51 Related Work Barros & Johnson: On the equivalence of the ideal arbiter, synchronizer and inertial delay, IEEE TC J. A. Brzozowski & M. Seger: Asynchronous Circuits, Springer 1995; relationship with ternary analysis K.C. Lam, R. K. Brayton: Timed Boolean Functions, Kluwer G. Berry: The Constructive Semantics of Esterel, M. Mendler, T. Shiple, G. Berry: Constructive boolean circuits and the exactness of timed ternary simulation. FMSD M. Mendler, Bamberg University HDT 2017 Vienna,
52 Thank you for your attention! Questions? M. Mendler, Bamberg University HDT 2017 Vienna,
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