3DIC TSV-Stack Electrical Analysis Recommendation & Some Upfront Definitions

Transcription

1 3DIC TSV-Stack Electrical Analysis Recommendation & Some Upfront Definitions Patrick M. Williams Senior Engineer, EDA East Fishkill, NY 3DIC CAD Si2-GSA Workshop October 1, 2009

2 Complex Networks Abound Many Configurations Strata 3 -> SP (Package Connection) Feol/Beol Layers of strata 3 Strata 2 -> S2/SN2 Feol/Beol Layers of strata 2 Test Pads for inividual testing of stratums Strata 1-> S1/SN1 Feol/Beol Layers of strata 1 Feol/Beol Layers of strata 0 Strata 0 -> S0 ( Last Chip to Heat Sink ) Key Micro C4 C4 to Package Representation of TSV Stack ( stacks can be disjoint as well ) Logic Symbol TSV and placement ( paired for redundancy ) ( representation only and not to scale ) 2 3DIC CAD Si2-GSA Workshop October 1, 2009

3 3DIC Recommended Definitions Stratum - essentially an individual chip but with sole purpose to be part of the system stack Strata stratums bonded together to form a stack TSV - is a through silicon via in some sense. Face - the face of a stratum is also called the frontside of a stratum and has physical meaning and related to the side of the wafer that has the BEOL metal. Backside - the backside of a stratum has a physical meaning and describes the side of the wafer that is opposite the frontside, area of active devices Stratum 0 - It occupies the position in the stack that will be closet to the heat sink. Stratum p or Terminal Stratum - is the stratum in a stack that is furthest from stratum 0 and the stratum closet to the package. Stratum n - is a stratum that is neither 0 nor p. Stratum n are the strata types located between p and 0. These stratums must contain both top and bottom side uc4/tsv Adjacent Strata - Adjecent Strata in a stack are numbered consecutively with no negative indices. Down - is the logical direction from stratum i towards stratum i-1. Up - is the logical direction from stratum i towards stratum i DIC CAD Si2-GSA Workshop October 1, 2009

4 3DIC Recommended Definitions ( cont. ) Adjacent strata may make logical signal connections by: TSV head - a connector from stratum n with a TSV tail connector of adjacent stratum or stratum n+1. A TSV head may or may not connect to a TSV tail on the same stratum. When both a TSV head and a TSV tail are present in the same x,y location on a single stratum, and NOT directly connected to each other, this is known as a disjoint TSV. When both TSV head and a TSV tail are present in the same x,y location on a single stratum, and ARE directly connected to each other, this is know as a thru-and-thru or tnt TSV or TSV tnt Adjacent strata may make logical signal connections by: A TSV tnt connector from stratum n with a TSV tail connector of stratum n+1 A TSV tnt connector from stratum n with a TSV head connector of stratum n-1 A TSV tnt connector from stratum n with a TSV tnt connector of strata n-1 and n+1 uc4 - is a micro C4 used to physically form the connection between a TSV head and TSV tail on different strata C4 - is a large C4 that can connect to TSV head connection of the terminal stratum using the redistribution layer on the backside of the terminal stratum Pad - is a physical structure on any stratum that can be probed in lonely stratum model ( not initially part of the stack and typically used for testing ) 4 3DIC CAD Si2-GSA Workshop October 1, 2009

5 Face-up vs. Face down Stack Analysis Face down Face up Carrier/Package Active Devices Of the Strata (red layer) Carrier/Package Should standards reflect/control design implementation of orientation SPFD / SPFU ( Stratum Package Face Down or Face Up ) SN(0-N)FD / SN(0-N)FU ( Stratum N Face Down or Face Up ) Enablement of Stack Level Checks Final stack analysis LVS ( Stack vs Logical Schematic ) Other TSV and uc4 physical checks Technology checks, ESD Analysis 5 3DIC CAD Si2-GSA Workshop October 1, 2009

6 TSV Through Silicon Vias Electrical Perspective Similar to standard vias from electrical perspective but Conductivity stretches in 3 rd dimension across other domains -> The Stack(s) TSV potentially a RLC network but model/table based for TAT of all analysis Proper inclusion of TSV into endless of network configurations between stratums and general communications of the entire stack Logical Verification of entire network connection is critical to assure proper connectivity Consider logical inclusion of TSV model, Verilog or VHDL TSV types should be defined logically and carried throughout schematic/physical design system Assures proper logic validation of entire stack or system Timing, Noise, Power, Clocking, LVS, Testing and ERC analysis a must to assure design robustness of the entire system stack Single EC on one Stratum could effect Multiple Stratums/Chips -> Costly First Time Right Tape Outs -> Critical to reduce mask / fabrication cost of system stack Therefore to reduce development risk and cost implications Recommendation TSV should be an recognized as an design element ranging from Logic Description to LVS TSV element should be a two terminal device with ports/pins as bidirectional Assure proper network inclusion of every TSV within each stratum and across the entire stack against all analysis domains 6 3DIC CAD Si2-GSA Workshop October 1, 2009