Carbon Nanotube Interconnect: Challenges and Solutions for On-Chip Communication in Future Nanoscale ICs

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1 Carbon Nanotube Interconnect: Challenges and Solutions for On-Chip Communication in Future Nanoscale ICs Arthur Nieuwoudt ELEC 527 Presentation Rice University 3/13/2007 Copyright 2007 by Arthur Nieuwoudt. Interconnect and Technology Scaling On-chip communication currently a bottleneck Copper interconnect currently plagued by delay, noise, and reliability problems Electromigration also decreases reliability Problem exasperated by interconnect scaling Smaller wire dimensions Process variations becoming an important reliability concern R. Kumar, Intel Tech. Jour., 2001.

2 Copper Wire Resistivity Increases due to Technology Scaling Resistivity of copper interconnect increases as cross-sectional dimensions decrease Results from surface roughness and grain boundary scattering Dimensions on the order of electronic mean free path Potential solutions in copper technology limited Radical alternative technologies are required Resistivity ( µω cm) Local Interconnect Global Interconnect Bulk Copper Wire Width (nm) International Technology Roadmap for Semiconductors (ITRS), Carbon Nanotubes for On-Chip Interconnect Carbon nanotubes have been proposed as a possible replacement for on-chip interconnect Large current density Relatively low resistivity Small dimensionality Fundamental research questions/challenges: What is the predicted performance and reliability of ICs that utilize nanotubebased interconnect? How can nanotube-based interconnect be realized in a practical manner in the IC manufacturing process? Z. Chen et al., Nanotechnology, 2006.

3 Agenda Properties of carbon nanotubes Predicting the performance of carbon nanotube interconnect Circuit models for carbon nanotube interconnect Investigating the performance and reliability of nanotube-based interconnect Fabrication of nanotube-based interconnect Conclusions Image from A. P. Graham et al., Appl. Phys. A, Types of Carbon Nanotubes Single-walled carbon nanotubes (SWCNTs) Rolled single sheet of graphene Typical diameter: 0.4 nm to 4.0 nm Multi-walled carbon nanotubes (MWCNTs) Nested SWCNTs Distance between layers: 0.34 nm Typical diameter: up to 100 nm Nanotubes that are 4 mm long have been realized 1 Graphene SWCNT MWCNT Vertically Integrated MWCNT S. Li et al., Nano Lett., Images from A. P. Graham et al., Appl. Phys. A, 2005.

4 Single-Walled Carbon Nanotubes: Electrical Properties SWCNTs exhibit either metallic or semiconducting behavior z Depends on chirality z 1/3 of possible nanotube chiralities are metallic Strong carbon-carbon bonds allow large current densities z Nanotube: ~109 A/cm2 z Copper: ~106 A/cm2 z Nanotubes resistant to electromigration Low resistivity (~1 µω-cm) J. Wildoeer et al., Nature, B. Q. Wei et al., App. Phys. Lett., Image courtesy M. Strock Carbon Nanotube Bundles Bundles of SWCNTs have been proposed for interconnect applications Why bundles? z Large current carrying capability of parallel conduction channels z High contact resistance of single SWCNT (~6.5 kω) Bundles of SWCNTs needed to lower overall resistance A. Thess et al., Science, A. Nieuwoudt and Y. Massoud, IEEE T-ED,

5 Interconnect Application Domains Desired nanotube-based interconnect properties depend on application domain Global interconnect (~100s µm) Intermediate interconnect (~10s µm) Local interconnect (<10 µm) Inter-layer vias (~1 µm) Need to design nanotubebased interconnect solutions for each domain Resistive properties Current density Fabrication M. Bohr, Intel Developers Forum, Electrical Modeling of Carbon Nanotube Interconnect Like standard copper interconnect, DC and AC performance of SWCNTs can be abstracted using RLC models Single nanotube RLC model developed by Burke in ,2 Models SWCNTs as a 1-D quantum wire Accounted for quantum capacitance and kinetic inductance Assumes magnetic inductive and electrostatic capacitive coupling between the nanotube and a ground plane Models intrinsic resistance of the nanotube (~6.5 kω) First RLC circuit model for microwave behavior of individual SWCNTs 1 P.J. Burke, IEEE Trans. Nano., P.J. Burke, IEEE Trans. Nano., 2003.

6 Circuit Model for SWCNT Bundle Interconnect Equivalent circuit model for SWCNT bundles Based on model for a single SWCNT from Burke Captures experimentally verified resistance as well as theoretically predicted capacitive and inductive effects Formulations for each model element Diameter-dependent ohmic (R o ) and contact resistances (R i + R c ) Scalable modeling of magnetic (L m and M m ) and kinetic inductance (L k ) Electrostatic (C c and C e ) and quantum capacitance (C q ) Y. Massoud and A. Nieuwoudt, ACM Journal on Emerging Technologies in Computing Systems (JETC), Resistance Modeling Three types of resistance for SWCNTs 1,2 Ohmic (R o ): per unit length beyond mean free path (~4 kω/µm) Contact (R c ): lumped resistance due to metal contacts (0 100s kω) Intrinsic (R i ): lumped resistance due to ballistic conduction (~6.5 kω) High bias voltage can significantly increase resistance due to saturation current (I o ) 2,3 Total bundle resistance 2 nb l b = Bundle length λ ap = Mean-free path of acoustic-phonon scattering V b = Bias voltage I o = Saturation current = number of SWCNTs in bundle 1 J.-Y. Park et al., Nano Lett., Mar A. Nieuwoudt and Y. Massoud, IEEE T-ED, Z. Yao et al., Phys. Rev. Lett., Mar

7 Diameter-Dependent Contact Resistance Contact resistance of SWCNTs depends on nanotube diameter Demonstrated experimentally by W. Kim et al., App. Phys. Lett. 87, Impacts both resistance and maximum current for nanotubes with diameters smaller than 2 nm Increase over nominal contact resistance (R cnom ) can be modeled based on the measured data in [Kim 05] (D rc ): d t = SWCNT diameter > Reduces saturation current (I o ) from 25 to 5 µa when nanotube diameter is 1 nm Can have significant impact of SWCNT bundle resistance W. Kim et al., App. Phys. Lett., A. Nieuwoudt and Y. Massoud, IEEE T-ED, Diameter-Dependent Ohmic Resistance Mean free path of acoustic-phonon scattering (λ ap ) depends on diameter based on experimental and theoretical results 1,2,3 α = scattering rate; v F = Fermi velocity; T = temperature Therefore, the effective diameter-dependent SWCNT ohmic resistivity is 4 λ ap vfdt αt C λ is based on experimental data 1 X. Zhou et al., Phys. Rev. Lett., C. T. White and T. N. Todorov, Nature, H. Suzuura and T. Ando, Phys. Rev. B, A. Nieuwoudt and Y. Massoud, IEEE T-ED, 2006.

8 Effective Ohmic Resistivity Resistivity ( µω cm) Dense Bundle - Diameter Dependent Resistance Sparse Bundle - Diameter Dependent Resistance 22 nm Width 45 nm Width Bulk Copper Nanotube Diameter (nm) SWCNT diameter has large impact on bundle resistance As diameter (D) increases, the number of nanotubes decreases for a given bundle size Resistance increases (~D^2) As D increases, individual nanotube resistance decreases Resistance decreases (~1/D) Therefore, effective resistivity linearly increases Ohmic resistance advantage over copper greatly depends on SWCNT diameter A. Nieuwoudt and Y. Massoud, IEEE T-ED, A. Nieuwoudt and Y. Massoud, IEEE Conf. Nano., Overall Resistance Comparison to Copper: Dense Bundles d t = 1 nm Global interconnect: ohmic res. dominates Local interconnect: contact res. dominates Diameter has a large impact on percentage improvement over copper d t = 1 nm: 61% d t = 2 nm: 22 % A. Nieuwoudt and Y. Massoud, IEEE T-ED, 2006.

9 Capacitance for SWCNT Bundles Three types of capacitance for SWCNTs Electrostatic capacitance between SWCNT and ground (C e ) Electrostatic capacitance between adjacent SWCNTs (C c ) Quantum capacitance (C q ) 1 Electrostatic capacitance has significantly more impact than the quantum capacitance for SWCNT bundles 2 Within SWCNT bundles, C c is small since the nanotubes in the bundle have the same bias voltage Model capacitance between large SWCNT bundles as equivalent conductors 3 Error less than 5 percent when compared to modeling the nanotubes discretely using FastCap 4 and Comsol 1 P.J. Burke, IEEE Trans. Nano., S. Salahuddin et al., IEEE T-ED, Y. Massoud and A. Nieuwoudt, ACM JETC, K. Nabors and J. White, IEEE Trans. CAD, Electrostatic Capacitance Results SWCNT Bundles Parallel Conductors C = 84.3 af/µm C = 85.1 af/µm

10 Inductance for SWCNT Bundles Inductance in global interconnect can impact delay, cross-talk, voltage overshoot, and power consumption Models for SWCNT bundles contain both a magnetic and kinetic inductance 1 Based on model for a single SWCNT from Burke 2 Magnetic inductance: voltage induced by time varying magnetic fields produced by loops of current Kinetic inductance: dependent on the net sum of the kinetic energy of left and right moving electrons in a 1-D quantum wire 1 A. Nieuwoudt and Y. Massoud, IEEE Trans. Nano., P.J. Burke, IEEE Trans. Nano., Kinetic Inductance For a single nanotube (L k ) and a SWCNT bundle (L kb ), the worstcase predicted kinetic inductance values are n b = number of SWCNTs in bundle Kinetic inductance three orders of magnitude larger than the magnetic inductance for a single SWCNT Conflicting experimental results for kinetic inductance Kinetic inductance observed experimentally in [1] for MWCNTs Kinetic inductance not observed experimentally for SWCNTs for frequencies up to 10 GHz in [2] Kinetic inductance will be difficult to observe experimentally due to the small ωl/r Comprehensive analysis of SWCNT bundles for VLSI interconnect applications should include a range of per unit length values of kinetic inductance 1 R. Tarkiainen et al., Phys. Rev. B, Z. Yu and P. J. Burke, Nano. Lett., July 2005.

11 Inductance Modeling: Previous Work Magnetic inductance equal to kinetic inductance for bundle geometries in interconnect applications Magnetic inductance depends on current return paths May not be known a priori Increases model complexity Need modeling solutions for magnetic inductance for SWCNT bundles Number of nanotubes where magnetic and kinetic inductances are equal A. Nieuwoudt and Y. Massoud, IEEE Trans. Nano., Magnetic Inductance Modeling Model SWCNT bundle inductance using the Partial Element Equivalent Circuit (PEEC) method Model each SWCNT as a current carrying filament Calculate self-inductance of nanotube: l t = SWCNT length; d t = SWCNT diameter Calculate mutual inductance between each pair of SWCNTs: R t = l t /s t ; s t = Spacing between SWCNTs A. Nieuwoudt and Y. Massoud, IEEE Trans. Nano., A. Nieuwoudt and Y. Massoud, IEEE Conf. Nano., 2006.

12 Total Loop Inductance Combine partial self-inductance with parital mutual inductance to determine the total loop inductance z Lmat is the partial inductance matrix z it is a vector of the normalized current in each SWCNT Modeling each nanotube discretely not a scalable solution for SWCNT bundles with 100s of individual nanotubes SWCNTs A. Nieuwoudt and Y. Massoud, IEEE Trans. Nano., A. Nieuwoudt and Y. Massoud, IEEE Conf. Nano., Scalable Inductance Modeling Solutions Equivalent width model z Model bundle as a finite number of equivalent conductors z Number of equivalent conductors determine accuracy z Adjust the cross section of each conductor to match the ohmic resistance of an individual SWCNT Equivalent conductivity model z Model bundle as a equivalent conductor with the same dimensions as the bundle z Multiple filaments can improve accuracy z Adjust conductivity to match overall ohmic resistance A. Nieuwoudt and Y. Massoud, IEEE Trans. Nano., A. Nieuwoudt and Y. Massoud, IEEE Conf. Nano.,

13 Speed and Accuracy Results for Simulated Interconnect Geometries CPU Time (s) Maxim um Percentage Error Filament 3 Filament 5 Filament 1 Conductor 2 Conductors 4 Conductors 8 Conductors Equivalent Conductivity Model Equivalent Width Model Self-Inductance Only 1 Filament 3 Filament 5 Filament 1 Conductor 2 Conductors 4 Conductors 8 Conductors Equivalent Conductivity Model Equivalent Width Model Self- Inductance Equivalent conductivity model provides the best speed versus accuracy tradeoff A. Nieuwoudt and Y. Massoud, IEEE Trans. Nano., A. Nieuwoudt and Y. Massoud, IEEE Conf. Nano., Modeling MWCNTs MWCNTs have also been proposed for interconnect and inter-layer via applications 1,2 [2] Can achieve low resistance [3] if the interior shells of the MWCNT are contacted 1,2 Number of conducting channels increases as number and diameter of shells increases 2,3 Large diameter semiconducting nanotubes relatively efficient conductors due to reduced band gap 2,3 1 A. P. Graham et al., Appl. Phys. A, H. J. Li et al., Phys. Rev. Lett., A. Naeemi and J. D. Meindl, IEEE EDL, 2006.

14 Predicting the Performance of SWCNT Bundle Interconnect Delay is an important metric for interconnect performance For global interconnect, wire delay dominates gate delay More important for intermediate length wires as technology scales Current density also important from a reliability standpoint Increases electromigration for copper interconnect For nanotubes with small diameters, saturation current per nanotube is approximately 5 µa Calculate delay and current density using HSPICE simulations 1,2 Driver and load device parameters from 22 nm node of ITRS Extract SWCNT bundle RLC values using equivalent circuit model Compare performance of SWCNT bundles with copper interconnect with the same cross-sectional dimensions 1,2 1 A. Nieuwoudt et al., ASP-DAC, Y. Massoud and A. Nieuwoudt, ACM JETC, Local Interconnect Performance: Current Density Contours: Current per Nanotube in µa Maximum current per nanotube is 3.5 µa Less than saturation current (5 to 25 µa) Similar results for global interconnect Will not pose a reliability issue A. Nieuwoudt et al., ASP-DAC, Y. Massoud and A. Nieuwoudt, ACM JETC, 2006.

15 Local/Intermediate Interconnect Performance: Delay Short bundles largely effected by contact resistance Driver resistance lowers impact of resistance on delay Delay is proportional to percentage of metallic SWCNTs SWCNT bundles may be useful in local interconnect due to their resistance to electromigration A. Nieuwoudt et al., ASP-DAC, Y. Massoud and A. Nieuwoudt, ACM JETC, Global Interconnect Performance: Delay Delay decrease for bundles primarily determined by number of nanotubes (n b ) Potential delay benefits heavily depends on future fabrication technology A. Nieuwoudt et al., ASP-DAC, Y. Massoud and A. Nieuwoudt, ACM JETC, 2006.

16 Impact of Inductance on Delay Inductive effects can have a large impact on delay for global interconnect applications Impacts delay when wide interconnect lines are present SWCNT bundles can lose a percentage of their performance advantage over copper due to inductive effects Inductive effects can also cause significant voltage overshoot With Inductance Without Inductance A. Nieuwoudt et al., ASP-DAC, A. Nieuwoudt and Y. Massoud, IEEE EDL, Magnetic and Kinetic Inductance: Inductive Reactance to Resistance Ratio Inductive reactance to resistance ratio ωl/r determines impact of inductance on impedance (Z = R + jωl) ω(l kin )/R stays at a constant value much less than 1 (assumes worst case kinetic inductance value L kin =4 nh/µm) ω(l mag + L kin )/R varies significantly and can be greater than 1 Kinetic inductance will have a small impact on delay and other inductive effects ω(l mag + L kin )/R f = 10 GHz ω(l kin )/R A. Nieuwoudt et al., ASP-DAC, A. Nieuwoudt and Y. Massoud, IEEE EDL, 2007.

17 Relative Impact of Magnetic and Kinetic Inductance Simulated delay and voltage overshoot with total inductance (L tot = L mag + L kin ) and only magnetic inductance (L mag ) L kin has small impact on SWCNT performance due to inductive effects 5% maximum contribution to delay 2.5% maximum contribution to voltage overshoot Worst case kinetic inductance value assumed (L kin =4 nh/µm) Percentage Difference in Delay (L tot L mag ) Percentage Difference in Voltage Overshoot (L tot L mag ) A. Nieuwoudt et al., ASP-DAC, A. Nieuwoudt and Y. Massoud, IEEE EDL, Potential Impact of Kinetic Inductance in Future Process Technologies The small constant kinetic inductive reactance to resistance ratio (ωl/r) limits the effect of kinetic inductance For f = 10 GHz, ωl/r is approximately 0.03 for kinetic inductance Even less important if kinetic inductance is less than theoretical value Small even for large frequencies in future process technologies Even if significant kinetic inductance is present, its practical implications on delay will be minimal In contrast, magnetic inductance can have a significant impact on SWCNT bundle performance for global interconnect Assumes L k = 4 nh/µm A. Nieuwoudt et al., ASP-DAC, A. Nieuwoudt and Y. Massoud, IEEE EDL, 2007.

18 Impact of Interconnect Manufacturing Process Variations Process variations can impact standard copper interconnect properties Multi-conductor pattern erosion and dishing due to chemicalmechanical polishing Changes conductor thickness Impacts interconnect resistance and capacitance 35% 3-sigma variations are possible in current and future process technologies 1,2 Dielectric thickness variation impact capacitance Variations in conductor width due to lithographic errors also impact interconnect resistance and capacitance Impact of process variations increases as process technology scales Important to understand potential impact of process variations for nanotube-based interconnect solutions ITRS. 2 S. Nassif, CICC, Process Variation for SWCNT Bundles We have identified 10 potential sources of process variations for SWCNT bundle interconnect 1,2 Can be categorized into two types of process variation Intra-bundle variation statistical variation of the properties of each individual nanotube in the bundle Inter-bundle variation statistical variation of the average properties of the nanotubes within the bundle Statistical distribution and amount of variation dependent on parameters in SWCNT bundle manufacturing process 3,4 1 A. Nieuwoudt and Y. Massoud, IEEE T-ED, A. Nieuwoudt and Y. Massoud, ISQED, M. Liebau et al., Fullerenes, Nanotubes, and Carbon Nanostructures, Z. Chen et al., Nanotechnology, 2006.

19 Variation Comparison between SWCNT Bundles and Copper Interconnect Simulated impact of 10 sources of variation Most SWCNT specific sources of variation impact resistance Nanotube-specific sources of variation cause SWCNT bundles to have larger uncertainty in delay Variation increases as process technology scales A. Nieuwoudt and Y. Massoud, IEEE T-ED, A. Nieuwoudt and Y. Massoud, ISQED, Manufacturing Technology for Nanotube-Based Interconnect Solutions Performance analysis highlights the importance of nanotube properties on interconnect performance Bundle geometry, nanotube diameter, and nanotube chirality greatly impact potential performance improvement over copper Need to control manufacturing tolerances to reduce the statistical uncertainty in interconnect performance To effectively realize nanotube-based interconnect solutions, two important issues must be addressed: How can we effectively control nanotube properties during the growth process? How can we efficiently integrate nanotube-based interconnect into the IC manufacturing process?

20 Control over Nanotube Structure and Geometry Control of nanotube diameter distribution during chemical vapor deposition (CVD) process studied extensively 1,2,3 Mean diameter primarily controlled by catalyst particle size and temperature Control of standard deviation also crucial Chirality not controlled in standard CVD process 4 1 C. Cheung et al., J. Phys. Chem. B, G.-H. Jeong et al., J. Appl. Phys., S. Han et al., J. Phys. Chem. B, L. Henrard et al., Eur. Phys. J. B, [1] Separating Metallic Nanotubes Proportion of metallic nanotubes greatly impacts nanotube-based interconnect performance Several potential techniques have been developed 1,2,3 AC dielectrophoresis among the most promising techniques 1,2 Apply an electric field to align SWCNTs nanotubes Tuning the frequency can separate metallic and [1] semiconducting nanotubes Position controlled by electode placement Has the potential to simultaneously generate 1000s of metallic bundles Despite promising recent results, metallic nanotube separation still an open research problem 1 J. Li et al., Appl. Phys. Lett., 2006; 2 R. Krupke et al., Science, 2003; 3 S. R. Lustig et al., J. Phys. Chem. B, 2005.

21 Large Scale Integration of Carbon Nanotube Interconnect Key requirements for the large scale integration of nanotube-based interconnect: Simultaneous parallel growth/placement of nanotubes Reliable growth/placement of nanotubes Connectivity with other interconnect and device components Vertical and horizontal interconnect required Compatible with established IC manufacturing process Large scale manufacturability will be the deciding factor for the adoption of nanotube-based interconnect solutions Vertical Integration of Nanotube Interconnect Vertical interconnect used for inter-layer vias Most mature nanotube-based interconnect fabrication technology exists in this domain Several promising methods have been proposed over the past several years 1,2,3,4 Combine the standard photolithography process with directed growth of nanotubes using CVD Have experimentally achieved similar resistance to tungsten-based vias [3] [2] 1 S. Sato et al., IEEE Interconnect Tech. Conf., Y. Awano, IEICE Trans. Electronics, X. Li et al., Nano Lett., A. P. Graham et al., Small, 2005.

22 Integration of MWCNT-Based Vias Most promising recent results reported by Fujitsu 1,2 Multi-step process Create via holes using standard process (a) Deposit layer of TiN (5 nm) into via holes (a) Deposit size-controlled Co or Ni particles on substrate (a) Grow MWCNTs from catalyst particles during CVD (b) Pattern top layer over via (c) [2] [1] 1 S. Sato et al., IEEE Interconnect Tech. Conf., Y. Awano, IEICE Trans. Electronics, Integration of MWCNT-Based Vias Manufacturing process able to generate vias in holes with diameters as low as 40 nm. Achieved 0.59 Ω resistance for an MWCNT-based via with a diameter of 2 µm (a) 2 µm; (b) 100 nm; (c) 40 nm S. Sato et al., IEEE Interconnect Tech. Conf., Y. Awano, IEICE Trans. Electronics, 2006.

23 Integration of Horizontal Nanotube-Based Interconnect Horizontal integration less mature than techniques for vertical integration Difficult to deposit catalyst particles on vertical surfaces for horizontal growth Results in lower nanotube density 1 Other types of catalysts may hold promise for directionally-directed growth 2 Important fabrication challenges remain for horizontal growth 1 Y. Awano, IEICE Trans. Electronics, Z. Chen et al., Nanotechnology, [1] [2] Conclusions Nanotube-based interconnect solutions can potentially provide a significant performance improvement as technology scales Advantages more pronounced as technology scales Global interconnect and inter-layer vias receive the most benefit Control of nanotube properties in manufacturing process crucial for realizing the potential benefits Bundle geometry, SWCNT diameter, and chirality greatly impact potential performance improvement Need to control manufacturing tolerances to reduce the statistical uncertainty in interconnect performance Large scale integration of carbon nanotube interconnect in IC fabrication is still a critical need Vertical interconnect integration process maturing Horizontal interconnect integration in its early stages of development

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