Digital Systems Design Overview. ENGIN 341 Advanced Digital Design University of Massachuse?s Boston Department of Engineering Dr.

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1 Digital Systems Design Overview ENGIN 341 Advanced Digital Design University of Massachuse?s Boston Department of Engineering Dr. Filip Cuckov

2 Overview 1. IntroducGon to Programmable Logic Devices 2. Field Programmable Gate Arrays (FPGAs) 3. ImplemenGng FuncGons on FPGAs 4. The Zynq System on Chip (SoC) 5. FPGA Design Flow

3 1. Introduc:on to Programmable Logic Devices

4 Programmable Devices Comparison SPLD PLA PAL GAL PROM EPROM EEPROM CPLD FPGA

5 Implemen:ng Func:ons Using ROMs In General

6 Programmable Logic Arrays F 0 = A B + AC F 1 = B + AC F 2 = A B + BC F 3 = AC + B PLA Architecture PLA Example ImplementaGon

7 GAL 22V10 Output Logic Macrocell Detail

8 CPLD Example Xilinx CoolRunner XCR3064XL

9 2. Field Programmable Gate Arrays Field Programmable Logic Block Arrays (FPLBA???) Name due to early PLD- type block usage in Altera devices. Modern FPGAs mostly use LUTs First FPGA: Xilinx XC2000 ca FPGA Market Share (2013 data) 6% 7% 10% 2% 2% 6% 31% FPGAs vs CPLDs 36% Xilinx Altera Actel VanGs Laece Lucent QuickLogic Cypress

10 FPGA Architectures

11 FPGA Programmable Logic Block* Models Usually composed from Look- Up- Tables (LUTs) Actel: MUX based LUT- Based Logic Block MUX- Based Logic Block *As in: basic building blocks

12 Actual FPGA Logic Block Variants Simplified view of sample Xilinx (slice) and Altera (logic element) Logic Blocks

13 FPGA Programmable Interconnect

14 FPGA Programmable I/O Blocks

3. Implemen:ng Func:ons on FPGAs vs Book Chapter 6 George Boole (1815-1864) Boole s Expansion

F 0 + a F 1 Example: F(a,b,c,d,e) = abc e + a b cd + cde + a b F 0 = 0 bc e + 1 b cd + cde + 1 b

15 3. Implemen:ng Func:ons on FPGAs vs Book Chapter 6 George Boole ( ) Boole s Expansion Theorem / Shannon s Expansion or DecomposiGon F(a,b,c,d,e) = a F(0,b,c,d,e) + a F(1,b,c,d,e) = a F 0 + a F 1 Example: F(a,b,c,d,e) = abc e + a b cd + cde + a b F 0 = 0 bc e + 1 b cd + cde + 1 b = b cd + cde + b F 1 = 1 bc e + 0 b cd + cde + 0 b = bc e + cde Claude Elwood Shannon ( )

16 Original Func8on a b c d e F Expansion/Decomposi:on Example Implement F using 4- input LUTs (LUT4) F 0 = b cd + cde + b F 1 = bc e + cde F = a F 0 + a F 1 F 0 (b,c,d,e) b c d e F b c d e LUT4 F 0 b c d e F 1 (b,c,d,e) b c d e F LUT4 F 1 F (a,f 1,F 0,*) a F 1 F 0 * F a LUT4 F * is a LUT input we don t care about

17 Further Decomposi:on F(a,b,c,d,e) = a b F(0,0,c,d,e) + a b F(0,1,c,d,e) + ab F(1,0,c,d,e) + ab F(1,1,c,d,e) = a b F 00 + a b F 01 + ab F 10 + ab F 11 This would be done in order to implement F using 3- input LUT () Same Example: F(a,b,c,d,e) = abc e + a b cd + cde + a b F 00 = 0 0 c e cd + cde = cd + cde F 01 = 0 1 c e cd + cde = 1 F 10 = 1 0 c e cd + cde = cde F 11 = 1 1 c e cd + cde = c e + cde

18 Original Func8on a b c d e F F 00 = cd + cde F 01 = 1 F 10 = cde F 11 = c e + cde F = a b F 00 + a b F 01 + ab F 10 + ab F 11 = ( F 1 + F 2 + F 3 ) + F 4 = F F 4 F 1 (a,b,f 00 ) a b F 00 F F 00 (c,d,e) c d e F Further Decomposi:on Example F 2 (a,b,f 01 ) a b F 01 F F 01 (c,d,e) c d e F F 3 (a,b,f 10 ) a b F 10 F F 10 (c,d,e) c d e F F 4 (a,b,f 11 ) a b F 11 F F 1 F 2 F 3 F F 11 (c,d,e) c d e F F 123 (F 1,F 2,F 3 ) F(F 123,F 4,*) F 123 F 4 * F

19 Diagram and Alterna:ve MUX Implementa:on c d e F 00 a b F 1 c d e F 00 c d e c d e F 01 F 10 a b a b F 2 F 3 F 123 F c d e c d e F 01 F 10 b a F c d e F 11 a b F 4 c d e F 11 b

20 4. The Zynq System on Chip (SoC) Xilinx Zynq System on Chip (SoC) Overview Zynq Overview 16m 25s (OpGonal Answers why was Zynq created) Zynq Architecture 10m 49s (Brief overview of the PS and PL components) Zynq Processing System (PS) 7m 25s (OpGonal Brief overview of Zynq PS) Zynq Programmable Logic (PL) 9m 23s (Brief overview of Zynq PL) Zynq PL Architecture Xilinx 7 Series FPGA Overview 28m 21s (OpGonal - General overview, watch at 1.5x speed) CLB Architecture 21m 52s (A must see, IMDB ragng of 9.1) AddiGonal Xilinx videos and training: h?p:// h?p://

Digilent Zybo Feature FPGA I/O Interfaces Descrip8on Zynq- 7000 AP SoC XC7Z010-1CLG400 USB- UART for programming, serial comm., and power One 10/100/1G Ethernet USB OTG 2.

21 Digilent Zybo Feature FPGA I/O Interfaces Descrip8on Zynq AP SoC XC7Z010-1CLG400 USB- UART for programming, serial comm., and power One 10/100/1G Ethernet USB OTG 2.0 USB- UART bridge 16- bit VGA output Dual role (Input/Output) HDMI I2S CODEC Audio Line- In, Line- Out, microphone Memory 512 Mbyte DDR3 128 Mbit Quad- SPI Flash MicroSD card connector Switches and LEDs 4 Slide switches accessible from PL 4 LEDs accessible from PL 1 LED accessible from PS 4 Push- bu?ons accessible from PL 2 Push- bu?ons accessible from PS 1 Reset bu?on accessible from PL 1 Reset bu?on accessible from PS Clocks Expansion ports one MHz Oscillator for PS One processor- dedicated Pmod connector One dual (analog/digital) Pmod conenctor 4 Pmod connectors

Zynq- 7000 AP SoC XC7Z010-1CLG400 Processing System (PS) 650Mhz dual- core Cortex- A9 processor DDR3 memory controller with 8 DMA channels High- bandwidth peripheral controllers: 1G Ethernet, USB 2.

22 Zynq AP SoC XC7Z010-1CLG400 Processing System (PS) 650Mhz dual- core Cortex- A9 processor DDR3 memory controller with 8 DMA channels High- bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO Low- bandwidth peripheral controller: SPI, UART, CAN, I2C Programmable Logic (PL) Equivalent to ArGx- 7 (7 Series) FPGA: 4,400 logic slices, each with four 6- input LUTs and 8 flip- flops 240 KB of fast block RAM Two clock management Gles, each with a PLL and a MMCM 80 DSP slices Internal clock speeds exceeding 450MHz On- chip analog- to- digital converter (XADC)

23 Xilinx 7 Series FPGA Configurable Logic Block Each CLB is composed of of 2 slices Slices can be of type SLICEL SLICEM Slice features: Real 6- input look- up table (LUT) technology Dual LUT5 (5- input LUT) opgon Distributed Memory and Shiq Register Logic capability Dedicated high- speed carry logic for arithmegc funcgons Wide mulgplexers for efficient uglizagon Xilinx 7 Series FPGA CLB Source: Xilinx 7 Series FPGA CLB User Guide

24 Xilinx 7 Series FPGA Slice Detail The four (A, B, C, and D) 6- input (A1- A6) LUTs provide 2 independent outputs (O5 and O6) The LUTs can implement: Any arbitrarily defined six- input Boolean funcgon OR Two arbitrarily defined five- input Boolean funcgons, as long as these two funcgons share common inputs Slices also contain three mulgplexers used to combine up to four LUTs to implement any funcgon of 7or 8 inputs. F7AMUX: Used to generate 7- input funcgons from LUTs A and B F7BMUX: Used to generate 7- input funcgons from LUTs C and D F8MUX: Used to combine all LUTs to generate 8- input funcgons. SLICEL element shown. See source for SLICEM details.

25 Xilinx 7 Series FPGA Slice Detail Carry Chain(s) Dedicated fast lookahead carry logic can perform fast arithmegc addigon and subtracgon. Cascadable to form wider add/subtract logic. Run upward and have a height of four bits per slice. For each bit, there is a carry MUX and a XOR gate for adding/subtracgng the operands with selected carry bits. The dedicated carry path and carry MUX can also be used to cascade funcgon generators for implemengng wide logic funcgons. Memory Elements Flip- Flops 8 in total 4 are only DFF and 4 can be configured as DFF or Latch Distributed RAM LUTs can be configured as RAM (SLICEM only) Dual- Port 32 x 1bit RAM, up to Single- Port 256 x 1bit RAM

26 PL Other PL Elements Clock Management Mixed- Mode Clock Manager Phase Locked Loop (PLL) DSP Slices 25x18 bit signed mulgplier 48 bit adder/accumulator 25 bit pre- adder Block RAM Dual- port 36KB blocks Programmable FIFO logic PS Zynq Layout Snapshot using Vivado

27 5. FPGA Design Flow Computer Aided Design (CAD) Tools Xilinx Vivado Aldec AcGve- HDL (Free Student EdiGon) FuncGonal SimulaGon Synthesis Post Synthesis SimulaGon Mapping, Placement, RouGng ImplementaGon

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