The Semiconductor Industry s Nanoelectronics Research Initiative: Motivation and Challenges

Transcription

1 The Semiconductor Industry s Nanoelectronics Research Initiative: Motivation and Challenges Dr. Jeff Welser Director, SRC Nanoelectronics Research Initiative IBM Almaden Research Center April, 29

2 Semiconductor Research Corporation: Collaboratively Sponsored University Research The Semiconductor Industry Association (SIA) members have recognized that collaboration among industry, government and academia is the most efficient means of advancing university research capabilities Strong university research is critical to maintain technology innovation Research in new concepts, breakthrough ideas and solutions to problems for which no currently known solutions exist Development of talent pool of scientists and engineers Semiconductor Research Corporation (SRC) has been established to facilitate collaboratively sponsored university research Manages full spectrum of research related to CMOS and beyond technology Awarded the 25 National Medal of Technology For building the world s largest and most successful university research force to support the semiconductor industry... 2

3 Semiconductor Research Corporation A Family of Distinct, Related Program Entities TRC s Global Research Collaboration Ensuring vitality of current industry Focus Center Research Program Breaking down barriers to extend CMOS to its limits Nanoelectronics Research Initiative Beyond CMOS identify next information element Attracting and educating the next generation of innovators and technology leaders Topical Research Collaborations Topic(s) chosen by participants 3

4 Log of the Number of Components Per Integrated Function Moore s Law Electronics, Volume 38, Number 8, April 9, 965 Year 4

5 BIT (bits/s/cm 2 ) Moore s Law: Transistors per chip Binary Information Throughput (BIT) Motivation: density speed functionality Why scaling? To increase the Binary Information Throughput (BIT) BIT.E+2.E+2.E+9.E+8.E+7.E+6 What is the ultimate number of binary transitions per second in a cm 2 chip area? n bit n bit the number of binary states f switching frequency f - a measure of computational capability on device level Year 5

6 Transistor Scaling Dennard, et al., 974 Voltage, V WIRING t ox GATE W Voltage, V / WIRING t ox / GATE W/ n+ source n+ drain n+ source n+ drain L x d L/ p substrate, doping *N A x d / p substrate, doping N A S G D RESULTS: Higher Density: Higher Speed: Lower Power: per circuit Power Density: Constant 6

7 Power Density (W/cm 2 ) CMOS Power Issue: Active vs. Passive Power Power components: Active power Passive power Gate leakage Source - Drain leakage Air Cooling limit Active Power Passive Power.. Gate Leakage G. Polysilicon S Tox=A Gate Gate Length (microns) Gate Length (microns). S D Silicon (SOI) Gate Oxide 7

8 Module Heat Flux(watts/cm 2 ) Has This Ever Happened Before? 4 CMOS 2 Bipolar Start of Water Cooling? Year of Announcement 25 ~ 22: New utilization of technology Multi-core, 3D integration, new memory devices, sensors, etc. > 22?: New technology Nanoelectronics Research Initiative 8

9 Key Systems Transitions Bipolar Frequency CMOS Frequency & density CMOS SoC Integration & density CPU L2 Cache Cost Power CPU 2 Cost Power Multi-Chip Module (MCM) 98 s Power 5 99 s 2 s Blue Gene L Multi-core microprocessor, ASIC library, design tools 24 & Beyond (Note: Figures not to scale) 9

10 System Integration Example: BlueGene/L Cabinet (32 Node boards, 8x8x6) System (64 cabinets, 64x32x32) Node Board (32 chips, 4x4x2) 6 Compute Cards Chip (2 processors) 2.8/5.6 GF/s 4 MB Compute Card (2 chips, 2xx) 5.6/.2 GF/s.5 GB DDR 9/8 GF/s 8 GB DDR 2.9/5.7 TF/s 256 GB DDR 8/36 TF/s 6 TB DDR

11 Cell Processor ~25M transistors ~235mm2 Top frequency >4GHz 9 cores, threads > 256 GFlops > 26 GFlops Up to 25.6GB/s memory B/W Up to 75 GB/s I/O B/W Large design investment (time & money)

12 Heterogeneous Multi-Core Architectures A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Flexible Processors Organization General-purpose CMOS CPU Several application-specific processors/systems May be CMOS hybrids and/or Operate in multiple physical domain MF(n) application-specific processor implementing a specific macro-function (may need specialized devices) MF MF2 MF3 MF4 Key Challenge: Software Applications MF2 MF General Purpose Processor MF5 MF6 MF MF9 MF8 MF7 2

13 Drain Current (log(i D )) New Device Types S < kt/q Molecular devices Gate Voltage (V GS ) Fine-grain PLA Spintronics Double-Gate / FinFET Gate 3D, heterogeneous integration Nanowire Nanotube Quantum cascade Source Drain Embedded memory Time 3

14 27 ITRS Risk Assessment of Potential Future Memory Devices Engineered Tunnel Barrier Fuse / Anti-fuse Nano- Mechanical Electronic Effects Scalability Performance Energy Efficiency Off/On Ratio Operational Reliability Operation Temp. CMOS Technology Compatibility CMOS Architecture Compatibility Ionic Ferroelectric FET Macromolecular Molecular (Emerging Research Devices, Table ERD9) 4

15 27 ITRS Risk Assessment of Potential Future Logic Devices Scalability Performance Energy Efficiency Gain Operational Reliability Operation Temp. CMOS Technology Compatibility CMOS Architecture Compatibility D Structures Channel Replacement Materials Single Electron Transistors Molecular Devices Ferromagnetic Devices Spin Transistors Emerging Research Devices Message: No good options for new logic devices except for FET extensions! (Several options for new memory devices) (Emerging Research Devices, Table ERD) 5

16 What is Information? Source: IBM Information is measure of distinguishability manifested in physical form

17 Particle Location is an Indicator of State 7

18 Electronic switches can be of different nature, but they all have similar fundamentals M V M p n n 8

19 Basic Equations of Two-well Bit a E b What are the requirements/limitations on the height and width the barrier? Boltzmann constraint on minimum barrier height B exp k E B b T x E p t 2 h 2 Heisenberg constraints on minimum barrier width 9

20 Classic Distinguishability: The Boltzmann constraint How small could the energy barrier height be? Barrier control (gate) a E b E b E b a OR E min E bit b Distinguishability requirement: The probability of spontaneous transitions(errors) error<.5 (5%).5 exp( E error min b k exp( B T Eb k T Eb k T B B ln 2 ) 2 )

21 Summarizing, what we have learned so far from fundamental physics ) Minimum energy per binary transition Boltzmann 2) Minimum distance between two distinguishable states x p Heisenberg x min a 2mkT E ln 2 min bit k B T ln 2.5nm(3 K) 3) Minimum state switching time E t Heisenberg t st kt ln s(3 K) 4) Maximum gate density n x 2 min gate 2 cm 2

22 P E chip bit Total Power Dissipation (@E bit = ktln(2)) k n B T E t bit ln [ cm J 2 ] - A Catastrophe! [ J ] [ s] P chip W cm 2 T=3 K The circuit would vaporize when it is turned on! 22

23 FETs approach the kt limit Data compiled by R. Keyes, IBM Research Emeritus 23

24 Can we operate FETs near or below kt?. Conventional Logic: Reduce ½CV 2 toward the kt limit, accept the reduction in switching speed, and use redundancy and error correction to keep the error rate in bounds. (Refrigeration is allowed, but this makes economic sense only if total power dissipation is reduced.) 2. Reversible Logic: Maintain ½CV 2 well above kt, implement adiabatic switching, energy-conserving reversible logic circuits, and energy-recovering (i.e. resonant circuit) power supply to reduce energy losses per switching event to ~ kt or below. 24

25 Adiabatic Charging How much energy must be dissipated to charge a capacitor? ( T >> RC) 25

26 Reversible Logic: Implementation with FETs It is conceptually possible to build general purpose reversible computers with energy dissipation per operation going asymptotically to zero as frequency goes to zero. But, frequency must be reduced by about / to achieve benefits with respect to conventional approaches to CMOS logic. Dissipation of 4 bit ripple counter (D. J. Frank, 995) Need to find right device system architecture combination that results in improved computation / sec / cm 2 / watt 26

27 Devices for Nanoelectronics Circuits Power / Heat Generation is the main limiting factor for scaling of device speed and switch circuit density Scaling to molecular sizes may not yield performance increases Forced to trade-off between speed and density Optimal dimensions for electronic switches should be ~5-5nm Achievable with Si easily within the scope of ITRS projections Going to other materials for FETs will likely achieve only onetime percentage gains Need a new device mechanism or computation architecture to enable a new scaling path 27

28 Beyond CMOS Logic: What to look for? To beat the power problem requires: A device with a lower energy, room temperature switching mechanism or A system that operates out of equilibrium or recovers operation energy as part of the logic computation Required characteristics: Scalability Performance Energy efficiency Gain Operational reliability Room temp. operation Preferred approach: CMOS process compatibility CMOS architectural compatibility Alternative state variables Spin electron, nuclear, photon Phase Quantum state Magnetic flux quanta Mechanical deformation Dipole orientation Molecular state 28

29 Nanoelectronics Research Initiative Milestones 2-24: Defining Research Needs ITRS-Emerging Research Device Technical Working Group NSF-SRC Ind-Academia-Govt Silicon Nanoelectronics and Beyond Workshops SIA Technology Strategy Committee workshops Defined 3 Research Vectors for finding the next switch SIA Board passes resolution for formation of NRI Current Member Companies: Sep 25: First NRI and NRI-NSF Solicitations released Jan 26: Research Programs started Sep 27: NIST joins NRI NRI partnership model highlighted in as sidebar in the National Nanotechnology Initiative (NNI) Strategic Plan (NNCO, /8) 29

30 NRI Mission Statement NRI Mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 22 timeframe. These devices should show significant advantage over ultimate FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology. To meet these goals, NRI pursues five research vectors, focused on discovering and demonstrating new devices and circuit elements for doing computation. Finally, it is desirable that these technologies be capable of integrating with CMOS, to allow exploitation of their potentially complementary functionality in heterogeneous systems and to enable a smooth transition to a new scaling path. 3

31 NRI Primary Research Vectors NEW DEVICE Device with alternative state vector NEW WAYS TO CONNECT DEVICES Non-charge data transfer NEW METHODS FOR COMPUTATION Non-equilibrium systems B A C Out NEW METHODS TO MANAGE HEAT Nanoscale phonon engineering NEW METHODS OF FABRICATION Directed self-assembly devices 3

32 NRI Funded Universities Notre Dame Illinois-UC Michigan Cornell Purdue Penn State UT-Dallas GIT SUNY-Albany GIT Harvard Purdue RPI Columbia Caltech MIT NCSU Yale UVA UC Los Angeles UC Berkeley UC Irvine UC Santa Barbara Stanford U Denver Portland State U Iowa UT-Austin Rice Texas A&M UT-Dallas ASU Notre Dame U. Maryland NCSU Illinois UC Over 3 Universities in 8 States Columbia Harvard Purdue UVA Yale UC Santa Barbara Stanford Notre Dame U. Nebraska/Lincoln U. Maryland Cornell Illinois-UC Caltech

33 NRI Research Centers Leveraging industry, university, and both state & fed government funds, and driving university nanoelectronics infrastructure WIN Western Institute of Nanoelectronics INDEX Institute for Nanoelectronics Discovery & Exploration SWAN SouthWest Academy for Nanoelectronics MIND Midwest Institute for Nanoelectronics Discovery UCLA, UCSB, UC- Irvine, Berkeley, Stanford, U Denver, Iowa, Portland State SUNY-Albany, GIT, RPI, Harvard, MIT, Purdue, Yale, Columbia, Caltech, NCSU, UVA UT-Austin, UT-Dallas, TX A&M, Rice, ASU, Notre Dame, Maryland, NCSU, Illinois-UC Notre Dame, Purdue, Illinois-UC, Penn State, Michigan, UT-Dallas, Cornell, GIT Theme : Spin devices Theme 2: Spin circuits Theme 3: Benchmarks & metrics Theme 4: Spin Metrology Task I: Novel state-variable devices Task II: Fabrication & Selfassembly Task III: Modeling & Arch Task IV: Theory & Sim Task V: Roadmap Task VI: Metrology Task : Logic devices with new state-variables Task 2: Materials & structs Task 3: Nanoscale thermal management Task 4: Interconnect & Arch Task 5: Nanoscale characterization Theme : Graphene device: Thermal, Tunnel, and Spin Theme 2: Interband Tunnel Devices Theme 3: Non-equilibrium Systems Model / Meas. Theme 4: Nanoarchitecture

34 Spin Wave Device Research Multiple PI s 34

35 Multiferroic Materials Achievement: Demonstrated control of ferromagnetism with an electric field applied to a multiferroic. Importance: First step in device development so that control of correlated properties is possible via a simple electric field. R.Ramesh (UC Berkeley) J. Orenstein (UC Berkeley) Next: Electric Field control of spin waves (linked with UCLA and UCSB efforts) 35

36 GMR (%) Molecular Excitons Spintronics Baldo et al (MIT) Quantum Dot Modeling Shur et al (RPI) Quantum Dot Devices Oktyabrsky et al (UAlbany) Spintronic Single SET. Device Electron Operation Spin Devices Global RF Magnetic Field H o e Raynolds et al -i (UAlbany) t ON State In Resonance Ballistic Spin Devices Labella et al (UAlbany) E R = V on g S pump A B S T A B Z Magnetoelectronic Devices Multi bits logic Ross et al (MIT) Z E R = Out of Resonance OFF State Graphene Nanowire Switches Murali and DeHeer (GT) V off g.5 S NiFe6/Cu6/Co8 2 m, 2 nm. S 2R.5 S 2 INSTITUTE FOR NANOELECTRONICS DISCOVERY AND EXPLORATION. S Field (Oe) Reconfigurable One-Dimensional (D) Switch (RDS) Ji Ung Lee (UAlbany) Logical Switches based on Complex Oxides Ahn et al (Yale) Post CMOS Switches The Molecular Conformational Molecular Nanowire Switch: Switches Operating Kaloyeros Principle et al (UAlbany) Employ metal ion location as a gate for switching of charge transport across a self-aligned molecular system Ion location is modulated by interaction between ion-bearing moiety and external signal Graphene based Quantum Devices Charles Marcus (Harvard) Configuration and switching paradigm for interleaved metal/arene atomic relay system 36

37 MOLECULAR EXCITON SPINTRONICS M. Baldo, MIT New idea: Utilizing excitons on molecules for logic Attributes: Easy to generate and convert singlet or triple optically or electrically Decays produce photons, not phonons (less heat generation; recoverable? interconnect?) Long lifetime (seconds) Challenges: Excitons are neutral transport is diffusive Strong spin-dependent exciton interactions INSTITUTE FOR NANOELECTRONICS DISCOVERY AND EXPLORATION Exciton Fission Provides Gain Light Emission is Spin Dependent singlet triplet triplet S T Fluorescence Molecular ground state Concept for a Programmable Logic Operation: NOR gate S Spin disallowed S pump S T Z S pump S T Z A or B = A Singlet quenched by triplet at A. Triplet is excited. Excited triplet decays. No output at Z B A = B = A B Triplet propagates to output (Z). Diffuse to input of next gate 37

38 Polarization Pseudospintronics in Bilayer Graphene A. MacDonald, UT-Austin New theory: Utilize collective behavior of electrons in bilayer graphene to create a switch Theory shows carriers can tunnel as coherent collection between layers at very small voltages Potential for large changes in resistance for small energy Hysteresis for potential latching logic E p Giant Electro-resistance V Collective FET? 38

39 Bi-layer pseudospin Field Effect Transistor (BiSFET) Simulated devices and basic logic gates (SPICE) Inverter with complementary BiSFET design simulated at GHz with 25mV operation at just 2x Landauer limit Bilayer pseudospin Field Effect Transistor (BiSFET): a proposed new logic device S.K. Banerjee, L.F. Register, E.Tutuc, D.Reddy and A. Macdonald., EDL 39

40 Schematic Device Wire Gate Inverter Experimental i i3 i2 Inverted output i o i o R. Cowburn, M. Welland, Room temperature magnetic quantum cellular automata, Science 287, 466, 2 A. Imre, Experimental Study of Nanomagnets for Magnetic QCA Logic Applications, U. of Notre Dame, Ph.D. Dissertation. C C A. Imre, et. al. Magnetic Logic Devices Based on Field-Coupled Nanomagnets, NanoGiga 27. A. Imre, et. al., Majority logic gate for Magnetic Quantum-Dot Cellular Automata, Science, vol. 3, No. 5758, pp , January3, 26. A. Imre, et. al., Majority logic gate for Magnetic Quantum- Dot Cellular Automata, Science, vol. 3, No. 5758, pp , January3, 26. Magnetic Quantum Cellular Automata (MQCA) M. Niemier, Notre Dame

41 25 ITRS Energy / Cost / Area / Delay 4

42 Computing with Alternate State Variables Many different device ideas being considered some likely attributes compared to CMOS: Slower Denser / 3D Local interconnect focused Uniform arrays / sea-of-gates Variability still an issue Switch ~ msecs ~ 8 MIPs ~3W Proof of concept? Architecture / System Question: How to get high computation throughput with these attributes? 42

43 Two Take-aways Power will continue as the principal scaling issue for all IC applications CMOS will continue to scale over at least the next decade, with emphasis on utilizing increasing transistor density over increasing frequency Any new technology must overcome the power / performance limits of a charge-based FET to continue the scaling trend of increased function / dollar Does it offer the prospect of lower energy operation / storage? Does it offer the prospect of non-equilibrium (e.g. ballistic) operation? Does it offer the prospect of energy recovery? 43

44 Computations per second NRI Goal: Continue the Curve... IE+2 IE+9 $ Buys: Discrete Transistor Integrated Circuit Nanotechnology IE+6 IE+3 Electro- Mechanical Vacuum Tube Mechanical IE+ IE-3 IE Source: Kurzweil 999 Moravec

45 Nanoelectronics Research Initiative Jeff Welser, Director Allison Hilbert, Executive Assistant 45