Simulation Study of a Deep-Trench LDMOS with Bilateral Super-Junction Drift Regions

Transcription

1 Simulation Study of a Deep-Trench LDMOS with Bilateral Super-Junction Drift Regions J.J. Cheng, P. Li, W.Z. Chen, B. Yi and X.B. Chen State Key Laboratory of Electronic Thin Films and Integrated Devices of China University of Electronic Science and Technology of China, Chengdu, China chengjunji5@126.com Abstract - An improved structure of the Deep-Trench Lateral Double-diffused Metal-Oxide-Semiconductor transistor (DT-LDMOS) is proposed and studied. The most improvement is that a well-known concept of super-junction is simultaneously applied to the bilateral drift regions beside the deep-trench. Thus, in comparison with the conventional device, the Figure of Merit (FOM, which equals BV 2 /Ron, sp) of the proposed one is increased by about 35.6%, which means a significant reduction of conduction loss is achieved. Another improvement is that the device substrate is changed from silicon-on-insulator to ordinary bulk silicon. Therefore, the highest lattice temperature in a heat dissipation test is reduced from about 373 K for the conventional device to about 312 K for the proposed one, which means a better heat dissipation performance is obtained. All in all, the proposed device not only attains a remarkable improvement in electric characteristics, but also possesses an enhanced reliability. It is believed to be a promising device for the monolithic power ICs with enhanced performance. Keywords - power electronics; power device; LDMOS; deep-trench; super-junction. I. INTRODUCTION The development of power electronics is closely related to the evolution of power devices [1]. Especially in a monolithic high-voltage ICs, power switches are critical to the chip performance. These switches are mostly the Lateral Double-diffused Metal-Oxide-Semiconductor (LDMOS) transistors, which consume large chip area [2]. Recently, a LDMOS based on a technology of Deep- Trench (DT) has gained increasing attention [3], [4]. This device uses a deep and narrow trench filled with dielectric, substituting the traditional semiconductor of silicon, to sustain most of the surface voltage. Since the critical electric-field of dielectric is much higher than that of silicon, the device width can be greatly curtailed. In the past five years, studies on developing the DT- LDMOS were actively carried out [5-11]. The common idea of them is to improve the distribution of electric-field in the drift region. Undoubtedly, the most effective approach to address that, as is well-known, should be the technique of Super-Junction (SJ), which is regarded as a breakthrough to the silicon limit [12-17]. However, although there have been many DT-LDMOS devices This work was supported in part by the Youth Fund of Natural Science Foundation of China under Grant 61643, and in part by the Open Foundation of State Key Laboratory of Electronic Thin Films and Integrated Devices under Grant KFJJ1612 and KFJJ178. x y G S D p + p-body n1 w p1 BCB improved by SJ, the improvements are always limited to be implemented in the drift region on only one side of the DT. Besides, in the prior art, Silicon-On-Insulator (SOI) is commonly used to eliminate the impact of substrate on surface electric-field distribution. The oxide layer in SOI would heavily hinder the heat powered by the device itself from diffusing to a heat sink at the bottom. To address the above issues, an improved DT-LDMOS is proposed in this paper. By applying SJ to the bilateral drift regions on both sides of the DT, the proposed device achieves a significantly improved trade-off between the breakdown voltage (BV) and the specific on-resistance (R on, sp). Moreover, through adopting the ordinary bulk silicon as substrate, not only is the cost economized, but also the reliability concerned about heat dissipation is strengthened. Therefore, the proposal is deemed to be promising for the monolithic power ICs with improved performance and efficiency. The theory and performance of the proposed device will be expounded in the following. II. w t n2 p2 n1 p1 STRUCTURE AND MECHANISM Fig. 1 and depict the cross section views of the proposed and conventional devices, respectively. In these figures, just one cell structure of each device is displayed. It is widely known that an actual device should consist of h1 h2 h3 G S D p + p-body n1 p1 BCB w w w w w 2w w t n2 oxide Figure 1. Cross section views of the proposed and conventional DT-LDMOS devices. There are two structural distinctions, i.e., the right drift regions, and the substrates. Just one cell of each device is displayed here, and the actual device consists of plenty of symmetrical cells in parallel. To analyze the characteristics of the total device, the boundary condition of reflection symmetry is applied at the left and right edges of the cell structure in the simulation. p3 n3 6 MIPRO 18/MEET

2 plenty of symmetrical cells in parallel. Therefore, to analyze the characteristics of the total device, a boundary condition of reflection symmetry, which is applied at the left and right edges of the cell structure, is used in all of the following simulations [18]. Additionally, in the actual device, there should be a junction termination at the edge of the outermost one of the parallel cells [19]. If the device is applied in monolithic ICs, this termination will act as an isolation between the high-voltage power devices and the low-voltage integrated circuits. There are numerous similarities between the two devices. Specifically speaking, at the bottom, both the substrates of p2 and p3 are connected to the ground as well as V. On the surface, there are three coplanar electrodes, which are named as Gate (G), Source (S) and Drain (D) from left to right, respectively. G is connected to a low-voltage control signal switching within the range of ± 1 V. S is always connected to V. D is connected to the highest reverse voltage through a resistance or an inductive load. Between S and D, there is a narrow DT filled with a dielectric of BenzoCycloButene (BCB) which has a low permittivity and a high critical electric-field. When the device is off, the DT sustains most of the reverse voltage between S and D. And due to the critical electric-field as high as 5.3 MV/cm in BCB [], the device width could be pretty small. Besides, on the left side of the DT, there is a drift region in a typical form of SJ, which consists of an n - pillar (n1) and a p - pillar (p1). Through a proper design, as well as making the doping dose of n1 and p1 be equal, the electric flux emitted by the depleted n1 can be fully absorbed by the depleted p1 when the device is off, even though the two pillars are heavily doped. In this case, the SJ drift region can act as an intrinsic region to sustain a reverse voltage as high as possible and, meanwhile, presents an ultra-low onresistance. The drift region in this situation is referred to charge-balanced. There are also two discernible distinctions between the two devices. First, as shown in Fig. 1, the right drift region in the conventional device is a common n-type layer (n3). However, in the proposed one as shown in Fig. 1, this region is improved to have the same SJ form as the left. According to the charge-balanced principle mentioned above, the trade-off between the BV and R on, sp can be further improved by this modification. Moreover, the additional SJ drift region located on the right side of the proposed device has a negligible effect on the dynamic electric characteristics, which will be demonstrated in part IV. The second structural improvement is the alteration of the substrate. In the conventional device, the material of SOI is utilized as substrate to protect the electric-field distribution in the drift regions. However, the oxide layer in SOI will hinder the heat produced by device operations from diffusing to the packaging metal at the bottom. This is dangerous for power device which is continuously working in the case of high-voltage and/or large-current. Hence, to improve the performance of heat dissipation, the substrate is replaced by ordinary bulk silicon in the proposed device. In conclusion, the above structural changes can contribute to the improvements on the tradeoff between the BV and R on, sp, and improve the heat dissipation reliability as well. III. SIMULATION AND OPTIMIZATION Both of the devices shown in Fig. 1 are optimized by using the simulation tool of MEDICI. Simulation models include CONSRH, CONMOB, FLDMOB, SRFMOB2, and IMPACT.I. In the turn-off process, the impact ionization rate (α) increases along with the drain voltage. When the integral of α equals 1, the device is broken and the drain voltage at this time is the BV. In the on-state, when the gate voltage and the drain voltage are fixed at 1 V and.5 V, respectively, the on-resistance multiplied by the device width of 13 m is R on, sp. More details of the simulation methods can be found in [18]. Before the simulation, several justifiable settings of the device size are assigned. In detail, the pillar width (w) is set to 2 m, and the DT depth (h 1) is set to 25 m. The thickness of n2 (h 2) is set to 2 m, and the thickness of the oxide in the conventional device (h 3) is set to 3 m. Besides, the thickness of the substrates of p2 and p3 are set to be sufficient for accurate simulations. In other words, p2 and p3 are thick enough to avoid being completely depleted at the highest reverse voltage. In the proposed device, from the bottom up, the key parameters need to be optimized include the doping concentrations of p2 (N p2) and n2 (N n2), the DT width (w t), and the doping concentrations of n1 (N n1) and p1 (N p1), respectively. The processes of optimization for the proposed device will be performed in this order. To shield the complex interplay among the parameters, some necessary assumptions are made. For instance, to analyze the influence of N p2 on BV without disturbances, we set the DT to have a sufficient width of 1 m, and set the drift regions consisting of n1 and p1 to be intrinsic to approach the ideal charge-balanced status even without lateral electric-field between the pillars. It should be indicated that whether the drift region is SJ or not, the narrow DT would act as a capacitor and induce charges in the silicon nearby it. Hence, a p - pillar and an n - pillar both with a variation vertical doping should be assigned to the left and the right nearby the DT, respectively. Namely, the left p1 and the right n1 or n3 should be always doped. Because the concept of variation vertical doping in such a device is not the issue studied in this paper, it will be ignored and not be reiterated below Concentration of p2 (1 14 cm -3 ) (c) (d) Figure 2. Optimization of N p2 for the proposed device. When N p2 is set to cm -3, cm -3 and cm -3, the BV is 491 V, 922 V and 551 V, respectively, and the potential distribution at the moment of breakdown is shown as, and (c), respectively. In these figures of potential distribution, the black contours are 5 V/div, and the white lines are the edges of depleted regions. (d) BV vs. N w t = 1 m; N n2 = cm -3 ; n1 and p1 are intrinsic. Taking into account the simulation results, a value of cm -3 is selected for N p2. MIPRO 18/MEET 61

3 Concentration of n2 (1 15 cm -3 ) Trench width wt ( m) Figure 3. Influence of N n2 on BV for the proposed w t = 1 m; N p2 = cm -3 ; n1 and p1 are intrinsic. Effect of w t on BV for the proposed N p2 = cm -3 ; N n2 = cm -3 ; n1 and p1 are intrinsic. In the proposed device, if N p2 is too large or too small, the BV will be impaired. This is because when the device is turning off, the potential of S and G maintains V, and the potential of D is increased gradually. If N p2 is quite large, according to Poisson s equation, a heavily doped substrate will provide plentiful charges to deplete n2 completely at a low reverse voltage, and then the potential of n2 will be clamped. As a result, the highest reverse voltage is sustained mainly by the right drift region and, therefore, the BV is reduced, as demonstrated by Fig. 2(c). Otherwise, if N p2 is quite small, the reverse voltage will be sustained mainly by the left drift region, and the BV will be reduced as well, as illustrated in Fig. 2. Based on the simulation results as shown in Fig. 2(d), a value of cm -3 is selected for N p2. With the optimized N p2 and the same assumptions that w t = 1 m and that the drift regions are intrinsic, the impact of N n2 on BV is analyzed. As shown in Fig. 3, the BV is increased along with the decrease of N n2. However, since n2 is the current-conductive layer, the decreased N n2 will result in an increased R on, sp. For a comprehensive consideration of the trade-off between the BV and R on, sp, a value of cm -3 is chosen for N n2. Fig. 3 displays the effect of w t on BV, when both of N p2 and N n2 are optimized, and the drift regions are still intrinsic. It is noted that when w t is reduced to be less than 5 m, the BV is sharply decreased. This is because when the DT is so narrow, the lateral electric-field in it is enormous. According to the equation of continuity of electric flux, this electric-field is decreased proportionally into the silicon nearby the dielectric, where the reducing factor is equal to the relative permittivity of silicon Concentration of n1 (1 15 cm -3 ) FOM (MW/cm 2 ) Concentration of p2 (1 14 cm -3 ) divided by that of the dielectric. However, although the electric-field is decreased, it is still larger than the critical electric-field of silicon, and can lead to breakdown. Otherwise, when w t is larger than 5 m, the breakdown will mainly be decided by the electric-field distribution in bulk silicon. Since n2 has a heavy doping, the voltage drop across it is small, and most of the reverse voltage is sustained by the bilateral SJ drift regions. Therefore, further increase of w t will barely benefit the BV, but only increases the cell pitch and raises R on, sp. Based on above, a value of 5 m is chosen for w t. In this case, the aspect ratio of the DT is (5:1). We conducted an experiment to confirm this aspect ratio is feasible. As illustrated in Fig. 4, an aspect ratio of (27.44 m: 5.52 m) which approximates to the required one is obtained. After N p2, N n2 and w t were optimized, the influence of N n1 and N p1 is analyzed. According to the charge-balanced concept, N n1 should equal N p1. Meanwhile, an increased N n1 contributes to a smaller R on, sp, but deteriorates the BV, due to the enhanced electric-field between n1 and p1, as indicated in Fig. 5. The main purpose of this work is to improve the trade-off between the BV and R on, sp, so a well-known Figure of Merit (FOM) is introduced as FOM = (BV 2 / R on, sp) [7]. Depending on the simulation results, the optimized N n1 as well as the one associated with the highest FOM is found to be cm -3. Since each of the above steps is based on some assumptions and actually there is a complex interplay among them, a fine-tuning of N p2 is supplemented, as shown in Fig. 5. Finally, the optimized structure for the proposed device gains a FOM of about MW/cm 2 with a BV of about 892 V FOM = MW/cm 2 Figure 5. Impact of N n1 on BV (the left axis) and on FOM (the right axis) for the proposed N p2 = cm -3 ; N n2 = cm -3 ; w t = 5 m. Fine-tuning optimization of N p2 for the proposed N n2 = cm -3 ; w t = 5 m; N n1 = cm -3. Figure 4. Scanning Electron Microscope photo of the deep-trenches. The DT is etched by using an Inductively Coupled Plasma (ICP) technique. The aspect ratio obtained in the experiment is about (27.44 m : 5.52 m), which is approximate to the required value of 5: Concentration of p3 (1 14 cm -3 ) Concentration of n3 (1 14 cm -3 ) Figure 6. Opitimaztion for the conventional device. Impact of N p3 on N n1 = cm -3 ; N n2 = cm -3 ; w t = 5 m. Effects of N n3 on BV (the left axis) and on FOM (the right N n1 = cm -3 ; N n2 = cm -3 ; w t = 5 m FOM (MW/cm 2 ) 62 MIPRO 18/MEET

4 TABLE I. Parameter OPTIMIZED PARAMETERS Value Doping concentration of n1 (N n1) cm -3 Doping concentration of n2 (N n2) cm -3 Doping concentration of n3 (N n3) cm -3 Doping concentration of p1 (N p1) cm -3 Doping concentration of p2 (N p2) cm -3 Doping concentration of p3 (N p3) cm -3 Width of the deep-trench (w t) 5. m The conventional device is optimized as consistently as the proposed one. The optimization process is concisely presented in Fig. 6. As mentioned, the structural distinctions between the conventional and the proposed devices are the right drift region and the substrate. Therefore, it can be concluded from Fig. 6 that, when the doping concentration of p3 (N p3) equals cm -3 and the doping concentration of n3 (N n3) is cm -3, the conventional device is optimized, and achieves a FOM of about MW/cm 2 with a BV of about 915 V. The optimized parameters are listed in Table I. It should be explained that all of them can be fabricated in reality. For example, for the proposed device, N p2 of cm -3 can be realized by using an epitaxial silicon wafer which is doped by boron and with the resistivity of about 46 Ω cm. Based on this wafer, series of epitaxies and ion implantations are performed to form n2 and the pillars of n1 and p1. After that, a deep-trench is etched and filled by the chemical vapor deposition (CVD). At last, after some basic common CMOS processes, the proposed device can be fabricated. All of the above processes have been commonly adopted to fabricate SJ or DT devices in industry. Besides, the material of BCB is also a feasible dielectric for power devices. Its properties and characteristics have been studied by many previous studies. For example, the filling process for it and the influence of the interface between the BCB and silicon have been experimentally studied in [21]. Hence, it is a reasonable inference that the proposal is feasible. IV. CHARACTERISTICS AND COMPARISON To compare the device characteristics, such as the static and dynamic electric characteristics, we substitute the optimized parameters into a series of simulations. The comparison results are expounded as following: A. Static electric characteristic Since the drift region of n2 is heavily doped, the voltage drop across it is small, and most of the reverse voltage is sustained by the SJ drift regions beside the DT. As shown in Fig. 7, at an approximate reverse voltage of about V, the two devices both present uniform distribution of potential contours in the right drift region. However, it should be pointed out that in the conventional device, N n3 is only about cm -3. In other words, it achieves the BV of about 915 V through sacrificing the other performance as well as increasing the R on, sp. Figure 7. Potential distribution at the moment of breakdown for the proposed and conventional devices. In the right drift region of them, the potential contours are both distributed uniformly. But the doping concentrations there have a great different. N n1 for the proposed device is over tenfold larger than N n3 for the conventional one. Figure of Merit (MW/cm 2 ) [15] in 16 [17] in 17 [16] in 16 [14] in 15 [6] in 13 [9] in 14 Figure 8. Comparison of the FOM performance between some recently reported LDMOS and the proposed device, where the FOM achieved in this work is the highest. Therefore, the FOM for it is just about MW/cm 2. For the proposed device, N n1 has reached cm -3. Meanwhile, due to the application of charge-balanced, the breakdown voltage still achieves 892 V. Therefore, the FOM of the proposed device is enhanced to about MW/cm 2, which is increased by 35.6% in comparison with that of the conventional one. Fig. 8 exhibits the FOM performance of numerous LDMOS published recently, including the DT-LDMOS improved by some other techniques [5]-[11] and the devices of lateral SJ LDMOS [14]-[17]. Evidently, due to a further application of SJ, i. e., due to the addition of the right SJ drift region, the proposed device achieves a higher FOM than those in the prior art. More specifically, as shown in Fig. 9, the relationship between the BV and R on, sp of DT-LDMOS is further improved by this work. The curve marked with silicon limit was proposed by B.J. Baliga in 1989, and has been broken through by X.B. Chen with his patent of superjunction [12]. However, since SJ has not been perfectly applied to a LDMOS yet, this silicon limit continues to be applicable for most of the LDMOS. Taking advantage [1] in 15 [7] in 14 [5] in 12 [8] in 14 [11] in 15 This work MIPRO 18/MEET 63

5 Specific on-resistance (m cm 2 ) 6 4 "Silicon limit"[13] [8] [5] [9] [11] [7] [6] Temperature (K) Time ( s) Figure 9. Comparison of the BV ~ R on, sp relationship between some recently published DT-LDMOS and the devices studied in this work, where the relationship achieved in the proposed device is optimum. of the DT, the referenced structures of DT-LDMOS, especially the latest published one with a variable-k dielectric trench and the conventional device simulated in this work, all achieve a lower R on, sp than that in the silicon limit at the same BV. In other words, these devices all overcome the silicon limit. Nevertheless, in comparison with them, the proposed device achieves a much better trade-off between the BV and R on, sp, which means the static electric characteristic of DT-LDMOS is optimized to a new level. Drain voltage (V) Drain voltage (V) ns 1.5 ns Time (ns) 19 ns 18 ns Time (ns) Figure 1. Comparisons of the turn-on and turn-off processes, where the two devices are both connected to a DC bus-voltage (V DD) of 5 V with the same resistance load. The control signal as well as the gate voltage triggers the device at the time of ns. The turn-on time and turn-off time are computed as the time for output voltage varying from 9% to 1% and from 1% to 9% of V DD, respectively Drain current density ( A/ m) Drain current density ( A/ m) Figure 11. Highest lattice temperature extracted from the heat dissipation testing, where a thermal resistance is assumed at the device bottom, and the devices are repeatedly switching in a high-power case. B. Dynamic electric characteristic According to the simulation results as shown in Fig. 1, the turn-on time for the conventional and proposed devices is 1.5 ns and.77 ns, and the turn-off time for them is 18 ns and 19 ns, respectively. The comparison reveals the structural changes proposed in this paper have a negligible effect on the dynamic electric characteristics. Actually, influence of a SJ drift region on switching performance is usually referred to a turn-off delay time. At the beginning of turn-off, charges are gradually taken away from the drift region. n1 and p1 with a depleted region between them are acting as a differential capacitance (C SJ). Since the depleted region has a large area, and is thin at this moment, C SJ is tremendous. The device should charge C SJ first and, therefore, there is a delay time before the reverse voltage is rapidly increased. The standard calculation of turn-off time is to compute the time for output voltage varying from 1% to 9% of the highest reverse voltage, and it can be observed from Fig. 1 that, the incipient reverse voltage during the delay time (from ns to about 1 ns) is small. Therefore, the delay time caused by the SJ drift region affects neither the power loss nor the turn-off time. As a result, although there is larger turn-off delay time for the proposed device, due to the additional SJ drift region on the right, the switching performance is actually not affected. C. Heat dissipation characteristics Since the surface of power devices is covered by packaging adiabatic materials, the dissipation of the heat powered by the devices themselves mainly relies on a heat sink at the bottom. However, in the conventional device as shown in Fig. 1, the oxide layer in SOI obviously hinders heat from flowing to the bottom and, therefore, leads to a threat to the device reliability. To cope with that, we change the substrate in the proposed device to ordinary bulk silicon, as shown in Fig. 1. To illustrate the advantage of this modification, a simulation of heat dissipation testing is performed. In the testing, the ambient temperature is set to 3 K. The thermal conductivity of the oxide and BCB are assumed according to the references [18], []. The thermal boundary conditions for this non-isothermal simulation include a finite thermal resistance between the device and a heat sink. This thermal resistance is assumed to be MIPRO 18/MEET

6 Figure 12. Comparison of the 3-D temperature distributions between the proposed and conventional devices. The distributions are both extracted at the tenth circle in the high-power heat dissipation test. K m/w and is located at the bottom of the device, which is defined according to the realistic application of an 8- lead standard Small Outline Package (SOIC-8) with a chip area of about 4 mm 2. Under these conditions, both the proposed and conventional devices are forced to work in a high-power situation, i.e., they are connected to a 4 V bus-voltage with an on-state current of 14 A, and repeatedly switch in a frequency of 1 khz. In Fig. 11, it can be seen that during the testing, the highest lattice temperature for the conventional device is continuously increased, while that for the proposed device gradually reaches a stabilization. After ten circles, as well as at the time of 1 s, the highest lattice temperature for the conventional device is raised to about 373 K, while that for the proposed device is only about 312 K. This can be intuitively observed by the temperature distribution at this time. Evidently, as shown in Fig. 12, the oxide layer in the conventional device badly hinders the heat dissipation, and in the proposed device, the heat can swimmingly flow to the heat sink at the bottom, which makes the device more reliable. V. CONLUSION In this paper, an improved structure of DT-LDMOS is proposed and studied by simulations. Through the application of the bilateral SJ drift regions and the modification of the substrate, the proposed device not only achieves a significant improvement in electric characteristics, but also possesses an enhanced heat dissipation reliability. The simulation results demonstrate the advantages of the proposal. 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