CD4541B (CERDIP, PDIP, SOIC)

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查询 CD44 供应商 CD44 Data sheet acquired from Harris Semiconductor SCHS0 COS Programmable Timer High Voltage Types (0V Rating) [ /Title (CD4 4) /Subject CO Proramable imer igh oltge ypes 0V atng)) /utho

1 查询 CD44 供应商 CD44 Data sheet acquired from Harris Semiconductor SCHS0 COS Programmable Timer High Voltage Types (0V Rating) [ /Title (CD4 4) /Subject CO Proramable imer igh oltge ypes 0V atng)) /utho () /Keyords Haris emionuctor, D400, etal ate, OS pdip, erdip, il, iliary, il Features Low Symmetrical Output Resistance, Typically 00Ω at = V uilt-in Low-Power RC Oscillator Oscillator Frequency Range DC to 00kHz External Clock (pplied to Pin ) can be Used Instead of Oscillator Operates as N Frequency Divider or as a Single- Transition Timer Q/Q Select Provides Output Logic Level Flexibility UTO or STER RESET Disables Oscillator During Reset to Reduce Power Dissipation Operates With Very Slow Clock Rise and Fall Times Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range Symmetrical Output Characteristics 00% Tested for Quiescent Current at 0V V, 0V, and V Parametric Ratings eets ll Requirements of JEDEC Standard No., Standard Specifications for Description of Series COS Devices Ordering Information PRT NUER Pinout TEP. RNGE ( o C) PCKGE PKG. NO. CD44F - to 4 Ld CERDIP F4. CD44E - to 4 Ld PDIP E4. CD44H - to Chip - CD44 - to 4 Ld SOIC 4. Description CD44 (CERDIP, PDIP, SOIC) TOP VIEW R TC C TC R S NC UTO RESET STER RESET 4 CD44 programmable timer consists of a -stage binary counter, an oscillator that is controlled by external R-C components ( resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitions and can also be reset via the STER RESET input. The output from this timer is the Q or Q output from the th, 0th, th, or th counter stage. The desired stage is chosen using time-select inputs and (see Frequency Select Table). The output is available in either of two modes selectable via the ODE input, pin 0 (see Truth Table). When this ODE input is a logic, the output will be a continuous square wave having a frequency equal to the oscillator frequency divided by N. With the ODE input set to logic 0 and after a STER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after N- counts and remains in that state until another STER RESET pulse is applied or the ODE input is set to a logic. Timing is initialized by setting the UTO RESET input (pin ) to logic 0 and turning power on. If pin is set to logic, the UTO RESET circuit is disabled and counting will not start until after a positive STER RESET pulse is applied and returns to a low level. The UTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, should be greater than V. The RC oscillator, shown in Figure, oscillates with a frequency determined by the RC network and is calculated using: f = R TC C TC NC ODE Q/Q SELECT Where f is between khz and 00kHz and R S 0kΩ and R TC V SS 7 OUTPUT CUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation 99 File Number 7.

2 CD44 Functional Diagram Functional lock Diagram R TC C TC R S R R ODE Q/Q SELECT 0 9 Q = PIN 4 V SS = PIN 7 R N P Q R S C TC R TC OSC R -STGE COUNTER R N P 0 OR -STGE COUNTER R OF UX 0 ODE 9 Q/Q SELECT UTO RESET PWR ON RESET NUL RESET = 4 V SS = 7 NC = 4, FIGURE. V SS ll inputs are protected by COS Protection Network. FREQUENCY SELECTION TLE NO. OF STGES N COUNT N R S C TC INTERNL RESET TO CLOCK CKT TRUTH TLE STTE PIN 0 R TC uto Reset On uto Reset Disable aster Reset Off aster Reset On 9 Output Initially Low fter Reset (Q) Output Initially High fter Reset (Q) FIGURE. RC OSCILLTOR CIRCUIT 0 Single Transition ode Recycle ode

3 CD44 bsolute aximum Ratings DC Supply - Voltage Range, Voltages Referenced to V SS Terminal V to +0V Input Voltage Range, ll Inputs V to +0.V DC Input Current, ny One Input ±0m Device Dissipation Per Output Transistor For T = Full Package Temperature Range (ll Package Types) mW Operating Conditions Temperature Range T o C to o C Supply Voltage Range For T = Full Package Temperature Range.....V (in), V (Typ) Thermal Information Thermal Resistance (Typical, Note ) θ J ( o C/W) θ JC ( o C/W) PDIP Package N/ CERDIP Package SOIC Package N/ aximum Junction Temperature (Plastic Package) o C aximum Storage Temperature Range (T STG )... - o C to 0 o C aximum Lead Temperature (Soldering 0s) t Distance /in ± /in (.9mm ±0.79mm) from case for 0s aximum o C (SOIC - Lead Tips Only) CUTION: Stresses above those listed in bsolute aximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ J is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications CONDITIONS LIITS T INDICTED TEPERTURES ( o C) PRETER V O (V) V IN (V) (V) IN TYP X UNITS Quiescent Device Current, (Note ) I DD (ax) - 0, µ - 0, µ - 0, µ - 0, µ Output Low (Sink) Current l OL (in) 0.4 0, µ 0. 0, µ. 0, µ Output High (Source) Current, I OH (in) 4. 0, m. 0, m 9. 0, m. 0, m Output Voltage: Low-Level, V OL (ax) - 0, m - 0, m - 0, m Output Voltage: High-Level, V OH (in) - 0, m - 0, m - 0, m Input Low Voltage, V IL (ax) 0., V, V., V

4 CD44 Electrical Specifications (Continued) CONDITIONS LIITS T INDICTED TEPERTURES ( o C) PRETER V O (V) V IN (V) (V) IN TYP X UNITS Input High Voltage, V IH (in) 0., V, V., V Input Current, l IN (ax) - 0, ±0. ±0. ± ± - ±0 - ±0. µ NOTE:. With UTO RESET enabled, additional current drain at o C is: 7µ (Typ), 00µ (ax) at V; 0µ (Typ), 0µ (ax) at 0V; 0µ (Typ), 00µ (ax) at V Dynamic Electrical Specifications T = o C, Input t r, t f = 0ns, C L = 0pF, R L = 00kΩ PRETER SYOL (V) IN TYP X UNITS Propagation Delay Times Clock to Q ( ) t PHL, t PLH µs µs µs ( ) t PHL, t PLH -.0 µs µs µs Transition Time t THL ns ns ns t THL ns ns - 0 ns STER RESET, CLOCK Pulse Width ns ns - ns aximum Clock Pulse Input Frequency f CL -. - Hz Hz - - Hz aximum Clock Pulse Input Rise or Fall time t r,t f, 0, Unlimited µs 4

CD44 Digital Timer pplication positive pulse on STER RESET resets the counters and latch. The output goes high and remains high until the number of pulses, selected by and, are counted.

5 CD44 Digital Timer pplication positive pulse on STER RESET resets the counters and latch. The output goes high and remains high until the number of pulses, selected by and, are counted. This circuit is retriggerable and is as accurate as the input frequency. If additional accuracy is desired, an external clock can be used on pin. setup time equal to the width of the one-shot output is required immediately following initial power up, during which time the output will be high ( ) 0 INPUT R TC C TC R S R R OUTPUT t ( ) - 9 (.9 -.) FIGURE. DIGITL TIER PPLICTION CIRCUIT NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (0 - inch). FIGURE 4. DIENSIONS ND PD LYOUT FOR CD44

6 CD44 Dual-In-Line Plastic Packages (PDIP) INDEX RE SE PLNE SETING PLNE D -C- -- N N/ D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and etric dimensions, the inch dimensions control.. Dimensioning and tolerancing per NSI Y Symbols are defined in the O Series Symbol List in Section. of Publication No Dimensions, and L are measured with the package seated in JEDEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. old flash or protrusions shall not exceed 0.00 inch (0.mm).. E and e are measured with the leads constrained to be perpendicular to datum -C-. 7. e and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E., E., E., E., E4. will have a dimension of inch ( mm) (0.) C L S e C E C L e C e E4. (JEDEC S-00- ISSUE D) 4 LED DUL-IN-LINE PLSTIC PCKGE INCHES ILLIETERS SYOL IN X IN X NOTES C D D E E e 0.00 SC.4 SC - e 0.00 SC 7. SC e L N Rev. 0 /9

7 CD44 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) SE PLNE SETING PLNE S b ccc bbb S b C - C - S D e D S NOTES:. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. Dimensions b and c apply to lead base metal only. Dimension applies to lead plating and finish thickness. 4. Corner leads (, N, N/, and N/+) may be configured with a partial lead paddle. For this configuration dimension b replaces dimension b.. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimension Q shall be measured from the seating plane to the base plane. 7. easure dimension S at all four corners.. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per NSI Y Controlling dimension: INCH. E L c e/ S D S aaa C - LED FINISH SE ETL b (b) SECTION - -D- -- Q -C- -α S e c D S (c) F4. IL-STD- GDIP-T4 (D-, CONFIGURTION ) 4 LED CERIC DUL-IN-LINE FRIT SEL PCKGE INCHES ILLIETERS SYOL IN X IN X NOTES b b b b c c D E e 0.00 SC.4 SC - e 0.00 SC 7. SC - e/ 0.0 SC. SC - L Q S α 90 o 0 o 90 o 0 o - aaa bbb ccc , N 4 4 Rev. 0 4/94 7

8 Small Outline Plastic Packages (SOIC) CD44 N INDEX RE e D 0.(0.00) C E C- SETING PLNE S H 0.(0.00) 0.0(0.004) NOTES:. Symbols are defined in the O Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per NSI Y Dimension D does not include mold flash, protrusions or gate burrs. old flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width, as measured 0.mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.04 inch). 0. Controlling dimension: ILLIETER. Converted inch dimensions are not necessarily exact. α L h x 4 o C 4. (JEDEC S-0- ISSUE C) 4 LED NRROW ODY SLL OUTLINE PLSTIC PCKGE INCHES ILLIETERS SYOL IN X IN X NOTES C D E e 0.00 SC.7 SC - H h L N α 0 o o 0 o o - Rev. 0 /9

9 IPORTNT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. ll products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTIN PPLICTIONS USING SEICONDUCTOR PRODUCTS Y INVOLVE POTENTIL RISKS OF DETH, PERSONL INJURY, OR SEVERE PROPERTY OR ENVIRONENTL DGE ( CRITICL PPLICTIONS ). TI SEICONDUCTOR PRODUCTS RE NOT DESIGNED, UTHORIZED, OR WRRNTED TO E SUITLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTES OR OTHER CRITICL PPLICTIONS. INCLUSION OF TI PRODUCTS IN SUCH PPLICTIONS IS UNDERSTOOD TO E FULLY T THE CUSTOER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 99, Texas Instruments Incorporated

CD74HC147, CD74HCT147

Data sheet acquired from Harris Semiconductor SCHS149 September 1997 CD74HC147, CD74HCT147 High Speed CMOS Logic 10-to-4 Line Priority Encoder [ /Title (CD74 HC147, CD74 HCT14 7) /Subject (High Speed CMOS