Pipelined ADC Design. Sources of Errors. Robust Performance of Pipelined ADCs

Transcription

1 Pipelined ADC Design Sources of Errors Robust Perforance of Pipelined ADCs 1

2 Review Standard Pipelined ADC Architecture V ref CLK V in S/H Stage 1 Stage 2 Stage 3 Stage k Stage -1 Stage n 1 n 2 n 3 n k n -1 n Pipelined Assebler Vres 1 Vres 2 Vres 3 Vres k Vres n-1 D n 2

3 Pipelined Converter Stage V ink Clk Stage k Vref V resk n k V INk S/H AMP V RESk C LK ADC DAC wn k V REF D OUTk 3

4 Pipelined Converter Stage V INk S/H AMP V RESk C LK ADC DAC wn k V REF D OUTk Generally cobined into one switched-capacitor gain stage 4

5 Review Siplified Pipelined Stage V INh AMP V RESh ADC DAC n 1 V REF D OUTh Generally oitted on last stage 5

6 Modeling of a Pipelined ADC Assue all nonlinearities can be neglected 6

7 Pseudo-Static Tie-Invariant Modeling of a Linear Pipelined ADC Paraaterization of Stage k Aplifier Closed-Loop Gain Fro input 1k Fro DAC 2k Fro offset 3k Offset Voltage - V OSk DAC V DACki ADC Offset Voltages - V OSAki Out-Range Circuit (if used and not included in ADC/DAC) DAC Levels - V DACBki Aplifier Gain 4k V INk ADC n 1 D OUTk DAC AMP V REF V RESk 7

8 Pseudo-Static Tie-Invariant Modeling of a Linear Pipelined ADC Paraeterization of Input S/H Stage V IN S/H V IN1 C LK V = V + in1 10 in 20 V OS0 8

9 Pseudo-Static Tie-Invariant Modeling of a Linear Pipelined ADC V INk AMP V RESk ADC DAC n 1DOUTk V REF For notational convenience, assue 1 bit/stage V = V + d V + RESk 1k ink k DACk 2k 3k V OSk 9

10 Matheatical Representation of the n Pipelined Stages V = V + d V + RES1 RES in1 in2 1 2 DAC1 V = V + d V + DAC V V OS1 OS2 V = V + d V + RESk 1k ink k DACk 2k 3k V OSk V = V + d V + RESn 1n inn n DACn 2n 3n V OSn 10

11 Matheatical Representation of the Pipelined ADC V = V + in1 10 in 20 V OS0 V = V + d V + RES1 RES in1 in2 1 2 DAC1 V = V + d V + DAC V V OS1 OS2 V = V + d V + RESk 1k ink k DACk 2k 3k V OSk V = V + d V + RESn 1n inn n DACn 2n 3n V OSn 11

12 Matheatical Representation of the Pseudo- Static Pipelined ADC V = V + in1 V = V + d V + RES1 RES in in1 in2 1 2 DAC1 V = V + d V + 20 V OS0 DAC V V OS1 OS2 V = V + d V + RESk 1k ink k DACk 2k 3k V OSk V = V + d V + RESn 1n inn n DACn 2n 3n V OSn V RESk V in(k + 1) = for k = 1 n-1 2n equations 2n-1 interediate nodal voltages and V in 12

13 13 Solution of the 2n linear equations = DACn 1n n n DAC DAC in V... d... V d V d V OSn 1n n OS OS V V V + 1n RESn... V

14 Review Solution of the 2n Linear Equations V in d V + d V d 21 2n REF = 1 DAC1 2 DAC2 n DACn n n 2 V V n + V OS1 VOS2... VOSn n Ter involving digital output codes VRESn V + n n 2 REF Code-independent offset ter Code-dependent but can be bounded by ½ LSB 14 with out-range strategy and variability bounding

15 Review Solution of the 2n Linear Equations = V V V n n 2k REF 3k RESn REF Vin d V k DACk k VOSk k n k= 1 n+1 k= 1 n j= 1 1j j= 1 1j k= 1 1k ij = 2, V DACk =V REF /2, V OSk = 0 V in n VREF d VREF V V = k + + RESn k -1 n + 1 n n + 2 k = REF 1 15

16 Pseudo-Static Tie-Invariant Modeling of a Linear Pipelined ADC V INk AMP V RESk ADC DAC n 1DOUTk V REF If ore than 1 bit/stage is used and DAC is binarilyweighted structure ( ) 2 n k V = V + -1 d V + V RESk 1k ink 2k j=1 kj DACkj 3k OSk 16

17 Pseudo-Static Tie-Invariant Modeling of a Linear Pipelined ADC V INk AMP V RESk ADC DAC n 1DOUTk V REF If DAC is characterized by f ( V, d ) ( ( )) n k V = V + f V, d + V RESk 1k ink 2k k REF kj j=1 3k OSk k n k REF kj j=1 17

18 Solution of the 2n Linear Equations If ore than 1 bit/stage is used and DAC is binarilyweighted structure ( h=n kj = ) V V V n n 2k REF 3k RESn REF Vin d V kj DACkj k VOSk k n k= 1 j=1 n+1 k= 1 n j= 1 1j j= 1 1j k= 1 1k ( ) If DAC is characterized by f V, d n n k n V f V, d V k n k REF kj j=1 ( ( )) V V V = k REF 3k RESn REF in REF kj k OSk k n k= 1 k j=1 n+1 k= 1 n j= 1 1j j= 1 1j k= 1 1k No errors causing spectral distortion or INL degradation if ters involving d kj are correctly deterined and last residue is variability bounded 18

19 Solution of the 2n Linear Equations for 1 bit/stage architecture n Vin = α kd k + f(offset) + α k k = 1 = V DACk k j= 1 f(residue) f(offset) is code-independent, ideally zero, and causes only overall offset error in ADC f(residue) is code-dependent but can be bounded by 1 lsb (causing at ost ½ LSB error) with out-range protection 2k 1j No errors causing spectral distortion or INL degradation if α k are correctly deterined and last residue is variability bounded 19

20 Pseudo-Static Characterization of Pipelined ADC with Arbitrary Bits/Stage and Out-Range Protection n Vin = α kd k + f(offset) + k = 1 f(residue) d k are boolean output variables fro stage ADCs (including out-range protection if included) the α k are functions of DAC levels and aplifier gains f(offset) is code-independent, ideally zero and causes only overall offset error in ADC f(residue) is code-dependent but can be bounded by 1 lsb (causing at ost ½ LSB error) with out-range protection Equation applies to both sub-radix2 and extra coparator out-range protection No errors causing spectral distortion or INL degradation if α k are correctly deterined and last residue is variability bounded 20

21 Pseudo-Static Characterization of Pipelined ADC with Arbitrary Bits/Stage and Out-Range Protection n Vin = α kd k + f(offset) + k = 1 f(residue) No errors causing spectral distortion or INL degradation if α k are correctly deterined and last residue is variability bounded α k ters are rando variables at the design stage but deterinistic at the chip level f(residue) is rando at the design stage but deterinistic at the chip level Key Questions: How can the correct deterination of the α k ters be guaranteed? How can a required bound of f(residue) be achieved? 21

22 n Observations Vin = α kd k + f(offset) + k = 1 f(residue) Substantial errors are introduced if α k are not correctly interpreted or f(residue) is not bounded! If α k are correctly interpreted, and f(residue) is bounded, data conversion process with a pipelined architecture is extreely accurate Bound on f(residue) can be achieved by aking n large enough Major challenge at low frequencies is accurately interpreting the digital output codes (α k s) (Reeber assuption of linearity is still being ade) 22

23 Approaches to Correctly Interpreting Output Codes 1. Design all coponents and blocks to be sufficiently ideal to achieve target perforance with high yield 2. Reduce design requireents on coponents and blocks and use calibration (analog or digital) to achieve target perforance with high yield 3. Try to achieve ideal perforance and use calibration to overcoe deficiencies in design Which approach does industry alost exclusively follow today? 1 Which approach shows the ost proise for low voltage, high speed, high resolution design? 2 Why is approach 3 not the ost attractive approach to follow? Can not derive enough speed and area benefits in eerging processes 23 (Reeber assuption of linearity is still being ade)

24 Why has the calibration or digital calibration approach not been widely adopted by industry? Unaware of the approach? Nuerous authors have discussed concepts in the literature for nearly 2 decades 24

25 Pipelined ADC Digital Calibration Algoriths 1. Y.-M. Lin, B. Ki, and P. R. Gray, A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-u CMOS, IEEE J. Solid-State Circuits, vol. 26, pp , April A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, A 15-b 1-Msaple/s digitally selfcalibrated pipeline ADC, IEEE J. Solid-State Circuits, vol. 28, pp , Deceber T.-H. Shu, B.-S. Song, and K. Barcrania, A 13-b 10-Msaples/s ADC Digitally Calibrated with Oversapling Delta-Siga Cionverter, IEEE J. Solid-State Circuits, vol. 30, pp , April M. K. Mayes and S.W. Chin, A 200-W 1-Msaple/s 16-b Pipelined A/D Converter with On-Chip 32-b Microcontroller, IEEE J. Solid-State Circuits, vol. 31, pp , Dec S.-U. Kwak, B.-S. Song, and K. Bacrania, A 15-b 5-Msaples/s Low-Spurious CMOS ADC, IEEE J. Solid-State Circuits, vol. 32, pp , Deceber I. E. Opris, L. D. Lewicki, and B. C. Wong, A Single-Ended 12-bit 20-Msaples/s Self- Calibrating Pipeline A/D Converter, IEEE J. Solid-State Circuits, vol. 33, pp , Deceber O. E. Erdogan, P. J. Hurst, and S. H. Lewis, A 12-bit Digital-Background-Calibrated Algorithic ADC with -90-dB THD, IEEE J. Solid-State Circuits, vol. 34, pp , Deceber I. E. Opris, B. C. Wong, and S. W. Chin, A Pipeline A/D Converter with Low DNL, IEEE J. Solid-State Circuits, vol. 35, pp , February J. Ming, and S. H. Lewis, An 8-bit 80-Msaples/s Pipelined Analog-to-Digital Converter with Background Calibration, IEEE J. Solid-State Circuits, vol. 36, pp , October A. Shabra, and H. S. Lee, Oversapled Pipeline A/D Converters with Misatch Shaping, IEEE J. Solid-State Circuits, vol. 37, pp , May S.-Y. Chuang, and T. L. Sculley, A Digitally Self-calibrating 14-bit 10-MHz CMOS Pipelined A/D Converter, IEEE J. Solid-State Circuits, vol. 37, pp , June E. Soenen and R. Geiger, "An Architecture and an Algorith for Fully Digital Correction of Monolithic Pipelined ADC's," IEEE Trans. on Circuits and Systes II, pp , March

26 Digital Calibration Algorith Suary of Reported Calibration Results Year Author Resolution Speed (MS/s) INL (LSB) ENOB Calibration 1993 Karanicolas, A.N Digital, off-chip 1996 Mayes, M.K Digital, on-chip 1997 Song, B.S Digital, background 1998 Wooley, B.A Analog, off-chip 1998 Lewis, S.H Digital, on-chip 1999 Erdogan, O.E Digital, on-chip 2000 Blecker, E.B Digital, background 2000 Opris,I.E Self-calibration 2002 Chuang, Y.H Digital, on-chip 2002 Lewis, S.H Digital, background 2002 Shabra, A Self-calibration Why is calibration not substantially enhancing perforance? 26

27 Perforance of reported Calibration- ADCs 27

28 Why has the calibration or digital calibration approach not been widely adopted by industry? Unaware of the approach? Nuerous authors have discussed concepts in the literature for nearly 2 decades Adequate perforance iproveents not obtained in silicon! Most report perforance with calibration at about 11-bit to 12-bit level Mayes reported 15-bit perforance in 1996 but only at 1MHz 28

29 Observations (cont) n V = α d + f(offset) + f(residue) in k= 1 k k If nonlinearities are present, this analysis falls apart and the behavior of the ADC is unpredictable! n V = α d + f(offset) + f(residue)+ ε nonlinear in k= 1 k k ( ) Two ajor types of nonlinearities 1. Saturating nonlinearities (cause inforation loss in residue path) 2. Continuous nonlinearities Most successful designers have ethods for addressing the first type Few know how to address the second type but fortunately these can be relatively sall in any good designs (but not sall enough to practically eet high-end perforance requireents) 29

30 Perforance Liitations (contributors to nonideal α k and nonlinearities) ADC Break Points (offsets) DAC DAC Levels (offsets) Out-range (over or under range) Aplifier Offset voltages Settling Tie Nonlinearity (priarily open loop) Open-loop Out-range Gain Errors Inadequate open loop gain Coponent isatch Power Dissipation kt/c switching noise X INk C LK d k ADCk V REF DACk Ap 30 X OUTk

31 How serious are these liitations? Serious enough to cause ultiple-lsb INL perforance in soe coercial parts Serious enough to cause ultiple passes in silicon before having a arketable product Serious enough to cause apprehension in designers about whether experiental results will agree with siulated results 31

32 How serious are these liitations? Serious enough to cause delays in introducing parts into the arket Serious enough to risk cancellation of projects that are over budget and uncertain of ultiate success Serious enough to give acadeics the opportunity to look at the issues before industry solves all of the probles Serious enough to provide long-ter deand and opportunities to designers that can anage these liitations 32

33 How are these liitations addressed? Use gain-boosting techniques to enhance aplifier gain Iproves closed-loop accuracy Reduces iplications of op ap nonlinearity on linearity of feedback aplifier Existing architectures won t provide adequate gain in low-voltage processes Add out-range (over-range) protection circuitry Extra coparators to detect and correct overranging Sub-radix aplifier gains to bound output range Size capacitors to anage kt/c noise and anage gain accuracy 33

34 How are these liitations addressed? Use calibration circuitry to correct for gain, offset and DAC errors Analog calibration reduces switch transitions during noral operation and keeps digital circuitry at a iniu Digital calibration iniizes parasitics in the analog path Accuracy Bootstrapping Digital Calibration Dynaic Eleent Matching Add power to aplifier in early pipelined stages to iprove settling perforance 34

35 How are these liitations addressed? Use interleaving to reduce settling requireents of inter-stage aplifiers and input saple and hold but Challenge to anage aperture uncertainty associated with sapling by the interleaving Fixed-pattern noise introduced by isatch in parallel paths difficult to reove 35

36 Perforance Liitations (consider aplifier, ADC and DAC issues ) ADC Break Points (offsets) DAC DAC Levels (offsets) Out-range (over or under range) Aplifier Offset voltages Settling Tie Nonlinearity (priarily open loop) Open-loop Out-range Gain Errors Inadequate open loop gain Coponent isatch Power Dissipation kt/c switching noise 36

37 Interstage Aplifiers Typical Finite-Gain Inter-stage Aplifier (shown single-ended with 1-bit/stage) φ 1 φ φ 2 V ink 1 φ 1 C 2 V REF φ 2 d 1 C 1 φ 1 φ 2 d 1 AMP V OUTk Ideally Gain = C C V =V 1+ -d V 1 1 OUT IN 1 REF C C 2 2 V =2V -dv OUT IN 1 REF 37

38 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) R+ R- Input Stage k Input Stage k+1 Input Stage k+2 38

39 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) V R+ V R- Input Stage k Input Stage k+1 Input Stage k+2 R+ R- R- R+ 39

40 Interstage Aplifiers Ideal transfer characteristics (2 bits/stage) V R+ R+ V R- Input Stage k Input Stage k+1 Input Stage k+2 R- R- R+ 40

41 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) R+ R- R- R+ But what really happens? 41

42 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) But what really happens? Ideal Op Ap Transfer Characteristics 42

43 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) But what really happens? Output Range A A = FB 1+Aβ 1 β Finite Op Ap Gain 43

44 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) But what really happens? V OUT V DD Output Range Output Range Liited V DD V IN 44

45 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) But what really happens? V OUT V DD V DD V IN Output Range Liited and Transfer Characteristics are Nonlinear 45

46 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) But what really happens? Offsets occur as well 46

47 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) What are the effects of these errors? Output Effect of Gain Error 47

48 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) What are the effects of these errors? Output Effect of Aplifier Offset 48

49 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) What are the effects of these errors? V R+ Output V R- V R- Input V R+ Effect of ADC Offset 49

50 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) What are the effects of these errors? V R+ Output V R- V R- Input Effect of DAC Errors V R+ 50

51 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) What are the effects of these errors? V R+ Output Output V R- V R- Input Effects of Siultaneous Errors V R+ 51

52 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) What are the effects of these errors? V R+ Output V R- V R- Input V R+ Incorrect Interpretation of Digital Output Codes Over-range of aplifier Inputs (saturating nonlinearities) Over-range of Residue at n-1 stage 52

53 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) V R+ Over-range Protection V R- V R- Input V R+ Extra coparator levels in ADC 53

54 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) Over-range Protection V R+ V R- V R- Input V R+ Output Extra coparator levels in ADC (1 extra coparator) 54

55 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) Over-range Protection V R+ V R- V R- Input V R+ V R+ Output V R- V R- Input V R+ Extra coparator levels in ADC (2 extra coparators) 55

56 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) Over-range Protection V R+ Output V R- V R- Input V R+ Extra coparator levels in ADC (2 extra coparators) 56

57 Issues with out-range protection with extra coparators Robust to large levels of coparator offset voltage Increased dynaic power dissipation and loading of V IN bus Increase in area 57

58 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) Over-range Protection V R+ R+ V R- V R- Input V R+ R- Input Stage k Input Stage k+1 Input Stage k+2 Sub-radix Structure 58

59 Interstage Aplifiers Ideal transfer characteristics (1 bit/stage) Over-range Protection V R+ V R+ V R- V R- Input V R+ R+ V R- Input Stage k Input Stage k+1 Input Stage k+2 Sub-radix Structure R- R- 59 R+

60 Issues with sub-radix protection Robust to large levels of coparator offset voltage Requires ore involved adders when output code is re-assebled Requires additional stages in pipeline (but at LSB end so power and atching requireents are relaxed 60