SUPERIOR-ORDER CURVATURE-CORRECTED PROGRAMMABLE VOLTAGE REFERENCES

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1 SUPEIO-ODE CUATUE-COECTED POGAMMABLE OLTAGE EFEENCES Cosin Popa e-ail: Faculty of Electronics and Telecounications, University Politehnica of Bucharest, B dul Iuliu Maniu 1-3, Bucuresti, oania Key words: Curvature-correction technique, teperature dependence, optiization, weak-inversion ABSTACT Two new voltage references will be presented, having the goals of low-power low-voltage operation and of an extree teperature coefficient, respectively The first circuit was based on the copensation of the nonlinear teperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages The reducing of TC for the second circuit is achieved by the cuulative effect of two ethods: autoprograable teperature stabilization of the chip and superior-order curvature-correction technique A digital prograable loop is designed to select the optial stabilization teperature and the optial type of the curvature-correction SPICE siulations confir the theoretical estiations, TC s of 5 51 pp / K and 4 pp / K, respectively I INTODUCTION The voltage references find applications in a large area of applications, including A/D and D/A converters, eories, data acquisition systes or sart sensors Two iportant goals in developing this class of circuits could be differentiated: one focusing on low-power lowvoltage operation, the circuit being designed for portable equipents or edical devices and other referring to an extree teperature behavior, dedicated to professional systes In order to obtain a low-power operation, the supply voltage is typically uch lower than the noinal supply voltage for the process and the iniu voltage of a battery often dictates it For the high-perforance voltage references, the syste ust operate on the noinal supply voltage, because all the circuits have to reach high perforance As a result of the superior perforance of bipolar references with respect to the circuits using MOS transistors, the first approaches of high-perforance voltage reference were ipleented in bipolar technology However, due to the nonlinear teperature dependence of the base-eitter voltage [1], it exists a theoretical liit for iproving the teperature stability of a siple BG In order to reduce the teperature dependence of the bandgap reference, a lot of curvature-correction techniques [2]-[4] have been developed For CMOS bandgap references, the required bipolar devices are realized as parasitic vertical or lateral transistors, available in CMOS technology The result will be a sall degradation of the circuit teperature behavior because of the poorer atch of MOS devices paraeters with respect to those of bipolar transistors II THEOETICAL ANALYSIS There will be proposed two voltage references based on the sae principle, but focusing on low-power lowvoltage operation and on extree teperature perforance, respectively THE LOW-POWE LOW-OLTAGE OLTAGE EFEENCE The first voltage reference represents an iproveent of the circuit presented in [5], being designed for ipleenting in CMOS technology The original idea is that each single bipolar transistor to be replaced by three MOS transistors working in weak inversion (Figure 1) Q3 Q1 3 Q I(T) 1 Q4 Figure 1: The low-power low-voltage voltage reference 3 Q6 Q5 Iα 2 CC EF

2 The ain advantages of these replaceents are: The full copatibility with CMOS technology; The reducing of the isatch errors; The canceling of the errors caused by the nonzero values of the base currents and by theirs teperature dependencies; The possibility of obtaining a very good controllability of the teperature behavior of the curvature-corrected voltage reference by choosing a proper teperature dependence of a α polarization current, I α = CT The exact value of paraeter α will be further deterined in concordance with the current technology Considering a subthreshold operation of MOS transistors fro Figure 1, the teperature dependence of gate-source voltage could be expressed as: GS GS T FB EG ( T ) = FB + EG + ( ) T + T nkt T + ( α + γ 2) ln (1) q T obility The first ter is a constant ter, the second one is a linear ter, which will be copensated by a copleentary linear dependent on teperature current, I 1 and the last ter odels the nonlinearity of the gatesource voltage teperature dependence This ter will be copensated by a suitable logarithic dependent on teperature current, I 3, also added with GS ( T ) / 2 Iposing the design condition that both the linear and the logarithic curvature-correction to be fulfilled and using the usual values γ = 2 and 2 / 3 = 3, it result α = 2, equivalent with the necessity of polarizing Q 1, Q3, Q5 2 and Q 6 transistors at PTAT currents The reference voltage will be approxiately independent on teperature, EF = 2( FB + EG ) THE EXTEME PEFOMANCE AUTOPOGAMMABLE THEMAL SYSTEM In order to obtain an extreely sall teperature coefficient, an autoprograable theral syste will be presented [6] where T is the reference teperature, E G is the silicon bandgap energy, n and FB are constant paraeters and γ odels the teperature dependence of the carriers CC UA MEM A/D DATA DATA I O I IC1, IC2 E CKM IC1, IC2 E CKM COMM THEM STAB MAIN EF EF EF CK ak EF aux / n I1 Ia fck I1 OSC O DI I EF aux AUX EF I I, I1 I, I1 I, I1 I, I1 I a(k) I 6 Ia(k) I6 I ak Ia(k) SEL Ia(k) / I I Ia I6 Ia(k) / I MULT GND Figure 2: The block diagra of the theral syste

3 Considering that the ain voltage reference fro Figure 2 is ipleented using the bipolar version of the circuit fro Figure 1, the reference voltage will have the following expression: KT T = + + EF ( T ) 2EG ( 2η α 1) 1 ln (2) q T In order to cancel the teperature dependence of EF, it is necessary that α = 2η 1, where η is a technology dependent paraeter, with an usual value of 3, 6 3, 7 Because η has an epirical value, an accurate value of α is difficult to achieve The new proposed idea is to ipleent an autoate loop, which digitally select the optial value of α fro a large list of values, between 6 and 7 The concrete ipleentation of this technique is 6 based on a constant factor, PTAT and a variable factor, 1 PTAT The selection of the optial value for the α paraeter is digitally ade, with a bit resolution I a(k) circuits ipleent α PTAT / k 1 2 currents for realize a PTAT teperature dependence In order to obtain k α = 6 + a k / 2 expression, identical current k = 1 ultipliers were used ( a k are binary coefficients) The selection of the currents active in the coputation of the α exponent (equivalent with the selection of the current curvature-correction technique) will be ade using selection circuits I and I 1 are approxiately independent on teperature and PTAT, respectively The theral stabilization circuit will fixed the ain reference teperature at an optial value T A variation range of the stabilization teperature between ( T ) = 365K and ( T ) 15 = 3K will be iposed in order to iniize the difference between T and the central point of the circuit teperature characteristic Together with the arithetical unit, the coand circuit will start and supervise the study of the voltage reference theral characteristic and the selection of optial stabilization teperature and of optial correction type The stabilization circuit drive is achieved by a digital changing of potential in range, with a 1 step The easureent cycle This cycle will assure the data basis for evaluate the theral behavior of the entire syste, resulting values of the reference voltage, corresponding to 256 distinct curvature-corrections and to 16 values of stabilization teperature Based on this inforation, an arithetical unit UA will deterine the optial correction and the optial reference teperature esetting the syste An output signal, applied to C 1 and C 2 counters and to B bistabil at t oent will start the syste with the first correction ( α = 6 ) and with the first teperature ( T ) = 365K Measureents for ( T ) 365K = Applying f CK on the clock input of C 1 will increent it, passing through all the 256 types of correction C 2 will reain in the " " state (equivalent with ( T ) teperature) and CK M = f CK (the eory is active and store the 256 distinct values of EF ) Heating of the syste fro ( T ) to ( T ) 1 After 256 TCK ( t 1 oent), O 9 O1 = 1, so CK 2 = 1 and C 2 will pass in " 1" state, equivalent with ( T ) 1 = 366K Because of the theral inertia of the syste, the t1 t 2 interval (whose length depends on the chip theral resistance) is introduces to allow the syste to stabilize at ( T ) 1 For this reason, f CK is disconnected fro the eory for 3 256TCK ; CK 2 will fall when O 9 O 1 becoes 1 Measureents for ( T ) 366K 1 = At t 2 oent, the teperature is stabilized al ( T ) 1, so the easureents are valid CK M = f CK, equivalent with an active eory The cycle is repeated for all the 16 values of the teperature, resulting values for EF stored in the eory An A/D converter resolution of 32 bits is enough large in order not to introduce suppleentary errors The optiization cycle The easureent cycle ends at t 4 oent After t 1 (which allows the arithetical unit to copute the optial values of the type correction and of the reference teperature), the PE inputs of the counters will be activated After t 2 (necessary for the chip to stabilize at the optial teperature), the signal will be activated, pointing out the end of the optiization cycle and the validity of the reference voltage with autoprograable superior-order curvature-correction

4 I C1 CK M MEM DATA DATA UA f CK E E I C2 I C1 CK M E I C2 a k I 9 I 1 I 1 I CK 1 C1 O 9 O 1 O 1 O PE I 5 I 1 I 4 O 1 O 4 CK 2 C2 PE O 5 4 b k B CK B O t 1 AD MUX O I 15 I 14 I 13 I 1 I 365 EF aux /n = 3 t 2 a k Figure 3: The coand circuit (T) (T) (T)1 (T)1 (T)1 (T)2 (T)2 (T)2 (T)14 (T)14 (T)14 (T)15 (T)15 (T)15 (T) (T) (T)opt CK 2 CKM O9O f CK O5 t t 1 t 2 t 3 t 4 t 1 t 2 Figure 4: The graphical diagras for easureent and optiization cycles III EXPEIMENTAL ESULTS The SPICE siulation EF (t) for the low-power lowvoltage curvature-corrected voltage reference fro Figure 1 ( 35µ CMOS technology) is presented in Figure 5 The siulated teperature coefficient is o TC = 5 51pp / K for < t < 9 C and CC = 25 The siulated results EF (t) for the autoprograable theral syste, using 5 values of α paraeter (, 1, 2, 6, 7 ), are presented in Figure 6, showing a decreasing of the teperature coefficient when α atches better the theoretical estiated values (Table 1) Table 1 α TC( pp / K) Figure 5: SPICE siulation EF (t) for the low-power low-voltage circuit

5 5 51pp / K for an extended teperature range, o < t < 9 C and a sall supply voltage, CC = 2 5 The theral syste with ultiple superior-order curvature-correction fro the second part includes an autoprograable digital loop, which selects the optial values of the curvature-correction type and of the stabilization teperature The inial value of the siulated teperature coefficient was about 4 pp / K (an idealized value because no isatches errors have been considerred), the circuit requiring a technology with sall paraeters spread Figure 6: Siulation results for EF (t) CONCLUSIONS Two superior-order curvature-corrected voltage references have been presented, focusing on low-power low-voltage operation and on high perforance The new proposed low-power low-voltage circuit was based on the copensation of the nonlinear teperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors polarized at drain currents with different teperature dependencies The low-power operation was achieved by polarizing MOS transistors in weak inversion The circuit was ipleented in 35µ CMOS technology The SPICE siulation based on the previous entioned technology confirs the theoretical estiated results, reporting a teperature coefficient of EFEENCES 1 I M Filanovsky, Y F Chan, BiCMOS Cascaded Bandgap oltage eference, IEEE 39th Midwest Syposiu on Circuits and Systes, pp , O Salinen, K Halonen, The Higher Order Teperature Copensation of Bandgap oltage eferences, IEEE International Syposiu on Circuits and Systes, ISCAS 1992, vol 3, pp , M Gunawan, et al, A Curvature-Corrected Low- oltage Bandgap eference, IEEE Journal of Solid- State Circuits, vol 2 6, pp , I Lee, G Ki, W Ki, Exponential Curvature- Copensated BiCMOS Bandgap eferences, IEEE Journal of Solid-State Circuits, pp , P Malcovati, F Maloberti, M Pruzzi, C Fiocchi, Curvature Copensated BiCMOS Bandgap with 1 Supply oltage, ESSCIC, pp , 21 6 C Popa, Autoprograable Superior-order Curvaturecorrection CMOS Theral Syste, The 25 th International Seiconductor Conference, oânia, pp , 22