Schematic. ADSP-SC584 EZ-Board A B C D. 4 Title Title Block Size C. Board No. Rev 1.1A. Date A B C D

Transcription

1 D DSP-S EZ-oard Schematic Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard lock -. // D

2 Elizabeth Drive helmsford, M PH: --NLOGD D D DDR Interface // DSP-S EZ-oard -. DM_RESET_Z DM_RZQ DM Z DM Z DM Z DM Z DM Z DM_ODT_Z DM_RS_Z DM_WE_Z DM_KE_Z DM_S_Z DM_S_Z DM_K DM_K DM_LDM DM_UDM DM_UDQS DM_UDQS DM_LDQS DM_LDQS DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_ODT DM_RS DM_WE DM_KE DM_S DM_S DM_K DM_LDM DM_UDM DM_UDQS DM_UDQS DM_LDQS DM_LDQS DM_.V R.K.UF.K R.UF.V R. DM_K.UF UF.V.UF.UF.UF.UF.UF.UF.UF.V.UF.UF.UF.UF.UF.UF.UF Gb DDR RN R R R R R R R R DM Z DM Z DM Z DM Z R R R R R R R R RN R R R R R R R R RN R R R R R R R R RN R R R R R R R R RN DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z DM Z R R R R R R R R RN R R R R R R R R RN DM Z DM Z DM Z DM_S_Z DM_RS_Z DM_S_Z DM_ODT_Z DM_WE_Z DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ODT DM_RS DM_WE DM_S DM_S DM_KE_Z DM_KE R DM_RZQ DM_RESET R K DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_DQ DM_LDQS DM_LDQS DM_UDQS DM_UDQS DM_UDM DM_LDM DM_K DM_K DM_S DM_S DM_KE DM_WE DM_RS DM_ODT DM_ DM_ DM_ DM_VREF DM_ DM_ DM_RZQ DM_RESET E E D F E D D E U F SOKET SOKET DM_RESET_Z R DM_RESET U K K E L K L J G G G E G J R M J E R R R K E F F H F F E D D H J P N J E F F H H H H D D D D G G K J L L L P P P N N N N M R P M M M /P K KE DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ L Q Q Q Q Q Q Q Q Q Q LDM LDQS N N ODT RFU/ RFU/ RFU/ UDM UDQS VDD VDD VDD VDD VDD VDDL VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF S K S LDQS RS UDQS WE MTHM FG.V XU XU SPG DSPS.UF Place close to U DM_VREF R.K R.K PF DM_VREF Place R and close to U

3 Elizabeth Drive helmsford, M PH: --NLOGD D D. - DSP-S EZ-oard // Non-Mux Ports.V.V.V TP TP SYS_RESOUT SYS_FULT.V ML_SIGP ML_SIGN ML_LKN ML_LKP ML_DTN ML_DTP ML signals need to be short and matched trace length..v IN OUT NFEPT.V ML_SIGP ML_SIGN US_LKIN US_XTL US_V US_VUS US_ID ML_LKN ML_LKP US_DM US_DP ML_DTN ML_DTP TWI_SL TWI_SD TWI_SD TWI_SL TWI_SD JTG_TRST JTG_TDI TWI_SL SYS_MODE SYS_MODE SYS_MODE SYS_LKIN SYS_XTL SYS_LKOUT SYS_LKIN SYS_XTL JTG_TMS/SWDIO JTG_TK/SWLK JTG_TDO/SWO FER HD_VREFP HD_VREFP TP TP TP R R. R.K R R.K.K R R.K R.K.K R.K R R.K. R K R K R LED RED R.. R.UF UF DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN HDO_VIN HDO_VIN HDO_VIN HDO_VIN HDO_VIN HDO_VIN HDO_VIN HDO_VIN HDO_VREFP ML_DTP ML_DTN US_DP US_DM ML_LKP ML_LKN US_ID US_VUS US_VUS_FLG US_XTL US_LKIN ML_SIGN ML_SIGP HDO_VREFN HD_VIN HD_VIN HD_VIN HD_VIN HD_VIN HD_VIN HD_VIN HD_VIN SYS_XTL SYS_LKIN SYS_LKOUT SYS_XTL SYS_LKIN SYS_MODE SYS_MODE SYS_MODE TWI_SL SYS_HWRST SYS_RESOUT JTG_TDI JTG_TDO SYS_FULT JTG_TRST JTG_TK JTG_TMS TWI_SD TWI_SL TWI_SD TWI_SD TWI_SL SYS_FULT SYS_FULT SYS_RESOUT R K SYS_HWRST DI_PIN DSPS SPG U T T R R R P N P T U N P U U W V Y Y Y Y T Y DSPS SPG U Y Y DSPS SPG U H Y Y M M M K P J U L N P T U T P N FULT

4 Elizabeth Drive helmsford, M PH: --NLOGD D D Mux Ports // DSP-S EZ-oard -. PE_/SPI_MOSI/PPI_D/SM_Eb PE_/SPI_MISO/PPI_D/SM_Eb PE_/PPI_D/PWM_L/SM_D PE_/PPI_FS/SPI_SELb/URT_TSb/SHR_FLG PE_/PPI_FS/SPI_SELb/URT_RTSb/SHR_FLG PE_/PPI_LK/SPI_SELb/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_DH/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_SYN/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SPI_RDY/SHR_FLG PE_/PPI_D/PWM_DL/URT_RTSb/SM_D PE_/PPI_D/SPI_SELb/URT_TSb/SM_D/SPI_SSb PE_/PPI_D/SPI_SELb/SPI_RDY/SM_D PE_/SPI_LK/PPI_D/SM_MSb P_/SPI_SELb/SPI_RDY/M_T/SM_ P_/URT_TXb/SPI_SELb/M_ P_/N_TX/SM_MSb P_/N_RX/SPI_SELb/SM_MSb/TM_I P_/SPI_SELb/SPI_SSb P_/SPI_D P_/SPI_D P_/SPI_MOSI P_/SPI_MISO P_/SPI_MOSI/TM_LK P_/SPI_MISO P_/LP_LK/PWM_L/SPI_SELb/SM_REb P_/URT_RTSb/PPI_FS/M_/SM_MSb P_/URT_RXb/M_/TM_I PD_/PPI_D/PWM_TRIPb/ML_LKOUT/SM_D PD_/PPI_D/PWM_H/SM_D PD_/URT_TSb/PPI_D/M_/SM_D PD_/SPI_SELb/M_/SM_b/SPI_SSb PD_/LP_LK/PWM_DL/TRE_LK PD_/LP_K/PWM_SYN PD_/LP_D/PWM_TRIPb/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_DH/TRE_D/TM_LK PD_/LP_D/PWM_L/TRE_D/TM_LK PD_/URT_RXb/PPI_D/SM_/TM_I PD_/URT_TXb/PPI_D/SM_ P_/LP_D/TM_TMR/PWM_L/SM_D/NT_DG P_/LP_K/PWM_TRIPb/TM_TMR/SM_WEb P_/ETH_PTPPPS/SIN_D/PPI_D/SM_/TM_LK P_/ETH_PTPPPS/SIN_LK/PPI_D/SM_/TM_LK P_/LP_D/TM_TMR/N_RX/SM_D/TM_I P_/LP_D/PWM_DH/SM_D/NT_ZM P_/ETH_PTPLKIN/URT_TXb/PPI_D/SM_ P_/ETH_PTPUXIN/URT_RXb/PPI_D/SM_/TM_I P_/ML_LK/SIN_D/PPI_D/SM_RDY/ETH_PTPUXIN P_/ML_SIG/PPI_D/SM_/ETH_PTPUXIN P_/ML_DT/PWM_H/SM_/ETH_PTPUXIN P_/LP_D/PWM_H/TM_TMR/SM_D P_/LP_D/N_TX/SM_D P_/LP_D/PWM_L/TM_TMR/SM_D P_/LP_D/PWM_H/SM_D P_/LP_D/PWM_DL/SM_D/NT_UD P_/ETH_PTPPPS/SIN_D/SM_ P_/ETH_PTPPPS/SIN_D/SM_ P_/ETH_MD/SM_ P_/ETH_MDIO/SM_ P_/ETH_TXD/SM_ P_/ETH_TXD/SM_ P_/ETH_TXLK/SM_ P_/ETH_TXTL_TXEN/SM_ P_/ETH_RXD/SM_ P_/ETH_RXD/SM_ P_/ETH_RXTL_RS/SM_ P_/ETH_RXLK_REFLK/SM_ P_/ETH_RXD/SM_ P_/ETH_RXD/SM_ P_/ETH_MDIO/SM_ P_/ETH_MD/SM_ P_/ETH_TXD/SM_ P_/ETH_TXD/SM_ P_/ETH_PTPPPS/SIN_D/SM_ P_/ETH_PTPPPS/SIN_D/SM_ P_/LP_D/PWM_DL/SM_D/NT_UD P_/LP_D/PWM_H/SM_D P_/LP_D/PWM_L/TM_TMR/SM_D P_/LP_D/N_TX/SM_D P_/LP_D/PWM_H/TM_TMR/SM_D P_/ML_DT/PWM_H/SM_/ETH_PTPUXIN P_/ML_SIG/PPI_D/SM_/ETH_PTPUXIN P_/ML_LK/SIN_D/PPI_D/SM_RDY/ETH_PTPUXIN P_/ETH_PTPUXIN/URT_RXb/PPI_D/SM_/TM_I P_/ETH_PTPLKIN/URT_TXb/PPI_D/SM_ P_/LP_D/PWM_DH/SM_D/NT_ZM P_/LP_D/TM_TMR/N_RX/SM_D/TM_I P_/ETH_PTPPPS/SIN_LK/PPI_D/SM_/TM_LK P_/ETH_PTPPPS/SIN_D/PPI_D/SM_/TM_LK P_/LP_K/PWM_TRIPb/TM_TMR/SM_WEb P_/LP_D/TM_TMR/PWM_L/SM_D/NT_DG PD_/URT_TXb/PPI_D/SM_ PD_/URT_RXb/PPI_D/SM_/TM_I PD_/LP_D/PWM_L/TRE_D/TM_LK PD_/LP_D/PWM_DH/TRE_D/TM_LK PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_TRIPb/TRE_D PD_/LP_K/PWM_SYN PD_/LP_LK/PWM_DL/TRE_LK PD_/SPI_SELb/M_/SM_b/SPI_SSb PD_/URT_TSb/PPI_D/M_/SM_D PD_/PPI_D/PWM_H/SM_D PD_/PPI_D/PWM_TRIPb/ML_LKOUT/SM_D P_/URT_RXb/M_/TM_I P_/URT_RTSb/PPI_FS/M_/SM_MSb P_/LP_LK/PWM_L/SPI_SELb/SM_REb P_/SPI_LK P_/SPI_MISO P_/SPI_MOSI/TM_LK P_/SPI_MISO P_/SPI_MOSI P_/SPI_D P_/SPI_D P_/SPI_SELb/SPI_SSb P_/N_RX/SPI_SELb/SM_MSb/TM_I P_/SPI_LK P_/N_TX/SM_MSb P_/URT_TXb/SPI_SELb/M_ P_/SPI_SELb/SPI_RDY/M_T/SM_ PE_/PPI_D/PWM_SYN/TM_TMR/SM_D PE_/SPI_LK/PPI_D/SM_MSb PE_/PPI_D/SPI_SELb/SPI_RDY/SM_D PE_/PPI_D/SPI_SELb/URT_TSb/SM_D/SPI_SSb PE_/PPI_D/PWM_DL/URT_RTSb/SM_D PE_/PPI_D/PWM_SYN/TM_TMR/SM_D PE_/PPI_D/SPI_SELb/SPI_RDY/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_SYN/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_DH/SPI_SELb/SHR_FLG PE_/PPI_LK/SPI_SELb/SPI_SELb/SHR_FLG PE_/PPI_FS/SPI_SELb/URT_RTSb/SHR_FLG PE_/PPI_FS/SPI_SELb/URT_TSb/SHR_FLG PE_/PPI_D/PWM_L/SM_D PE_/SPI_MISO/PPI_D/SM_Eb PE_/SPI_MOSI/PPI_D/SM_Eb.V P_/LP_D/PWM_H/TM_TMR/SM_D P_/LP_D/PWM_L/TM_TMR/SM_D K R TP for PWM_H/L to connect to N Place close to DSP R K R K K R R K PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D R P_/SPI_LK P_/SPI_LK R DSPS SPG U G H L H J J G K K F G L N E F D D E D R R Y Y W W Y Y U Y Y V V Y V V V W W W Y Y Y M N F G G H H J J K K L L L M M DSPS SPG U R K K R R K R R R R R R R R R R P_/ETH_TXD/SM Z P_/ETH_TXD/SM Z R R P_/ETH_TXLK/SM Z P_/ETH_TXD/SM Z R P_/ETH_TXD/SM Z R P_/ETH_TXTL_TXEN/SM Z R R R R P_/ETH_RXD/SM DP P_/ETH_RXD/SM DP P_/ETH_RXLK_REFLK/SM DP P_/ETH_RXTL_RS/SM DP P_/ETH_RXD/SM DP P_/ETH_RXD/SM DP P_/ETH_RXD/SM M P_/ETH_RXD/SM M P_/ETH_RXLK_REFLK/SM M P_/ETH_RXTL_RS/SM M P_/ETH_RXD/SM M P_/ETH_RXD/SM M

5 Elizabeth Drive helmsford, M PH: --NLOGD D D. - DSP-S EZ-oard // Processor Power/Ground.V VDD_INT VDD_EXT VDD_INT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_HD VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_DM VDD_US VDD_EXT VDD_DM VDD_DM VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT.V IN OUT NFEPT FER.UF UF R R VDD_EXT DSPS SPG U U U W W M U U U J H K U H G G G H G G G G G G G G G F F L L M M J K K L F F G H F F F F F F F F F E D Y U U R R T T U U U U N N P P M L D J T T T T T R R P P P P P P N N N N N N N N M M M M M M M M L L L L L L L L K K K K K K K K J J J J J J H DSPS SPG U R Y Y T T T T T

6 Elizabeth Drive helmsford, M PH: --NLOGD D D DSP-S EZ-oard - Proc ypass aps //. VDD_EXT VDD_INT UF UF UF UF UF UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.V

7 D.V SW ROTRY R K R K R K SYS_MODE SYS_MODE SYS_MODE SW: oot mode selection switch MODE[:] oot Source No boot/ustom ROM SPI master boot SPI slave boot Reserved Reserved Reserved DEFULT US_XTL R should be depopulated when using the optional circuit OPTIL US RYSTL R Y MHZ R US_LKIN LP slave boot URT slave boot PF PF LKIN J SM R SYS_LKIN R should be depopulated when using the optional circuit OPTIL DSP RYSTLS R should be depopulated when using the optional circuit.v SYS_XTL R R R R Y Y MHZ MHZ SYS_LKIN SYS_XTL SYS_LKIN PF PF PF PF.V R.K R.K TWI_SD TWI_SL Y MHZ U X X LKIN INTR SD SL I_LS SS_DIS SI QFN VDD VDD VDDO VDDO VDDO VDDOD LK LK LK LK LK LK LK LK R.V.UF R R R SYS_LKIN SYS_LKIN DU_LKIN MHz MHz.MHz.V.V R K U VDD STNDY OUT MHZ US OS R US_LKIN.V.UF TWI ddress x x is the R/W bit. Read -, Write -.V.V R K.V U VDD STNDY MHZ OUT DP OS R DP_LKIN.V.UF R K.V U VDD STNDY OUT MHZ M OS R M_LKIN.V.UF Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard locks/oot Mode -. // D

8 D Mb QUD SPI FLSH.V R R K K R R K K P_/SPI_MOSI P_/SPI_LK SPIFLSH_S SPIFLSH_SPID SPIFLSH_SPID R K U DI/IO LK S WP/IO HOLD/IO WQFV SOI V DO/IO R.V P_/SPI_MISO XU.UF SOKET.V.UF.UF.UF Kb SPI EEPROM.V.V.V EEPROM_EN PD_/SPI_SELb/M_/SM_b/SPI_SSb R R K K U TLVG S_.V P_/SPI_MOSI/TM_LK P_/SPI_LK.V U V SI SK S L SOT- SO P_/SPI_MISO SPIFLSH_S_EN P_/SPI_SELb/SPI_SSb SPID_D_EN P_/SPI_D P_/SPI_D R K R K U TLVG S_ U TLVG S_ U TLVG S_ SPIFLSH_S SPIFLSH_SPID SPIFLSH_SPID.UF.UF TWI_SL TWI_SD P_/SPI_MISO P_/SPI_LK P_/SPI_SELb/SPI_SSb P ID PE_/PPI_D/SPI_SELb/SPI_RDY/SM_D P_/SPI_MOSI Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard SPI Flash - D P_/SPI_D P_/SPI_D //.

9 D.V US to URT.V ML / P VUS D- D+ ID SHELL.UF D IN IN IN URT_FLOW_EN P_/URT_RTSb/PPI_FS/M_/SM_MSb PD_/URT_TSb/PPI_D/M_/SM_D P_/URT_TXb/SPI_SELb/M_ P_/URT_RXb/M_/TM_I US-MIRO IN ESDVS R M URT_EN FER.UF FER R K.UF R K U PI TSSOP D IN IN IN IN N N ESD.UF N N R.UF.UF U VIO V R K USM USP RESET OSI OSO VOUT D D D TEST EPD FTRQ QFN R K TXD RXD RTS TS DTR DSR DD RI US US US US US.V.V LED YELLOW R..UF LED YELLOW R. ML_SIGN ML_SIGP ML_DTN ML_DTP ML_LKN ML_LKP P_/LP_D/N_TX/SM_D P_/LP_K/PWM_TRIPb/TM_TMR/SM_WEb P_/LP_LK/PWM_L/SPI_SELb/SM_REb TWI_SL TWI_SD.V draws m at.v J QSH OS TWI ddress x x is the R/W bit. Read -, Write - P_/ML_LK/SIN_D/PPI_D/SM_RDY/ETH_PTPUXIN P_/ML_SIG/PPI_D/SM_/ETH_PTPUXIN P_/ML_DT/PWM_H/SM_/ETH_PTPUXIN ML_EN ML_EN Low for oard Option (ML) ML_EN Float for oard Option (ML) P_/LP_D/TM_TMR/N_RX/SM_D/TM_I P_/LP_D/PWM_H/SM_D.V.V R K R K R K R R K K R K ENGINE_RPM_ THUMWHEEL_ P_/LP_D/PWM_DL/SM_D/NT_UD P_/LP_D/TM_TMR/PWM_L/SM_D/NT_DG P_/LP_D/PWM_DH/SM_D/NT_ZM U PI TSSOP.V SW OMM SW SW SW SW SH SHIELD SH SHIELD ROTRY_ENODER Volume ontrol "RPM" Engine RPM Single Ended.V P ID U SNLVG PE_/PPI_D/PWM_SYN/TM_TMR/SM_D.UF.UF Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard URT/MOST/Thumbwheel -. // D

10 Elizabeth Drive helmsford, M PH: --NLOGD D D US/D // DSP-S EZ-oard -. IN IN IN IN N N N N IN IN IN IN VUS D+ D- SHELL ID VRISTOR R.UF R.UF M R PT R ESD D FER ESDVS D US_DP US_DM US_ID US_VUS HOST/DEVIE US-MIRO P JUMPER SHORTING FLG IN OUT OUT EN.V SJ? DEFULT=INSTLLED TP U MI- SOI UF UF R R. P K R R K US_VUS US_V "US_VUS" Remove jumper when measuring US_VUS D UF T.V JUMPER JUMPER JUMPER V HD_VIN HD_VIN HD_VIN HD_VIN HD_VIN HD_VIN U D R.K R R R PF PF VDD_INT DEFULT=& SJ? SJ? DEFULT=& DEFULT=& SJ? HD onnectors HD_VIN SM J J SM SM J SM J.UF.V FER "VIN///" JUMPER DEFULT=& SJ? HD_VIN P ID V R K R K D MMZVTG IN P- P+ OUT SHDN V SOT- DMRTZ U UF UF -V V VIN VIN VIN VIN US OTG

11 Elizabeth Drive helmsford, M PH: --NLOGD D D. - DSP-S EZ-oard // N Engine HU ontrol V.V.V V.V.V V.V.V V TXD RXD SK SDI WKE SDO INH NH NL VIO VDD VT SSN TXD RXD EN ST WKE ERR INH NH NL VDD T RTH RTL Y Y Y Y Y Y Y Y V RJ J.UF.UF.UF.K R R K.UF PF R.K.K R UF R R PF PF FER RJ J FER PF PF N N N_EN P_/LP_D/N_TX/SM_D P_/N_TX/SM_MSb P_/LP_D/TM_TMR/N_RX/SM_D/TM_I P_/SPI_LK P_/SPI_MOSI/TM_LK P_/SPI_MISO P_/SPI_SELb/SPI_RDY/M_T/SM_ N_EN P_/LP_D/PWM_H/TM_TMR/SM_D P_/LP_D/PWM_L/TM_TMR/SM_D P_/N_RX/SPI_SELb/SM_MSb/TM_I P_/ETH_PTPLKIN/URT_TXb/PPI_D/SM_. R R. U SOI TJT R K K R R.K K R K R R K SOI TJ/ U TSSOP TLV U PESDN D D PESDN INH_TJ INH_TJ R..K R SW DIP JP ID N_INH INH_TJ INH_TJ "N Wake" V V V V R.K R K Q SSPE SSPE Q K R JUMPER SHORTING SJ? DEFULT=Pin K R UF K R UF V V V N INH HU TROL ENGINE

12 D LINK PORT / JTG OUT J LINK PORT / JTG IN J JTG_TK/SWLK_LINKPORT JTG_TDO/SWO_OUT JTG_TMS/SWDIO_LINKPORT JTG_TRST_LINKPORT MS MS MS MS MS MS D D D D D D D D K LK PD_/LP_D/PWM_DH/TRE_D/TM_LK PD_/LP_D/PWM_L/TRE_D/TM_LK PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_TRIPb/TRE_D PD_/LP_K/PWM_SYN PD_/LP_LK/PWM_DL/TRE_LK JTG_TK/SWLK_LINKPORT JTG_TDO/SWO_IN JTG_TMS/SWDIO_LINKPORT JTG_TRST_LINKPORT MS MS MS MS MS MS D D D D D D D D K LK P_/LP_D/TM_TMR/PWM_L/SM_D/NT_DG P_/LP_D/PWM_H/SM_D P_/LP_D/PWM_DL/SM_D/NT_UD P_/LP_D/PWM_DH/SM_D/NT_ZM P_/LP_D/TM_TMR/N_RX/SM_D/TM_I P_/LP_D/N_TX/SM_D P_/LP_D/PWM_L/TM_TMR/SM_D P_/LP_D/PWM_H/TM_TMR/SM_D P_/LP_K/PWM_TRIPb/TM_TMR/SM_WEb P_/LP_LK/PWM_L/SPI_SELb/SM_REb ERF ERF R K R K R K R K.V P JTG_TRST_LOL JTG_TRST_LINKPORT JTG_TMS/SWDIO_LOL JTG_TMS/SWDIO_LINKPORT JTG_TK/SWLK_LOL JTG_TK/SWLK_LINKPORT JTG_TDI JTG SWITHES SW DIP SW JTG_TRST JTG_TMS/SWDIO JTG_TK/SWLK JTG_TDI_LOL TRGET_RESET JTG_TDO/SWO_LOL JTG_TK/SWLK_LOL JTG_TMS/SWDIO_LOL JTG_TDI_LOL JTG_TRST_LOL R K R K TRE PD_/LP_LK/PWM_DL/TRE_LK R R K PD_/LP_D/PWM_DH/TRE_D/TM_LK PD_/LP_D/PWM_L/TRE_D/TM_LK PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_TRIPb/TRE_D JTG_TDO/SWO JTG_TDI JTG_TDO/SWO_LOL DIP JTG_TDO/SWO_LOL JTG_TDO/SWO_OUT JTG_TDO/SWO_IN JTG_TDO/SWO_IN.V.V R K R K R K R K R K SINGLE PRSSOR JTG SETTINGS EMULTOR OR DEUG GENT (DEFULT) SWITH SW?. SW?. SW?. SW?. SW?. SW?. ORD TTHED TO EMULTOR MULTI PRSSOR JTG SETTINGS USING TWO OR MORE EZ-ORDS (LINK PORT LES REQUIRED FOR MORE THN TWO ORDS) SWITH SW?. SW?. SW?. SW?. SW?. SW?. ORD TTHED TO EMULTOR ORD(S) NOT TTHED TO EMULTOR JTG_TRST_LOL R K R K P DEUG JTG_TMS/SWDIO_LOL JTG_TK/SWLK_LOL JTG_TDO/SWO_LOL JTG_TDI_LOL TRGET_RESET SW?. SW?. SW?. SW?. SW?. SW?. SW?. SW?. SW?. SW?. SW?. SW?. Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard Link Port/Debug -. // D

13 D.V.V.K RXXX R.K R.K R.K R. R. R. R. R. R. R. R. "//" Ohm traces U U J P_/ETH_MDIO/SM_ P_/ETH_MD/SM_ P_/URT_RTSb/PPI_FS/M_/SM_MSb P_/ETH_RXD/SM DP P_/ETH_RXD/SM DP P_/ETH_RXD/SM DP P_/ETH_RXD/SM DP P_/ETH_RXLK_REFLK/SM DP P_/ETH_RXTL_RS/SM DP P_/ETH_TXTL_TXEN/SM Z P_/ETH_TXD/SM Z P_/ETH_TXD/SM Z P_/ETH_TXD/SM Z P_/ETH_TXD/SM Z P_/ETH_TXLK/SM Z R R R Place close to U R R R R R R MDIO MDI_P MD MDI_N INTERRUPT MDI_P RXD MDI_N RXD MDI_P RXD MDI_N RXD MDID_P RXD/RX MDID_N RXD/RX RXD/RX TIVITY_LED/SPEED_STRP RXD/RX LINK_LED/RLED/SPEED_STRP RX_LK LINK_LED/DUPLEX_STRP RX_DV/RK LINK_LED/N_EN_STRP RX_ER/RXDV_ER OL/LK_M_FREQ RS/RGMII_SEL TX_LK/RGMII_SEL TX_ER TX_EN/TXEN_ER TXD TXD TXD TXD TXD/TX TXD/TX TXD/TX TXD/TX DUPLEX_LED/PHYDDR_STRP PHYDDR_STRP PHYDDR_STRP PHYDDR_STRP PHYDDR_STRP MULTI_EN_STRP/TX_TRIGGER MDIX_EN_STRP M_LK_EN_STRP TX_TLK/MN_MDIX_STRP N_IEEE_STRP VDD_SEL_STRP GTX_LK_TK RESET.UF DP_LED DP_LED DP_LED DP_LED.V.UF R.K.UF.UF.UF PHY ddress x P_/LP_D/TM_TMR/PWM_L/SM_D/NT_DG.UF.UF TD+ TD- MX- TD- MX- TD+ TD- MX- TD+ TD- MX- TD+ TT TT TT TT H.UF MX+ MX+ MX+ MX+ MT MT MT MT SH R. PF R. R D+ D- RJ R. DP_LKIN LK_TO_M LK_IN LK_OUT RESERVED RESERVED RESERVED G_REF TK TDO TMS TRST TDI RGMII - OM Mode R.K DP PQFP R.K R.K R.K R.K.V U Use lkoutdis to disable LK_OUT when used for SPDIF.V P_/ETH_PTPPPS/SIN_LK/PPI_D/SM_/TM_LK TWI_SL TWI_SD LK_IN D/S SL/LK SD/DIN V LK_OUT UX_OUT R DI_PIN DP_LED DP_LED R R.K. LED GREEN R.K R. LED GREEN R.K R R R..K. LED GREEN LED GREEN DP_LED DP_LED.V.UF PF Y MHZ PF R.K XTI/REF_LK XTO S-P MSOP TWI ddress x x is the R/W bit. Read -, Write - Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard DP -. // D

14 Elizabeth Drive helmsford, M PH: --NLOGD D D // DP Power. - DSP-S EZ-oard IO_VDD ORE_VDD IO_VDD ORE_VDD IO_VDD ORE_VDD IO_VDD ORE_VDD IO_VDD IO_VDD ORE_VDD IO_VDD IO_VDD ORE_VDD IO_VDD ORE_VDD IO_VDD IO_VDD IO_VDD ORE_VDD V_VDD V_VDD V_VDD V_VDD V_VDD_ V_VDD_ V_VDD_ V_VDD_ V_VDD_.V.V.V.V.V.V.V DP PQFP U R UF.UF.UF.UF UF UF UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF R. UF UF UF.V VR INPUT OUTPUT EN SEN NPDSN SOT-

15 D.V FER P_/ETH_TXLK/SM Z P_/ETH_TXTL_TXEN/SM Z P_/ETH_TXD/SM Z P_/ETH_TXD/SM Z P_/ETH_TXD/SM Z P_/ETH_TXD/SM Z UF UF Place close to U R R R R R R Place close to U FER R.V R.K U GTXLK/TX TX_EN TXD TXD TXD TXD UF UF OVDD OVDD OVDD UF TRD+ TRD- LED LED LED LED R. PF M_LED M_LED M_LED L NH L NH R. PF R. R. R. PF R. L NH L NH R R. PF. R. PF FER R. PF R. R..V FER R K R K.UF.UF "/" J D+ D- RJ P_/ETH_RXLK_REFLK/SM M P_/ETH_RXTL_RS/SM M.V P_/ETH_RXD/SM M P_/ETH_RXD/SM M P_/ETH_RXD/SM M P_/ETH_RXD/SM M P_/ETH_MDIO/SM_ P_/ETH_MD/SM_ R R R R R R R R P_/LP_D/TM_TMR/PWM_L/SM_D/NT_DG Place close to U PHY ddress x RGMII M_LKIN R R K RX RX_DV RXD RXD RXD RXD MDIO MD XTLI XTL PHY RESET M MLP TEST TEST TVOI DVDD DVDD VDDL VDDL VDDL PLLVDD VDD VDD ISVDD XTLVDD RD R.K UF UF UF FER FER FER.V UF UF UF UF UF UF UF UF UF UF FER UF FER UF UF.UF.UF.V Set bit register x to to put into isolate mode. TIVITY LED GREEN Set bit register x (Shadow ) to to put into super isolate mode. M_LED R R M_LED R P_/URT_RTSb/PPI_FS/M_/SM_MSb Link M_LED PF PF R LED GREEN LED YELLOW M_LED M_LED M_LED R.K R.K R.K M_LED.V PF Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard M -. // D

16 Elizabeth Drive helmsford, M PH: --NLOGD D D DU // DSP-S EZ-oard -. V.V.V V.V.V V.V V.V Y Y Y Y Y Y Y Y V.V DLK DLRLK S S DSDT DSDT DSDT DSDT DSDT DSDT D- D- MLKO XTLO MLKI/XTLI PLLVDD LF PLL PU/RST S_MODE SS/DDR/S SLK/SL MISO/SD/S MOSI/DDR/S DP DN DP DN DP DN DP DN D_IS D_IS DP DN DP DN DP DN DP DN DP DN DP DN DP DN DP DN D_IS D_IS TS_REF M D- VDRIVE VSENSE VSUPPLY IOVDD- DVDD- IOVDD- DVDD- VDD VDD VDD VDD DVDD- D-.V.V.UF.UF.UF.UF UF.UF UF.UF UF UF UF UF.UF FER. R PF PF.UF VR FZT UF.UF UF.UF R.K TWI_SL TWI_SD TWI ddress x x is the R/W bit. Read -, Write - heck for extender conflict DP DP DP DP DP DP DP DP DP DP DP DP DU_LKIN P_/ETH_PTPPPS/SIN_D/SM_ DI_PIN TLVG U S_ DI_PIN DI_PIN DU_EN DU_EN U TLVG S_ P_/ETH_PTPPPS/SIN_D/SM_ DU_SDTOUT DU_SDTOUT DU_LK DU_RESET DI_PIN TSSOP U TLV TLVG U S_ DU_LKIN DI_PIN K R R R R R R R K K R R K K R R K K R LQFP DUWSTZ U P_/ETH_PTPUXIN/URT_RXb/PPI_D/SM_/TM_I U TLVG S_ DU_LRLK DU_MLKO.UF.UF.UF.UF.UF.UF.UF.UF.UF.UF DI_PIN DI_PIN DI_PIN DI_PIN

17 D V TWI_SL TWI_SD PE_/SPI_MISO/PPI_D/SM_Eb PE_/SPI_LK/PPI_D/SM_MSb PE_/PPI_D/SPI_SELb/URT_TSb/SM_D/SPI_SSb SIGM STUDIO P PE_/SPI_MOSI/PPI_D/SM_Eb.UF.UF.UF.UF.UF UF.UF R UF.K V.V PF DU_LKIN DU_MLKO DU_RESET DU_LRLK DU_LK DU_SDTOUT DU_SDTOUT TWI_SL TWI_SD R R R K U MLKIN PD/RST S_MODE LRLK LK SDTOUT SDTOUT SL/LK SD/OUT DDR/LTH DDR/IN DUWPZ LFSP VDD VDD VDD DVDD D IOVDD EPD PLL_FILT INN INP INN INP INN INP INN INP VREF R.K.UF PF UF INN INP INN INP INN INP INN INP UDIO_VREF_D.V R K R K R K.UF heck for extender conflict TWI ddress x x is the R/W bit. Read -, Write - Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard DU -. // D

18 D V.UF.UF.UF.UF.UF UF.UF UF.V V.V R K R K.V R K R K.UF UF PF DU_MLKO P_/ETH_PTPPPS/SIN_D/SM_ P_/ETH_PTPPPS/SIN_D/PPI_D/SM_/TM_LK DI_PIN DI_PIN DI_PIN DI_PIN DU_FULT_RST_EN DU_EN U Y Y Y Y Y Y Y Y V TLV TSSOP TWI_SL TWI_SD U MLKIN PD/RST S_MODE FULT LRLK LK SDTOUT SDTOUT SL/LK SD/OUT DDR/LTH DDR/IN VDD VDD VDD DVDD IOVDD VT SW SW PLL_FILT MIIS INN INP INN INP INN INP INN INP VREF L.UH R R R R R R VOOST_IN K K.K.K.K.K VOOST_OUT R.K PF R R R R.K.K.K.K R. T UF SMD P ID P ID P ID P ID "MI" "MI" "MI" "MI" DU LFSP P P M D EPD UF UF UF.UF.V.UF heck for extender conflict TWI ddress x x is the R/W bit. Read -, Write - Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard DU -. // D

19 Elizabeth Drive helmsford, M PH: --NLOGD D D. - DSP-S EZ-oard // udio Input V R.K PF R.K FER R.K UF PF.K R R. PF.K R PF.K R. R PF PF R.K PF.K R FER R.K UF PF R.K R. PF R.K PF.K R R. PF PF R.K PF R.K FER R.K UF PF R.K R. PF.K R PF R.K. R PF PF.K R PF.K R FER.K R UF PF.K R. R PF.K R PF R.K. R PF PF IN_LEFT UDIO_VREF_D INP INN D LEFT D RIGHT D RIGHT D LEFT IN_RIGHT UDIO_VREF_D INP INN IN_LEFT UDIO_VREF_D INP INN IN_RIGHT UDIO_VREF_D INP INN U DRZ U DRZ U DRZ U DRZ U DRZ DRZ U U DRZ DRZ U.UF.UF.UF.UF FER V V

20 D DP R T UF P PF R.K J R X DP R T UF P PF R.K OUTP J R X.V DP DP DP R R R T UF P PF T UF P PF T UF P R.K R.K J R X J R X J R X DP DP DP R R R T UF P PF T UF P PF T UF P R.K R.K OUTP OUTP OUTP UDIO_JK_SEL Low for output UDIO_JK_SEL High for input OUTP IN_LEFT OUTP IN_RIGHT OUTP IN_LEFT OUTP IN_RIGHT UDIO_JK_SEL R K I I I I I I ID ID S E U.V.V V DGRQZ QSOP Y Y Y YD J R X J R X J R X "INPUT/OUTPUT" PF R.K PF R.K.UF DP R T UF P J R X DP R PF T UF P PF R.K R.K J R X "INPUT" DP HEDPHE OUT DP U DRZ U DRZ T UF P T UF P R.K R.K J.MM "HEDPHES" V DP R T UF P J R X UF PF R.K OUT (L) OUT (L) J OUT (L) OUT (L) OUT/IN (L) J OUT/IN (L) WHITE (LEFT) WHITE (LEFT) DP R T UF P PF R.K J R X RED (RIGHT) OUT (R) OUT (R) OUT (R) OUT (R) RED (RIGHT) OUT/IN (R) NOTE: THE NUMER INSIDE EH OF THE IRLES IS THE TUL PIN NUMER FOR THE RESPETIVE NETOR. OUT/IN (R) Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard udio onnectors -. // D

21 D "SPDIF IN".V.V.UF J VOUT V N N.V.UF.UF.V R K.V.UF "SPDIF IN/OUT" SPDIF OX INPUT J R X SPDIF_OX_IN.UF.UF R.K R. R.K U RIN- RIN+ N N SNLVDSD SOI V ROUT N R U TLVG S_ U TLVG S_ R K R R.V SPDIF_OPTIL_EN DI_PIN DI_PIN SPDIF_DIGITL_EN HU Data.UF.UF SPDIF_OX_IN SPDIF_OX_OUT JP.V R K U TLVG S_ U TLVG S_ R R SPDIF_DIGITL_EN DI_PIN DI_PIN SPDIF_OPTIL_EN.V R K.UF J VIN V N N Debug "SPDIF OUT".V.UF U SNLVG R.UF. SPDIF_OX_OUT R. J R X SPDIF OX OUTPUT Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard SPDIF -. // D

22 D Please contact your nearest DI sales fice to complete the Non-Disclosure greement (ND) required to receive additional technical information. Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard Master Node -. // D

23 D Please contact your nearest DI sales fice to complete the Non-Disclosure greement (ND) required to receive additional technical information. Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard Master/Slave Node -. // D

24 Elizabeth Drive helmsford, M PH: --NLOGD D D. - DSP-S EZ-oard // Push uttons/leds/reset PE_/PPI_FS/SPI_SELb/URT_TSb/SHR_FLG.V.V MR RESET V LED RED U SNLVG R. R K R K R K U SNLVG.UF.UF.UF.UF SW MOMENTRY R K U DM SOT SYS_HWRST R K TRGET_RESET EI_RESET_IN.V.V.V.V U TLVG S_ U TLVG S_ R R K R K UF UF R K R K R.UF R U LV R U LV SW MOMENTRY R K R K SW MOMENTRY.UF.UF PUSHUTT_EN PUSHUTT_EN LV U LV U LV U R K LV U.V.V Y Y Y Y Y Y Y Y V.V. R YELLOW LED R. R. R. LED GREEN.UF LED YELLOW LED YELLOW SSOP IDTFTPY U R K R K K R R K R K K R K R K R PE_/PPI_FS/SPI_SELb/URT_RTSb/SHR_FLG PE_/PPI_LK/SPI_SELb/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_DH/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_SYN/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SPI_RDY/SHR_FLG. R YELLOW LED R. R. LED YELLOW LED YELLOW R. LED YELLOW. R YELLOW LED K R LEDS_EN.UF U TLVG S_ R UF R K R SW MOMENTRY R K PUSHUTT_EN P_/URT_RTSb/PPI_FS/M_/SM_MSb U TLVG S_ S_ TLVG U U TLVG S_ S_ TLVG U PE_/PPI_FS/SPI_SELb/URT_TSb/SHR_FLG PE_/PPI_FS/SPI_SELb/URT_RTSb/SHR_FLG PE_/PPI_LK/SPI_SELb/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_DH/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_SYN/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SPI_RDY/SHR_FLG K R R K K R R K K R R K K R R K.V FLG_LOOP FLG_LOOP FLG_LOOP FLG_LOOP.UF.V.UF.UF.UF P_/ETH_PTPPPS/SIN_D/PPI_D/SM_/TM_LK P_/ETH_PTPPPS/SIN_D/SM_ P P P RESET RESET POWER

25 D TWI ddress x x is the R/W bit. Read -, Write -.V U TWI_SL TWI_SD SYS_HWRST R K R K VDD SL SD RESET INT INT R K MP QFN GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP EEPROM_EN URT_FLOW_EN URT_EN ML_EN N_EN N_EN DU_EN DU_EN UDIO_JK_SEL SPIFLSH_S_EN SPID_D_EN SPDIF_OPTIL_EN SPDIF_DIGITL_EN.V.UF R K R K R K TWI ddress x x is the R/W bit. Read -, Write -.V U TWI_SL TWI_SD SYS_HWRST VDD SL SD RESET INT INT GP GP GP GP GP GP GP GP PUSHUTT_EN PUSHUTT_EN PUSHUTT_EN LEDS_EN FLG_LOOP FLG_LOOP FLG_LOOP FLG_LOOP R K R K R K MP QFN GP GP GP GP GP GP GP GP DU_EN DU_FULT_RST_EN THUMWHEEL_ ENGINE_RPM_ D_MSTER_SLVE.V R K R K R K.UF Elizabeth Drive helmsford, M PH: --NLOGD DSP-S EZ-oard Stonfig -. // D

26 Elizabeth Drive helmsford, M PH: --NLOGD D D. - DSP-S EZ-oard // EI-.V SPI_SEL_ SPI_SEL_ SPORT_D SPORT_TDV PPI_FS RSVD RSVD PPI_D PPI_D PPI_D SPORT_D SPORT_TDV PPI_FS RSVD PPI_D RSVD PPI_D PPI_D PPI_D SPI_D SPI_D RESET_OUT* SL* GPIO TMR_ SPI_RDY RSVD TWI_* SPI_SEL/SPI_SS* SD* GPIO GPIO GPIO TMR_ RSVD RSVD RSVD RESET_IN* URT_RX PPI_D PPI_D VIN US_V PPI_D PPI_D RSVD PPI_D SPORT_INT URT_TX WKE* EXT_OOT SLEEP* RSVD RSVD TMR_ GPIO SL* SPI_MISO SPI_SEL_ SPORT_LK SPORT_FS SPORT_D PPI_FS RSVD PPI_INT PPI_D PPI_D PPI_D PPI_D PPI_D TMR_D* GPIO* GPIO GPIO SD* SPI_LK SPI_MOSI SPORT_D SPORT_FS SPORT_LK PPI_LK RSVD PPI_D PPI_D PPI_D PPI_D PPI_D PPI_D VIO PS_IN RSVD LKOUT RSVD PPI_D SPORT_NVT SPORT_NVT R K P_/ETH_PTPPPS/SIN_D/PPI_D/SM_/TM_LK P_/ETH_PTPPPS/SIN_LK/PPI_D/SM_/TM_LK P_/ETH_PTPLKIN/URT_TXb/PPI_D/SM_ P_/ETH_PTPUXIN/URT_RXb/PPI_D/SM_/TM_I P_/ML_LK/SIN_D/PPI_D/SM_RDY/ETH_PTPUXIN P_/ML_SIG/PPI_D/SM_/ETH_PTPUXIN P_/URT_RTSb/PPI_FS/M_/SM_MSb PD_/URT_TSb/PPI_D/M_/SM_D PD_/URT_RXb/PPI_D/SM_/TM_I PD_/URT_TXb/PPI_D/SM_ PD_/PPI_D/PWM_TRIPb/ML_LKOUT/SM_D PD_/PPI_D/PWM_H/SM_D PE_/SPI_MOSI/PPI_D/SM_Eb PE_/SPI_MISO/PPI_D/SM_Eb PE_/PPI_D/PWM_L/SM_D PE_/PPI_LK/SPI_SELb/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_DH/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_SYN/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SHR_FLG PE_/PPI_D/SPI_SELb/SPI_RDY/SHR_FLG PE_/PPI_D/PWM_SYN/TM_TMR/SM_D PE_/PPI_D/PWM_DL/URT_RTSb/SM_D PE_/PPI_D/SPI_SELb/URT_TSb/SM_D/SPI_SSb PE_/PPI_D/SPI_SELb/SPI_RDY/SM_D PE_/SPI_LK/PPI_D/SM_MSb DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN TWI_SL TWI_SD TWI_SL TWI_SD P_/URT_TXb/SPI_SELb/M_ P_/URT_RXb/M_/TM_I SYS_HWRST EI_RESET_IN PE_/PPI_D/PWM_SYN/TM_TMR/SM_D P_/LP_K/PWM_TRIPb/TM_TMR/SM_WEb P_/LP_D/TM_TMR/N_RX/SM_D/TM_I P_/LP_D/PWM_H/TM_TMR/SM_D SYS_LKOUT P.MM PE_/SPI_MOSI/PPI_D/SM_Eb PE_/SPI_MISO/PPI_D/SM_Eb PE_/SPI_LK/PPI_D/SM_MSb PD_/URT_RXb/PPI_D/SM_/TM_I PD_/URT_TXb/PPI_D/SM_ PD_/URT_TSb/PPI_D/M_/SM_D PD_/SPI_SELb/M_/SM_b/SPI_SSb P_/URT_RTSb/PPI_FS/M_/SM_MSb PE_/PPI_FS/SPI_SELb/URT_TSb/SHR_FLG PE_/PPI_FS/SPI_SELb/URT_RTSb/SHR_FLG V P_/SPI_SELb/SPI_RDY/M_T/SM_ P_/N_RX/SPI_SELb/SM_MSb/TM_I P_/SPI_MOSI/TM_LK P_/SPI_MISO P_/LP_LK/PWM_L/SPI_SELb/SM_REb PD_/SPI_SELb/M_/SM_b/SPI_SSb P_/SPI_LK P_/SPI_SELb/SPI_RDY/M_T/SM_

27 Elizabeth Drive helmsford, M PH: --NLOGD D D. - DSP-S EZ-oard // EI-/.V.V.V SPI_SEL_ SPI_SEL_ SPORT_D SPORT_TDV RSVD SYN_ SYN_RD SYN_D SYN_D SYN_D SPORT_D SPORT_TDV RSVD SYN_ SYN_D SYN_MS SYN_D SYN_D SYN_D SPI_D SPI_D RESET_OUT* SL* GPIO TMR_ SPI_RDY RSVD TWI_* SPI_SEL/SPI_SS* SD* GPIO GPIO GPIO TMR_ RSVD RSVD RSVD RESET_IN* URT_RX RSVD SYN_D VIN US_V RSVD RSVD RSVD RSVD SPORT_INT URT_TX WKE* SLEEP* RSVD RSVD RSVD TMR_ GPIO SL* SPI_MISO SPI_SEL_ SPORT_LK SPORT_FS SPORT_D RSVD SYN_ SYN_INT SYN_D SYN_D SYN_D RSVD RSVD TMR_D* GPIO* GPIO GPIO SD* SPI_LK SPI_MOSI SPORT_D SPORT_FS SPORT_LK RSVD SYN_ SYN_D SYN_D SYN_D SYN_D RSVD RSVD VIO PS_IN RSVD LKOUT SYN_WR SYN_D SPORT_NVT SPORT_NVT SYN_ SYN_ SYN_ SYN_ SYN_ SYN_GH SYN_RDY SYN_D SYN_D SYN_D SYN_ SYN_ SYN_ SYN_G SYN_D SYN_R SYN_D SYN_D SYN_D SYN_ SYN_ PWM_TRIP SYN_ SYN_ PWM_L PWM_L PWM_DH PWM_SYN SYN_ SYN_ SYN_ SYN_ PWM_H PWM_H PWM_H PWM_L PWM_DL RSVD PWM_TRIP SYN_MS SYN_D VIN US_V SYN_ SYN_MS RSVD SYN_MS SYN_ RSVD M_ RSVD M_ M_ M_ M_ M_LK RSVD RSVD RSVD RSVD RSVD RSVD RSVD SYNH_E RSVD RSVD SYN_D SYN_D SYN_D M_T RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SYN_E SYN_D SYN_D SYN_D SYN_D VIO PS_IN M_FS M_T RSVD SYN_D SYN_ SYN_ SYN_ SYN_ SYN_ R K P_/ETH_PTPPPS/SIN_D/SM_ P_/ETH_TXD/SM_ P_/ETH_TXD/SM_ P_/ETH_MD/SM_ P_/ETH_MDIO/SM_ P_/ETH_RXD/SM_ P_/ETH_RXD/SM_ P_/ETH_RXLK_REFLK/SM_ P_/ETH_RXTL_RS/SM_ P_/ETH_RXD/SM_ P_/ETH_RXD/SM_ P_/ETH_TXTL_TXEN/SM_ P_/ETH_TXLK/SM_ P_/ETH_TXD/SM_ P_/ETH_TXD/SM_ P_/LP_D/TM_TMR/PWM_L/SM_D/NT_DG P_/LP_K/PWM_TRIPb/TM_TMR/SM_WEb P_/ETH_PTPPPS/SIN_D/PPI_D/SM_/TM_LK P_/ETH_PTPPPS/SIN_LK/PPI_D/SM_/TM_LK P_/LP_D/TM_TMR/N_RX/SM_D/TM_I P_/LP_D/PWM_DH/SM_D/NT_ZM P_/ETH_PTPLKIN/URT_TXb/PPI_D/SM_ P_/ETH_PTPUXIN/URT_RXb/PPI_D/SM_/TM_I P_/ML_LK/SIN_D/PPI_D/SM_RDY/ETH_PTPUXIN P_/ML_SIG/PPI_D/SM_/ETH_PTPUXIN P_/ML_DT/PWM_H/SM_/ETH_PTPUXIN P_/LP_D/PWM_H/TM_TMR/SM_D P_/LP_D/N_TX/SM_D P_/LP_D/PWM_L/TM_TMR/SM_D P_/LP_D/PWM_H/SM_D P_/LP_D/PWM_DL/SM_D/NT_UD P_/SPI_SELb/SPI_RDY/M_T/SM_ P_/N_TX/SM_MSb P_/N_RX/SPI_SELb/SM_MSb/TM_I P_/LP_LK/PWM_L/SPI_SELb/SM_REb P_/URT_RTSb/PPI_FS/M_/SM_MSb PD_/PPI_D/PWM_TRIPb/ML_LKOUT/SM_D PD_/PPI_D/PWM_H/SM_D PD_/URT_TSb/PPI_D/M_/SM_D PD_/SPI_SELb/M_/SM_b/SPI_SSb PD_/LP_LK/PWM_DL/TRE_LK PD_/LP_K/PWM_SYN PD_/LP_D/PWM_TRIPb/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_L/TRE_D PD_/LP_D/PWM_H/TRE_D PD_/LP_D/PWM_DH/TRE_D/TM_LK PD_/LP_D/PWM_L/TRE_D/TM_LK PD_/URT_RXb/PPI_D/SM_/TM_I PD_/URT_TXb/PPI_D/SM_ PE_/SPI_MOSI/PPI_D/SM_Eb PE_/SPI_MISO/PPI_D/SM_Eb PE_/PPI_D/PWM_L/SM_D PE_/PPI_D/PWM_SYN/TM_TMR/SM_D PE_/PPI_D/PWM_DL/URT_RTSb/SM_D PE_/PPI_D/SPI_SELb/URT_TSb/SM_D/SPI_SSb PE_/PPI_D/SPI_SELb/SPI_RDY/SM_D PE_/SPI_LK/PPI_D/SM_MSb TWI_SL TWI_SD TWI_SL TWI_SD SYS_HWRST EI_RESET_IN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN DI_PIN PE_/PPI_D/PWM_SYN/TM_TMR/SM_D P_/LP_K/PWM_TRIPb/TM_TMR/SM_WEb P_/LP_D/TM_TMR/N_RX/SM_D/TM_I P_/LP_D/PWM_H/TM_TMR/SM_D P_/URT_TXb/SPI_SELb/M_ P_/URT_RXb/M_/TM_I P_/SPI_SELb/SPI_SSb P_/SPI_D P_/SPI_D P_/SPI_MOSI P_/SPI_MISO P_/SPI_LK PE_/PPI_LK/SPI_SELb/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_SYN/SPI_SELb/SHR_FLG PE_/PPI_D/PWM_DH/SPI_SELb/SHR_FLG SYS_LKOUT P.MM P_/ETH_PTPPPS/SIN_D/SM_ PE_/PPI_D/SPI_SELb/SPI_RDY/SM_D P_/URT_TXb/SPI_SELb/M_ P_/URT_RTSb/PPI_FS/M_/SM_MSb PD_/SPI_SELb/M_/SM_b/SPI_SSb P_/SPI_SELb/SPI_RDY/M_T/SM_ P_/URT_RXb/M_/TM_I PD_/URT_TSb/PPI_D/M_/SM_D.MM P PE_/SPI_MOSI/PPI_D/SM_Eb PE_/SPI_MISO/PPI_D/SM_Eb PE_/SPI_LK/PPI_D/SM_MSb PD_/URT_RXb/PPI_D/SM_/TM_I PD_/URT_TXb/PPI_D/SM_ PD_/URT_TSb/PPI_D/M_/SM_D PD_/SPI_SELb/M_/SM_b/SPI_SSb P_/URT_RTSb/PPI_FS/M_/SM_MSb V V R R R R R R R ll resistors shuold be placed close to U R R R R R R R R

28 D Test Points are scattered on P for Test Measurement Purposes. LEL "" LL TPs TP TP TP TP TP GP UF DP_VREG DP_VREG V UF UF PF UF R R PF R.K.K VR VREG VDD PVIN PVIN PVIN OMP EN FG PVIN PVIN PVIN OMP EN UK UK SYN/MODE RT F ST SW SW SW DL P DL SW SW SW ST F R.UF R R.UF.K K K R R R U S Da G Db S Da G Db SI K.K K R.K L.UH L.UH UF UF UF Remove jumpers when measuring power UF P R.. P R. VDD_INT.V TP TP SJ? SHORTING JUMPER DEFULT=INSTLLED SJ? SHORTING JUMPER DEFULT=INSTLLED UF PVIN OMP UK ST SW SW F.V PV_SOURE VDD_INT U IN- IN+ IN- VPU VS SL SD.V R K R K R K TP TP TWI_SL TWI_SD UF R R PF R.K EN FG PVIN OMP EN DP LFSP UK P P ST SW SW F P P PWRGD.UF R.K R K L.UH UF UF P R. P R..V TP SJ? SHORTING JUMPER DEFULT=INSTLLED VDD_EXT SJ? SHORTING JUMPER DEFULT=INSTLLED VDD_INT_SOURE VDD_EXT IN+ IN- WRNING RITIL PV T PV_SOURE IN+.V EPD IN QFN R K.UF Elizabeth Drive helmsford, M PH: --NLOGD TWI address x where x is the R/W bit. Read -, Write - DSP-S EZ-oard Power // -. D

29 Elizabeth Drive helmsford, M PH: --NLOGD D D. - DSP-S EZ-oard // attery/n/ Power VR OOT SW EN F VIN OMP RT/LK.UF.UF R.K R.K UF L.UH D D-G SH SH F D MRSTG FER PF D GSOT FER UF FER PF "attery" HSOI TPS U PG EN VOUT VIN DJ N DPPZ LFSP UF R K R.K R.K R.K.UF PV_MS V PG EN VOUT VIN DJ N LFSP DPPZ U UF K R R.K.K R.K R.UF PV_MS/SLV V PF R.K R.K PF P PWR V REGULTOR_EN V JUMPER SHORTING REGULTOR_EN SJ? DEFULT=Pin _POWER_EN N_INH ID JP D MMZVTG MMZVTG D D MRSTG UF UF P.MM VR EN INPUT OUTPUT DPUJZ-. TSOT.V.V UF UF V V V REG DIS