Design of Analog Integrated Circuits

Transcription

1 Design f Analg Integated Cicuits Opeatinal Aplifies Design f Analg Integated Cicuits Fall 01, D. Guxing Wang 1

2 Outline Mdel f Opeatinal Aplifies Tw Stage CMOS Op Ap Telescpic Op Ap Flded-Cascde Op Ap Refeence Bks: Razavi: Chap. 9; Chap. 3 Gay: Chap. 6

3 A Siplified Mdel f Real Aplifie An diffeential aplifie lineaized at a DC pint 1 ut v id I B1 v OS PSRR v dd, v ss v v ic v id v in in C in a( f ) v in v dd I B Ac v ic v ss 3

4 The Basic Opap Cicuit One f the st widely used cicuit stuctue It is als called Mille Op Ap (due t Mille cpensatin cap Cc)

5 Cicuit Decpsitin Tw gain stages Each stage pvides vltage gain s as t appach the vey high gain f an ideal Op Ap Fist input stage fed by the diffeential pai Q1-Q, with cuent i lad Q3-Q4 As discussed in Chapte IV, the input diffeential pai pvides vltage gain and cn-de ejectin ati (CMRR) It als pefs diffeential-t-single-ended cnvesin Secnd utput stage fed by cn-suce (CS) aplifie Q6 and its cuent-suce lad Q7 It pvides additinal vltage gain Its gain is als used in Mille-ultiplied cap (Cc) t educe the cpensatin cap size, while achieving gd stability

6 Biasing Cuent i fed by Q8, Q5 and Q7 pvides the bias cuents Q5 f the input diffeential pai Q7 f the utput stage This cuent i is fed by a efeence cuent I REF thugh Q8 Geneally I REF is chsen t be cnstant-g cuent s as t aintain cnsistent Opap gain ve pcess, vltage supply, tepeatue vaiatins (PVT)

7 Biasing: Systeatic DC Offset Input dc ffset Rand ffset: due t device isatches Systeatic ffset: due t p biasing Miniu systeatic ffset biasing design If n systeatic ffset, then Q6 and Q4 have the sae V GS And this cuent ust be exactly equal t the cuent supplied by Q7 S in de t iniize the systeatic ffset, the fllwing cnditin ust be et ) ( 4 ) ( 6 ) ( 6 I L W L W I I L W L W I 5 ) ( 7 ) ( 7 5 ) ( 7 ) ( 4 ) ( 6 ) ( L W L W L W L W

8 Input Cn-Mde Range and Output Swing Input Cn-Mde Range Lwest V ICM has t ensue Q1 and Q in active (satuatin) egin Highest V ICM has t ensue Q5 in active (satuatin) egin Vss V OV 3 V tn V tp V ICM Vdd V OV 5 V tp V OV1 Output Swing Lwest v has t ensue Q6 in active (satuatin) egin Highest v has t ensue Q7 in active (satuatin) egin Vss V OV 6 v Vdd V OV 7

9 Equivalent Cicuit Tw-Pt Sall-Signal

10 Vltage Gain Refe t the sall signal equivalent cicuit ) ( ) ( ) ( : : : tan ) ( : 1 : 1 : tan id in g g A A v v Gain Ttal g R G A dc gain stage nd R ipedance utput stage nd g G ce tanscnduc stage nd g R G A dc gain stage st R ipedance utput stage st g g G ce tanscnduc stage st R

11 Fequency Respnse Refe t the sall signal equivalent cicuit C1 is the ttal capacitance at the utput nde f 1 st stage C C C C C C 1 gd db gd 4 db4 gs6 C epesents the ttal capacitance at the pap utput nde, including lading capacit C L C Cdb6 Cdb7 C gd 7 C L Dinant ple fed by Mille cap Cc(C1 is negligible) P1 nd ple fed by C f f 1 R G 1 Ze fed by Cc (between input and inveting utput) f P Z R G C G C C C c

12 Hw t Chse Ple lcatins Recall unity-gain-bandwidth: assuing ne ple syste f t A v f P1 G 1 C We can chse the ple lcatins s that the pap can be appxiated as a ne ple syste within its unity-gainbandwidth f P and f Z have t be highe than f t C F f P > f t G 1 C C G C F f Z > f t G G 1 O is this gd enugh? We will evisit Ze Pble late

13 Phase Magin Mille cap Cc is utilized f ple-splitting, i.e., adding Cc lwes the dinant ple, while pushing away the nd ple beynd f t By caeful design, it is pssible t have abut 90 phase shift at f t, leaving us a cftable phase agin abut 90 Hweve, if the nd ple is clse enugh t ft, the pap will expeience uch e phase shift, eating up the phase agin And the ze has the sae negative effect n the pap s phase agin the ze in n the ight half plane-rhp (i.e., it is >0) f Z G C C It inceases phase shift and thus deceases the phase agin T ake it wse, the RHF ze als inceases gain and thus educes the gain agin Geneally speaking, an pap with a RHP ze is a bad design and ptentially unstable

14 Bde Plt f Tw Stage CMOS Opap RHP ze educes gain agin

15 Ze: Slving Right Half Plane (RHP) Pble RHP ze educes gain agin and akes pap unstable Slutin: adding a esistance R in seies with Cc Nw the new ze is calculated as: f Z 1 C C ( 1 G R)

16 Ze: LHP Bette? With RC lead cpensatin, the new ze is f Z 1 C C ( 1 G R) We can chse an R value (e.g. R appaching 1/G) s that the ze is ving fathe away f ft, aking it negligible t phase shift at ft; O we can chse R value exactly the sae as 1/G. The ze is at infinity; O we can futhe incease R value, e.g., R>1/G. Nw the ze is at left half plane (LHP); it still inceases the phase shift but it als educes the gain (s ipve the gain agin) O bette (?) we can chse such an R value that it ves the ze int LHP and cancel the nd ple.

17 Ze-Ple Cancellatin: Is It Bette? Recall the ze and nd ple f Z 1 C C ( 1 G R) G C Setting the equal, we get an R value: C 1 R ( 1) C C G Nw, we ve the ze int LHP, ight at the nd ple; Sunds like an inteesting idea t cancel the nd ple with the ze; Unftunately, the exact value f C is usually unknwn since it depends n the lading Fd f thught: hw we can play with R value t ptiize the fequency cpensatin t achieve best phase agin? And independent f pcess vaiatin (tacking G)? f P

18 Hw Abut the Ideal Cuent Suce Bias cicuit A bias cuent is independent f bth the supply vltage and the MOSFET theshld vltage; It is deteined by a single esist and the device diensins. g I I V B B GS13 1 nc 1 nc V x x GS1 W L W L I B 1 R 13 R V V GS1 GS13 V V t t I B C n x ( W L) 1 R B ( W ( W L) L)

19 Cnstant g Bias Cicuits Cnstant g g ( W L) 1 Cx W L 1 I B 1 R B 1 n W L 13 n-channel device g i g 1 I I Di B ( W ( W L) L) i 1 p-channel device g i g 1 I p I n Di B ( W ( W L) L) i 1

20 Slew Rate (SR)-Cncept A unity-gain fllwe with 1V step input One side f input diffeential pai will be tun ff

21 Slew Rate (SR)-Tw Stage Opap Mdel The input stage can be deled as a cuent suce; ne side f the diffeential pai is ff The the side cnducts all cuent, acting as a cuent suce The nd stage can be deled as an integat SR I C C

22 Slew Rate (SR) and Unity-Gain-Bandwidth (ft) Recall SR and unity-gain-bandwidth ft SR I C C P1 Cbining these tw equatins, we btain: f t 1 A I SR f t f tv G Thus, f a given ft, the SR is deteined by the vedive vltage f the input diffeential pai v f G 1 OV C C

23 Outline Ideal Opeatinal Aplifies Tw Stage CMOS Op Ap Telescpic Op Ap Flded-Cascde Op Ap

24 Single-Stage Cascde Op Ap Many pap applicatins see pue capacitive lads Nt necessay t have lw utput ipedance If we design an pap which has nly ne high ipedance nde at the utput: N fequency cpensatin is needed; the dinant ple is at the utput and the lad capacitance siply helps stability; High speed since all intenal ndes having elatively lw ipedance and lw capacitance These paps ae als called Opeatinal Tanscnductance Aplifies (OTAs) since thei tanscnductance (utput cuent vs. input vltage) is ne f the key pefance paaetes The Cascde Op Ap can be categized as OTA and is ne f the st ppula den CMOS paps

25 Telescpic Op Ap The telescpic pap is als knwn as the cascde pap, whee it uses cascde cuent i at its utput lad t achieve high utput ipedance Mtivatin: single-stage pap t achieve the sae gain as in twstage pap and t siplify the fequency cpensatin The fequency cpensatin is dne by adding lad capacitance Hw t d it: Tw-stage pap gain is abut 1/(g ds ) Recall cascde cuent i utput ipedance is abut g ( ds )

26 The Cicuit It nly has ne high ipedance nde at the utput, whee the dinant ple is; Fequency cpensatin is dne by adding lad capacitance; Questin: whee is the fist nndinant ple?

27 Biasing The cuent ae balanced s, I DS = I REF except f M13 which has, I DS13 = I REF Since, I 1 = I = I REF Then, V GS3 = V GS4 = V GS9 This als iplies that, V DS4 = V DS3 Siilaly, V DS5 = V DS6

28 Output Swing Assuing diffeential input signal is ze: V id = 0 Then, V OUT = V DD V TO V DSAT = V G6 The gate f M8 is als at, V DD V TO V DSAT Due t its cnnectin t M11, s V OUT = V G6 = V G8 The swing in the psitive diectin will be, V OUT.MAX = V G6 + V T But since V OUT = V G6 Thus utput swing is liited t nly 1 V T in the psitive diectin!

29 Output Swing cnt. In the negative diectin, V OUT.MIN = V G8 V T but since V OUT = V G8 the swing is nly 1 V T again. Thus the ttal utput swing is nly V T, nt gd f st applicatins. S is thee a slutin f the liited utput swing? we culd use a high swing cascde cnfiguatin as was descibed befe. O Flded-cascde pap

30 Outline Ideal Opeatinal Aplifies Tw Stage CMOS Op Ap Telescpic Op Ap Flded-Cascde Op Ap

31 The Cicuit I B I B I

32 Cicuit Decpsitin CS aplifie (diffeential pai) with CG aplifie (cascde tansists) Input stage fed by the diffeential pai Q1-Q Q3-Q4 f the CG aplifie cascde tansists Cascde cuent i Q5-Q8 fs the utput cuent suce lad s as t achieve the high utput ipedance. Q9/Q10//Q11 ae biasing tansists This is als knwn as flded-dwn cascde p ap. Why?

33 Biasing Q11 pvides the cnstant cuent I utilized f biasing the diffeential pai; Input diffeential pai Q1-Q is peating at I/ f each tansist Q9/Q10 pvide the cnstant cuent I B. Each f cascde tansists Q3-Q4 is biased at (I B -I/) I B has t be geate than I in de t keep Q3/Q4 in active egin and f lage signal peatin (duing SR liiting, all I will g thugh Q1 Q) Usually cnsues e pwe than telescpic cascde p ap. V BIAS1 / V BIAS / V BIAS3 has t be caefully selected in de t achieve ptiu input cn-de ange and utput vltage swing.

34 Input Cn-Mde Range and Output Swing Input Cn-Mde Range Highest V ICM has t ensue Q1 and Q in active (satuatin) egin Lwest V ICM has t ensue Q11 in active (satuatin) egin Vss V V OV11 tn V OV1 V ICM Vdd V V OV 9 tn Nte: V ICM can be lage than V DD, a significant ipveent ve twstage pap. Output Swing Lwest v has t ensue Q6 in active (satuatin) egin Highest v has t ensue Q10 and Q4 in active (satuatin) egin By caefully selecting VBIAS1 s that Q10 peates at the edge f satuatin Vss V V V v OV 7 OV 5 tn Vdd V V OV 4 OV10 Nte: Flded-cascde has lage utput swing than telescpic.

35 Ipving Output Swing Vss V OV 7 V OV 5 v Vdd V OV 4 V OV10

36 Equivalent Cicuit Sall-signal equivalent cicuit f the flded-cascde CMOS pap. This cicuit is in effect an OTA.

37 Vltage Gain Refe t the sall signal equivalent cicuit Tanscnductance Output esistance The dc pen-lp gain Its gain is abut ½ f that f a telescpic cascde pap 1 g g G ) 10 )( 4 4 ( g R g R R R R )} ( )] 10 ( 4 4 {[ 1 g g g R G v A

38 Fequency Respnse Refe t the sall signal equivalent cicuit C L is the ttal capacitance at the utput nde Dinant ple fed by C L and utput esistance Unity gain fequency Adding CL f t f P1 A v 1 RC L f P1 G C L Deceases pap s bandwidth (unity gain fequency) Ipves pap s stability

39 Slew Rate (SR) When a lage input signal is applied, the input diffeential pai can be deled as a cuent suce; ne side f the diffeential pai is ff The the side cnducts all bias cuent I, acting as a cuent suce One f cascde tansists will cay a cuent f (I B -I), while the the caying a cuent f I B The utput cuent t C L will then be I B -(I B -I)=I The slew ate: SR I C L F a given ft, the SR is deteined by the vedive vltage f the input diffeential pai I SR f t f tv G OV

40 Input Cn-Mde Range Rail-t-Rail

41 Rail-t-Rail Opeatin Tw paallel cpleentay input stages Q5-Q6 ae the cascde tansists f the Q1-Q NMOS input pai Q7-Q8 ae the cascde tansists f the Q3-Q4 PMOS input pai V ICM can be highe than V DD and lwe than V SS, achieving ail-t-ail peatin. Hweve: When V ICM is clse t V DD, nly Q1-Q pai is peating and Q3-Q4 pai is ff; The ttal gain is: G R n When V ICM is clse t V SS, nly Q3-Q4 pai is peating and Q1-Q pai is ff; The ttal gain is: When V ICM is in the id-ange, bth Q1-Q and Q3-Q4 pais ae peating; The ttal gain is: Questin: ail-t-ail peatin with cnsistent gain? A v A v G R p A ( G G R v n p)

42 Suay The IC p ap is a vesatile cicuit building blck Ideally nly aplify the input diffeence signal Ideally infinite input esistance and ze utput esistance Vitual Gund: ptentials at tw input teinals tack each the when applying negative feedback On-chip CMOS p aps Usually dive capacitive lad s d nt need ze utput esistance High gain: tw stages cascde aplifies Tw-stage p aps Mille cpensatin Lead cpensatin t ve RHP ze int infinity LHP SR is deteined by the fist-stage bias cuent and Mille cap Cascde p aps Fequency cpensatin is dne by adding inceasing lad capacitance Telescpic p aps have liited input cn-de ange and utput swing Flded-cascde p aps have bette ICM and utput swing at the cst f highe cuent cnsuptin and lwe gain (abut half) SR is deteined by the input pai bias cuent and lading cap