On Behavioral Model Equivalence Checking for Large Analog/Mixed Signal Systems

Transcription

1 On ehaviral Mdel quivalence Checking fr Large Analg/Mixed Signal Systems Amandeep Singh and Peng Li Department f lectrical and Cmputer ngineering Texas A&M University, Cllege Statin, TX {amandeep.singh, pli}@tamu.edu Abstract This paper presents a systematic, hierarchical, ptimizatin based semi-frmal equivalence checking methdlgy fr large analg/mixed signal systems such as PLLs, ADCs and I/O s. We verify the equivalence between a behaviral mdel and its electrical implementatin ver a limited, but highly likely, input space defined as the Cnstrained ehaviral Space. Further, we clearly distinguish between the behaviral and electrical dmains and define mappings between the tw dmains t allw fr calculatin f deviatin between the behaviral and electrical implementatin. The verificatin prblem is then frmulated as an ptimizatin prblem which is slved by interfacing a SQP based ptimizer with cmmercial circuit simulatin tls. The prpsed methdlgy is then applied fr equivalence checking f a PLL as a test case. Keywrds-Analg Circuits, Frmal verificiatin, quivalence Checking, System Verificatin; I. INTRODUCTION The recent advances in semicnductr technlgy and cntinued transistr scaling have allwed designers t integrate increasingly mre functinality n the same chip. This has resulted in develpment f cmplex mixed signal system n chip (SC) designs. Further, increasingly variable manufacturing prcess, limited vltage headrm and limited pwer budgets has lead t increasingly cmplex analg circuits. This increased design cmplexity necessitates the develpment f efficient verificatin methdlgies fr mixed signal systems t prevent cstly design errrs and reduce develpment time. The current state-f-the-art verificatin methdlgies and tls have enabled efficient verificatin f cmplex digital circuits with millins f gates; hwever, the same cannt be said fr analg r mixed signal circuits. The verificatin f analg circuits is still largely dne manually using SPIC level simulatins and is highly dependent n the skills and intuitin f the designer. This is a time cnsuming task. Als, SPIC level verificatin fr large systems invlving a number f big mixed signal cmpnents invlves huge cmputatinal cmplexity. The lack f frmal verificatin fr analg/mixed signal blcks ften results in nn-detectin f functinal errrs in the design leading t re-spins and increase in time t market. While being a significant present research challenge, autmated design verificatin fr analg/mixed signal systems is crucial. Several methds have been prpsed fr frmal verificatin f analg circuits [1-9]. Mst f these methds can be categrized int tw categries, equivalence checking and mdel checking. quivalence checking cmpares the utput f tw different mdels fr a given set f input cnditins [1]. Fr analg circuits, the exact same magnitudes f current and vltage may nt be attained, hence, an errr bund is defined and the mdels are said t be equivalent if the errr lies within this bund. In [1] the authrs prvide a gd summary f the equivalence checking methds prpsed till date. Mdel checking [1] invlves representing the design t be verified in frm f a transitin system. The specificatins f the design are translated t tempral lgic frmulas. State explratin algrithms are then used t verify if the specificatins are satisfied r nt. Hwever, mdel checking algrithms [8] [9] have als achieved limited success fr frmal verificatin f analg circuits. As illustrated in Fig. 1, mst f these existing methds ften require the cnversin f a high-dimensinal cntinuus state space t a large discrete equivalent s as t apply lean-like verificatin [4][5][7]. The resulting state explsin limits the applicatin f these methds t ty circuits f very lw dimensinality. Further, the inherent apprximatins in discretizatin can render these methds practically infrmal. Als, many f the methds prpsed have limited practicality as they assume a linear behavir fr the circuits under cnsideratin [6]. Recently an interesting blean-satisfiability based apprach has been prpsed [3]. The methdlgy cleverly leverages recent advances in SAT engine fr analg verificatin. Hwever, it als suffers frm scalability issues, as it is difficult t slve the satisfiability prblem fr large cmplex systems like phase lcked lps. Further, the run time increases expnentially as the granularity f the discretized device I-V tables used t frmulate the satisfiability prblem decreases. In this paper we prpse an ptimizatin based, hierarchical behaviral mdel equivalence checking methdlgy that is nt necessarily cmpletely frmal, but yet systematic and applicable t large designs such as PLLs, ADCs and I/O s. We use behaviral mdeling (e.g. Verilg AMS) as a system verificatin vehicle. The prpsed methdlgy facilitates feasible behaviral mdel equivalence checking under the fllwing system cntext. We assume that the desired system behavirs are encded in a set f blck-level behaviral mdels, r the reference system behaviral mdel (RS). Hence, the desired system perfrmance specificatins are als reflected in the simulated perfrmances f the RS. A given detailed electrical (circuit) implementatin, e.g., represented by a set f (extracted) blck-level SPIC netlist, is checked (verified) against the RS n an individual blck basis. ither, the implementatin is deemed as equivalent, r the check is incnclusive due t the cnservative nature f the check. In additin t the afrementined equivalence checking against a given glden RS, the prpsed wrk als serves an intrinsically related purpse: cmpare an existing electrical-level design implementatin against its crrespnding behaviral /10/$ I 55

2 Analg Circuit (Cntinuus State Space) State space discretizatin Apprximate FSM Mdel Frmal Verificatin (under all inputs) State space explsin!! Figure 1: Limitatins f current analg verificatin methds. mdel s as t prvide guidance fr behaviral mdeling. The prpsed methdlgy has several key characteristics: System-level behaviral simulatins are used as a basis t derive a limited but sensible set f input stimuli fr verificatin. Inherent abstractin in behaviral mdeling, which cntributes t the deviatin f the behaviral mdel frm its electrical cunterpart, is specifically targeted in ur verificatin; such mdeling abstractin is mathematically characterized by defining tw signal dmains and mapping functins between them. quivalence checking is frmulated as a cnstrained ptimizatin prblem and slved by interfacing behaviral and SPIC-level simulatrs that cntrast the behaviral mdel with the SPIC netlist. System equivalence checking is brken int individual blck-level checks, and hence perfrmed hierarchically; this makes the apprach scalable fr large designs. The rest f the paper is rganized as fllws: Sectin II gives the prblem descriptin; Sectin III prvides the detailed descriptin f the mapping functins and signal dmains used; Sectin IV frmulates the verificatin prblem as an ptimizatin prblem. Finally, Sectin V shws the results f ur verificatin methdlgy using a Phase Lcked Lp as a test case. II. PRLIMINARIS The prpsed semi-frmal, hierarchical, ptimizatin based equivalence checking methdlgy aims at verifying equivalence between the system behaviral mdel called the reference system behaviral mdel (RS) against detailed electrical, i.e. transistr level implementatin. A. Prblem Definitin We view that the input and utput signals t/frm each blck f the reference system behaviral mdel, hithert referred t as the ehaviral Signals, belng t a behaviral signal dmain Ω. Similarly, we define an electrical signal dmain Ω, which cntains the input and utput signals t/frm each blck f the electrical transistr level implementatin. T enable verificatin f large analg/mixed signal designs we als define a limited, but mst likely, input behaviral signal space fr the behaviral mdels called the Cnstrained ehaviral Space (IS). The mechanics f generating the IS fr each blck are discussed in sectin II.. The equivalence check is then perfrmed nt ver the universe f all pssible inputs in the behaviral signal space, instead, nly w.r.t the chsen set f sensible input stimuli as defined by the Cnstrained ehaviral input space. Fr each blck-level behaviral mdel, and a given behaviral input and the resulting behaviral utput, we perfrm equivalence check by asking the essential questin: des the crrespnding blck-level electrical mdel (spice netlist) retain the same (behaviral) input and utput crrespndence? The abve questin wuld have been trivial t answer if bth mdels perate in the same signal dmain. Hwever, the fact that such equivalence check has t be cnducted acrss tw signal dmains intrduces cmplicatins. As such, we define tw mapping functins f - and g - t map the signals frm the behaviral signal space t the electrical signal space and viseversa. The functin f - is a ne t many mapping while the functin f - is a many t ne mapping. The generatin f these mapping functins is dependent f the mdule being verified and is explained in Sectin IV. The btained behaviral IS are mapped t Ω using the mapping f - which is then used t drive the verificatin n an individual blck basis as shwn in Fig.. ach behaviral input in the IS is mapped int t a set f detailed electrical inputs which are then used t simulate the electrical transistr (Spice) level circuit. The resulting electrical utputs are mapped back t the behaviral dmain t cmpare with the reference behaviral utput f the behaviral mdel. The maximum discrepancy f the tw is used as metric t judge the equivalence.. Generatin f Cnstrained ehaviral Space T allw fr a scalable verificatin methdlgy we recgnize that the inputs t a specific circuit blck are cnstrained by the structure f the entire design, i.e. the inputs t each blck in the mdel cannt be any arbitrary input, and instead, nly a subset f them (Figure 3). This cnstrained behaviral signal space fr the behaviral mdel frms the IS. T generate the IS fr each blck in the behaviral mdel, the RS is simulated using a set f typical system-level simulatin stimuli, such as the nes that are used t measure system design specs (e.g. lck-in time fr PLL etc). Upn the cmpletin f each system-level simulatin, the behaviral input (as well as the crrespnding behaviral utput) is retained fr each circuit blck. The cmplete set f such behaviral inputs defines the IS fr the blck. In this case, quivalence Checking essentially checks the electrical implementatin against the RS under the typical input excitatins that are emplyed t measure system design specs. If the equivalence check succeeds, the crrespnding design specs f the RS wuld be deemed as reflecting thse f the actual implementatin. The use f the verificatin allws efficient determinatin f achieved system perfrmance specificatins withut resrting t expensive flat (SPIC) simulatins f the design. A mre cmplete input space IS can als be btained by simulating the RS with a mre cmprehensive set f system- System Space i i+1 lck i lck i +1 S System ehaviral Mdel i i+1 lck i lck i +1 lectrical (C ircuit) Implementatin Primary Decmpse C nstrained lck S pace lck i AMS Circuit ehaviral ehaviral i Output lck i f - {.}?? = g i - {.} lck i Figure : lck-level behaviral checking between behaviral and electrical implementatins. Primary Output Figure 3: s t a circuit blck are cnstrained by the structure f the design. A reference system behaviral mdel (RS) is used t derive blck-level inputs. 56

3 level input stimuli and recrd the crrespnding behaviral inputs appearing at the input t each circuit blck. In practice, these system-level inputs can be btained by using design knwledge r by intrducing pseud-randm variatins t typical inputs. In this case, a higher cverage in verificatin will be resulted as a larger set f input excitatins are included in the verificatin prcess. III. SIGNAL DOMAINS & MAPPING FUNCTIONS As described in the previus sectin, we use system-level behaviral simulatins t generate a behaviral input set (IS) fr each circuit blck. Then fr each behaviral input I (in the IS) and the crrespnding behaviral utput f the blck, O,, the electrical implementatin r a SPIC-level transistr mdel f the blck is checked against the behaviral blck mdel fr equivalence. As illustrated in Fig. 4, such equivalence check is perfrmed acrss tw different signal dmains: behaviral (Ω ) vs. electrical (Ω ). In this sectin we highlight the key differences between the behaviral and the electrical dmains. The mapping functins used t transfrm the signals frm ne dmain t anther are als explained. A. ehaviral vs. lectrical Dmains The behaviral dmain (Ω ), characterized by the behaviral signal space, is essentially an abstract frm f the actual electrical dmain (Ω ). The signals in the behaviral dmain are abstract versins f the electrical signals and are generated by remving sme details frm the electrical signals. Fr example, let us cnsider tw mdels, an electrical mdel and a behaviral mdel. We apply a sinusidal input wavefrm t bth the mdels. Further, let us als assume that the behaviral mdel utput nly depends n the frequency f the input signal and the time instants at which the wavefrm pulse crsses the rigin. Then in principle, any signal with any arbitrary wavefrm shape but identical frequency and zer crssing time shuld prduce the same behaviral utput as the sinusidal wavefrm. Hwever, the same shall nt be true fr the electrical utput. This difference between the behaviral utput and the electrical utput cmes frm the fact that while the electrical input is a sinusidal wavefrm the actual behaviral input signal simply abstracts away the wavefrm shape infrmatin while nly preserving the frequency and zer-crssing times. T further illustrate the differences between electrical and behaviral dmains, especially in relatin t analg/mixed signal systems, let us cnsider a behaviral mdel fr a vltage cntrlled scillatr (VCO) as shwn in Figure 5. The behaviral utput f the mdule nly depends n the time instants at which the phase changes, the lw and high utput vltage levels. N infrmatin abut the precise wavefrm shape is present in the behaviral signal, whereas the same infrmatin cntent is present in the electrical dmain utput f a VCO.. Signal-Dmain Mapping Functins T link the tw dmains tgether we define tw mappings, f - { }: Ω Ω and g - { }: Ω Ω. With the inherent abstractin in behaviral mdeling, f - is ne-t-many mapping Figure 5: Part f behaviral mdel fr a VCO. mdule vc (in,ut).. analg begin freq = (V(in)-Vmin)α+F min // Simple Linear mdel fr VCO frequency //phase calculatin phase = M_PIidtmd(freq,0.0,1.0,-0.5) //generatin f utput vltage V(ut) <+ transistin(n? Vl: Vhi, td,tr,tf) end and maps a behaviral signal wavefrm t a set f electrical realizatins; g - is many-t-ne mapping and abstracts away nnbehaviral details frm an electrical wavefrm. Using f - we map a single (behaviral) input I t the behaviral mdel t a set f electrical inputs, S I = {I 1, I } = f - {I }, which are used t exercise the SPIC mdel in Ω (Fig. 4). The resulting multiple electrical utputs S O = {O 1, O } are mapped back t Ω via S O ={g - {O i }} t cmpare against the reference utput f the behaviral mdel O. Nte that fr a single behaviral input I,, I = f - {I } defines the electrical input space ver which the electrical implementatin needs t be checked fr equivalence. On the ther hand, since the reference behaviral utput, O, is behaviral, the utputs f the electrical implementatins are mapped back t the Ω via g - fr cmparisn. T illustrate hw the tw mapping functins are generated in practice, let us cnsider part f the behaviral mdel f a phase lcked lp cmprising f the charge pump and a mdule cntaining the filter and a VCO (Fig. 6). The behaviral utput f the charge pump may cntain nly idealized current pulses which act as behaviral inputs fr the filter & VCO mdule. Nte that these utput signals are in the behaviral dmain and nly have essential mdeled behaviral characteristics f the utput signal. f - basically maps the behaviral utput signal t the electrical dmain by adding the un-mdeled electrical details, say in this case, the rise time and the fall time f the utput current pulse. Nte that fr each behaviral input signal multiple electrical signals are prduced. Similarly, the reference behaviral utput signal f the filter & VCO mdule, O, nly cntains the essential behaviral characteristics that are mdeled in the utput functin f the VCO, which fr a mdel shwn in Figure 5 shall be the level crssing time pints. T cmpare with this reference O, g - basically maps the detailed electrical utput wavefrms prduced by the SPIC-level blck mdel t the behaviral System Stimuli System ehaviral Simulatin I Fr each ehaviral beh. input & utput pair Space (IS) fr lck i f - {.} One-t-Many I ={I 1, I } ehaviral Mdel i S P IC -level Transistr Mdel i O Cmpare?? O ={O 1, O } Many-t-One g - {.} O ={O 1, O } ehaviral Dmain lectrical Dmain Figure 4: Signal mappings between the behaviral and electrical dmains. 57

4 Charge Pump (Driver eh. Mdel) f - {.}: g - {.} : Filter + VCO Add rise/fall time t utput current xtract Level Crssing pulses lck under Check (UC) Timestamps Figure 6: Illustratin fr generatin f mapping functin. dmain. In the present example, the electrical utputs f the crrespnding SPIC-level VCO net-list shall be simply mapped back t the behaviral dmain by extracting the level-crssing time stamps. In general, g - is many-t-ne since multiple electrical signals can have the same extracted behaviral features. In principle, mapping functins f - and g - are mdule dependent. In particularly, as illustrated in Fig. 6, f - fr the blck under check shall be cnstructed t reflect the behaviral abstractin embedded in the utput functin f the preceding (driver) behaviral mdel. On the ther hand, g - effectively extracts frm an electrical utput the behaviral characteristics that are specified in the utput f the behaviral mdel under check. IV. OPTIMIZATION ASD QUIVALNC CHCKING As described in previus sectins ur verificatin methdlgy invlves generatin f system level behaviral stimuli, mapping each behaviral input stimulus t a set f detailed electrical inputs which are then used t simulate the SPIC level transistr net-list. At the utput, we map the set f electrical signals prduced t the behaviral dmain, which are then cmpared with the crrespnding behaviral utputs frm the RS t verify equivalence between the tw implementatins. In this sectin we frmulate the abve cmparisn as a maximizatin prblem. The ptimizatin prblem may be slved using any simulatin based ptimizer, i.e. any available ptimizatin slver which des nt necessarily require a clsed frm expressin fr calculating the bjective functin. In this paper we used DONLP [10][11], a sequential quadratic prgramming (SQP) based ptimizatin engine fr the same. DONLP was interfaced with CADNC Spectre t allw cmputatin f the bjective functin using actual spice level simulatins. Fr a given behaviral input I, the behaviral mdel prduces O at the utput (Figure 4). T verify whether r nt this inpututput crrespndence is retained in the electrical implementatin, we ask the fllwing questin: fr all electrical input signals that have the behaviral characteristics specified by I, will the crrespnding electrical utputs maintain the same behaviral characteristics specified by O? Fr every circuit blck, we perfrm the abve equivalence check fr each behaviral input in its IS. An electrical implementatin is deemed as equivalent t the system behaviral mdel if and nly if all such checks are passed. We frmulate the abve as a maximizatin prblem. We parameterize the nn-behaviral electrical features nt mdeled in a behaviral input, such as finite rise/fall times and signal shapes, by intrducing additinal electrical feature parameters. We dente these electrical feature parameters as p. Such parameterizatin mathematically cnstructs the mapping functin f -. The mapped electrical input set S I = {I 1, I } = f - (I, ) defines a cnstrained electrical input excitatin space ver which the SPIC net-list needs t be cmpared with the behaviral mdel. We frmulate this task frmally as a maximizatin ptimizatin prblem in S I and seek t btain the maximum deviatin ε max frm the reference behaviral utput O : max ε = h O ( p ), O (1) p err ( ) subject t: p p p () I ( ) QSP I ) ) g O = f I, p ) (3) ( ) ( )) O = (4) O = (5) quatin (1) defines the bjective functin, which is an errr functin h specifying the derivatin between the mapped err electrical utput and the reference behaviral utput O. Fr instance, if O and O ( p ) are represented as vectrs f sampled signal values, L vectr nrm can be used t define the errr functin: herr = O ( p ) O In practice, the definitin f h is mdel dependent and is dependent n the functinality f err the blck. Fr example, fr the VCO behavir mdel shwn in Figure 5, it may be the L 1 vectr nrm f level crssing time stamps, while fr a charge pump it may be L vectr nrm f the vectr measuring the charge injected int the system at different time pints. quatin () defines the bund n the electrical input parameters. quatin (3) maps I t an electrical input signal by adding electrical features specified by p. QSP () in (4) maps an electrical input applied t the SPIC-level mdel t the crrespnding electrical utput; this mapping is realized by running circuit (SPIC) simulatin. Finally, (5) maps the electrical utput t the behaviral dmain by using g -. The prpsed ptimizatin-based equivalence-check flw is shwn in Figure 7, where an ptimizer (DONLP) is emplyed t search fr the maximum deviatin ε max. If ε is less than a userdefined tlerance, the equivalence check is deemed as passed; max therwise, a failure is reprted. At the inner lp f the ehaviral-level System Simulatin xtract lck-level ehaviral /Output signals Map t Generate lectrical Space SPIC-level Simulatin Map lectrical Outputs back t ehaviral Dmain Get the deviatin (errr) frm the reference behaviral utput Optimizer interfaced with s imulatr N Largest rrr Reached in the lectrical Space? Is the Largest rrr > Tlerance? N Fail Succeed Figure 7: Optimizatin based equivalence checking flw. 58

5 ptimizatin, the circuit simulatr, CADNC Spectre, is interfaced t prvide the mapping in (4). T make the abve methdlgy mre rbust and cnservative in nature, we als implemented a slightly mdified frm f the abve flw. The mdificatin was dne t allw the prpsed verificatin flw t merge cnveniently with the existing cmmercial circuit simulatin sftware like CADNC Spectre and HSPIC. Althugh the behaviral utput signal at any pint shuld/des nt depend n the nn-mdeled electrical details in the behaviral input signal, practical circuit simulatrs d nt distinguish between the behaviral signals and the electrical signals. The circuit simulatr treats the behaviral input and utput in the same way as they treat the electrical signals. This anmaly in simulatrs may smetimes lead t unexpected results. T avid any such ccurrences and enable a cnservative check we mdify the abve flw shwn in Figure 7 slightly. The mdified flw is shwn in Figure 8. As shwn in figure 8, at inner lp f ptimizatin, in additin t simulating spice level net-list we als simulate the behaviral mdel fr the blck under verificatin with the same electrical dmain input signal. The electrical utputs are then mapped back t the behaviral dmain and maximum deviatin between the electrical and behaviral dmain utputs are cmputed in the same manner as befre. V. XPRIMNTAL RSULTS The prpsed methdlgy was implemented using C language and was applied fr equivalence checking between verilg AMS based behaviral mdel f a phase lcked lp (PLL) and its electrical implementatin (CADNC Spectre net-list). The blck diagram f the PLL used is shwn in figure 9. T generate the behaviral input space (IS) fr each blck in the behaviral mdel, the reference behaviral mdel was simulated using a typical system-level simulatin setup used t calculate the lck-in time f a PLL. The reference input signal was a pulse f 10.9MHz and the vltage signal Vcntrl was used t mdify the divider rati f the PLL frm 150 t 100 at a time instant f 3μs. The verificatin f the entire system was perfrmed in a hierarchical manner by dividing the system int three mdules, lp filter and vltage cntrlled scillatr (VCO), charge pump and phase ehaviral-level System Simulatin xtract lck-level ehaviral /Output signals Map t Generate lectrical Space SPIC-level Simulatin & lck level ehaviral Simulatin Map lectrical Outputs back t ehaviral Dmain Get the deviatin (errr) frm the reference behaviral utput Optimizer interfaced with s imulatr N Largest rrr Reached in the lectrical Space? Is the Largest rrr > Tlerance? N Fail Succeed Figure 8: Mdified ptimizatin based equivalence checking flw. Vref Frequency Divider Vcntrl Figure 9: lck diagram f the phase lcked lp (PLL). detectr. A. Lp Filter and Vltage Cntrlled Oscillatr The behaviral input t the blck cmpsed f the lp filter and the VCO cnsists f idealized current pulses frm the charge pump. The electrical implementatin f the blck is shwn in Figure 10. Figure 11 depicts the spectre simulatin results f the current pulses generated by the charge pump frm 0.3μs t 0.66μs. The results depict the presence f spikes in the utput current whenever the current wavefrm amplitude changes suddenly. T map the idealized behaviral current pulse wavefrms int electrical equivalent signals fur electrical feature parameters, trise (t r ), tfall (t f ), peak_ps (p_ps) and peak_neg (p_neg) were defined. trise (t r ) and tfall (t f ) represent the rise time and fall time f the current wavefrms, and peak_ps (p_ps) and peak_neg (p_neg) refer t the peak amplitudes f the current spikes generated in the utput wavefrm. The behaviral utput f the blck, i.e. the VCO behaviral utput, is dependent nly n the level crssing time instants (Figure 5). Thus, the electrical utput signals are mapped back t behaviral dmain by simply extracting the level crssing time instants. ased n the abve, the ptimizatin prblem was frmulated as under: max ε = t t (6) tr, tf, p _ neg, p _ ps subject t: 1 t r (7) 1 t f (8) 3 p _ neg 0μA (9) 3 p _ ps 0μA (10) where t and t refer t the level crssing time instants btained frm the electrical and behaviral utputs respectively. The abve ptimizatin prblem was slved fr three different behaviral mdels f the VCO. The utput frequency versus cntrl vltage plts fr the three different VCO mdels are shwn in Figure 1. Mdel A clsely resembles the VCO characteristics acrss the entire cntrl vltage range whereas mdels & C are nly linear apprximatins t the VCO utput R C1 V crl C Lp Filter Phase Detectr Charge Pump Vb1 Vb1 Vb1 Vb1 Vb1 Lp Filter Vdd 1 V crl V crl V crl V crl VCO VCO Figure 10: lectrical implementatin fr lp filter and VCO. Vut Vut 59

6 Figure 11: Spectre simulatin: charge pump utput current. frequency characteristics. Table 1 belw shws the maximum errr btained fr each behaviral mdel, values f the electrical parameters added at that instant, equivalence decisin f the methdlgy, and the ttal runtime required fr ptimizatin. As expected, the maximum errr is least fr mdel A and is the nly mdel fr which equivalence test is successful. Table 1: quivalence check fr VCO and filter blck Mdel A Mdel Mdel C Maximum rrr 1.545e e e+03 Rise Time 1.999ns 1.999ns 50ns Fall Time 1.999ns 1.999ns 50ns Peak_ps 3μA 0μA 3μA Peak_neg 0μA 3μA 0μA quivalence N N Runtime (sec) Charge Pump The behaviral input t the charge pump (CP) cnsists f tw digital like vltage pulses up and dwn cntrlling the utput current. The electrical implementatin f the charge pump is shwn in Figure 13. T map the behaviral input signals int equivalent electrical wavefrms, tw electrical feature parameters, trise (t r ), and tfall (t f ) were defined. The electrical utput f the charge pump cnsists f the shrt duratin current pulses (Figure 11). Since the ttal charge injected int the system is the mst imprtant parameter fr the charge pump, the utput current was integrated t calculate the net charge intrduced by the charge pump. The ttal charges intrduced by the behaviral and electrical implementatins at different instants f time were then cmpared t calculate the errr functin. ased n the abve, the ptimizatin prblem was frmulated as under: maxε = ( q q )1e6 (11) tr, tf subject t: 1 t r (1) 1 t f (13) Figure 1: Frequency versus cntrl vltage fr the three VCO mdels. where q and q are vectrs cnsisting f the ttal charge injected int the system by the electrical and behaviral mdels at different time instants. T verify the methdlgy fr charge pumps, tw different behaviral mdels were used, with ne clser t the electrical implementatin than the ther (Figure 14). ehaviral mdel A tk int accunt the current mismatch between the up and dwn current while mdel simply neglected this difference and mdeled bth the current surces identically. The maximum deviatin between the electrical and behaviral mdels was calculated by slving the ptimizatin prblem in (11). Table belw shws the maximum deviatin between the electrical and behaviral signals and the equivalence decisin f the prpsed methdlgy. As expected, the maximum deviatin in mdel A is less than the maximum deviatin in mdel and equivalence test is successful nly fr mdel A. Table : quivalence Results fr the Charge Pump Mdel Maximum rrr Rise Time Fall Time Match Run Time(sec) A e+01 50ns ns e+01 50ns 50ns N 30.4 C. Phase Detectr The behaviral input t the phase detectr (PD) cnsists f input reference vltage and the utput vltage wavefrm (behaviral) f the frequency divider. The behaviral input vltage was mapped t electrical dmain by adding the rise and fall time parameters t the input behaviral wavefrms. Further, similar t the VCO utput wavefrms, the electrical dmain vltage wavefrms were mapped back t the behaviral dmain Vdd Charge Pump Figure 13: lectrical implementatin f charge pump. 60

7 Iup =.μa Iup = μa Idwn =.11μA Idwn = μa by simply extracting the time instants at which the utput vltage crssed the Vdd/ value. The ptimizatin prblem fr the phase detectr was frmulated as under: maxε = ( t t )1e6 + ( t t )1e6 where t u,, tr, tf t up, Mdel A Mdel Figure 14: Charge pump mdels. up up, dn dn, (13) subject t: 1 t r (14) 1 t f (15),t dn, and t dn, refer t the Vdd/ crssing time instants btained frm the electrical and behaviral utput fr the up and dwn vltage respectively. The abve ptimizatin prblem was slved fr the phase detectr and the maximum deviatin f e+01 was achieved fr trise=tfall=50ns. Since, the deviatin was less than the maximum threshld, the mdels were deemed equivalent. D. Verificatin f the prpsed methdlgy T verify that the prpsed methdlgy crrectly identified the equivalence between the behaviral mdels and their electrical implementatins, system level prperties f the PLL such as lcking time were calculated frm bth the behaviral and the electrical implementatins. Out f the three mdels available fr the filter and VCO blck (Table 1), mdel A was used t calculate the abve prperties as mdel A was deemed as equivalent by the verificatin methdlgy. Similarly, mdel A f the charge pump blck (Table ) was used in the abve calculatins. Figure 15 shws the frequency f the utput signal, Vut, as btained frm the reference behaviral mdel and when the individual behaviral mdels were replaced with their electrical cunterparts. A lcking time f 1.03μs was achieved under all the cases. The difference in the wavefrms at pwer n represents the fact that the behaviral mdels d nt capture the initial PLL pwer n prcess well. After pwer n the behaviral mdel and transistr level implementatin are equivalent t each ther. VI. ACKNOWLDGMNTS This wrk was supprted in part by the Semicnductr Research Crpratin and Texas Analg Center f xcellence. VII. CONCLUSION In this paper we presented an ptimizatin based, hierarchical behaviral mdel equivalence checking methdlgy fr large Analg/Mixed Signal designs such as PLLs, ADCs and I/O s. The verificatin methdlgy is nt necessarily frmal, but yet systematic and practical. It recgnizes that the inputs t any specific circuit blck in a system are cnstrained by the structure Figure 15: Output frequency f the PLL frm behaviral and electrical simulatins. f the entire design, and hence, verificatin is dne nly n a selected set f inputs rather than the universe f all pssible arbitrary inputs. The prpsed methdlgy is applied fr verificatin f a Phase Lcked Lp as a test case. RFRNCS [1] M. H. Zaki et al, Frmal verificatin f analg and mixed signal designs: a survey, Micrelectrnics Jurnal, 39(008) [] S.Steinhrst, L. Hedrich, Advanced methds fr equivalence checking f analg circuits with strng nnlinearities, Frmal Methds in System Design, Springerlink, 009. [3] S. Tiwary, A. Gupta, J. Phillips, C. Pinell, R. Zlatanvici, First Steps Twards SAT-based Frmal Analg Verificatin, I/ACM ICCAD, Nv [4] A.alivada, Y.V. Hskte, J.A.Abraham, Verificatin f transient respnse f linear analg circuits, I VLSI Test Sympsium, 1995, pp [5] Hedrich, L. and. arke, A frmal apprach t nnlinear analg circuit verificatin, Internatinal Cnference n Cmputer-Aided Design, 1995, pp [6] Hedrich, L. and. arke, A frmal apprach t verificatin f linear analg circuits with parameter tlerances Design Autmatin and Test in urpe, 1998, pp [7] T.R.Dastidar, P.P.Chakrabarti, A verificatin system fr transient respnse f analg circuits, ACM Trans. Design Autm. lectrn. Syst., vl. 1, n 3, pp. 1-39, 007. [8] T.Dang, A.Dnze, O.Maler, Verificatin f analg and mixed-signal circuits using hybrid system techniques, Frmal Methds in Cmpuer- Aided Design, Lecture Ntes in Cmputer Science, vl. 331, Springer, erlin, 004, pp [9] S.Gupta,.H.Krgh, R.A. Rutenbar, Twards Frmal Verificatin f Analg Designs, I/ACM Internatinal Cnference n Cmputer Aided Design, 004, pp [10] P. Spellucci, An sqp methd fr general nnlinear prgrams using nly equality cnstrained sub-prblems, Mathematical Prgramming, vl. 8, pp , [11] P. Spellucci, A new technique fr incnsistent prblems in the SQP methd, Mathematical Methds f Operatin Research, vl. 47, pp ,