Making Non-Volatile Nanomagnet Logic Non-Volatile
|
|
- Austin Chambers
- 5 years ago
- Views:
Transcription
1 Slides by Lubaba Making Non-Volatile Nanomagnet Logic Non-Volatile Aaron Dingler, Steve Kurtz Michael Niemier, Xiaobo Sharon Hu, Joseph Nahas
2 PAPER OVERVIEW Issue: - Nanomagnet Logic: greatest feature non-volatility (even at gate level). - Externally supplied switching energy is needed to re-evaluate a magnet ensemble, which could be done by multiphase clocking inherently pipelined manner for high throughput. However, this could arise bit conflicts (agitate random walk )make Nanomagnet Logic Volatile. Objective: To make Nanomagnet Logic Non-Volatile. Approach and Comparative Study: IMPROVING NON-VOLATILITY: Eliminate Random Walk: ( aspect ratio): drawback -> external energy - Selective Latching: Selected device to hold the data, needed to be non-volatile - Use surrounding devices with higher permeability [µ =B/H] - Use Biaxial anisotropic (magnetic)device [K u cos2(θ) + ¼ K 1 sin2(2θ)] 2
3 PAPER OVERVIEW Issue: - Nanomagnet Logic: greatest feature non-volatility (even at gate level). - Externally supplied switching energy is needed to re-evaluate a magnet ensemble, which could be done by multiphase clocking inherently pipelined manner for high throughput. However, this could arise bit conflicts (agitate random walk )make Nanomagnet Logic Volatile. ->system building Objective: To make Nanomagnet Logic Non-Volatile. Approach and Comparative Study: IMPROVING NON-VOLATILITY: Eliminate Random Walk:( aspect ratio): quantum study -> design modification - Selective Latching: system study -> design optimization - higher permeability: knowledge of physics-> device selection - Use Biaxial anisotropic (magnetic)device : quantum study -> device selection 2
4 OUTLINE Background Root cause Approach Comparative Simulation 4
5 NANOMAGNET LOGIC & FIELD-DRIVEN CLOCKING Nanomagnet library: programmable majority gates, fanout, AND/OR, NAND/NOR logic, Register, Wire->Anti-Ferromagnetically coupled line - Single domain magnets can represent and store binary data Field-driven clocking: Externally switching energy is needed to reevaluate a magnet ensemble Clk N Clk N+1 t (a) AF-lines move information; (b) an AF-line has a new input, and an external clocking field is used to facilitate re-evaluation of the line; (c) as the field is removed, devices relax along their easy axes; 5
6 OUTLINE Background Root cause - Origins of volatility Approach Comparative Simulation 6
7 ORIGINS OF ENSEMBLE VOLATILITY Architectural-level bit conflicts can occur in defect free NML: ->pipelining (eg:3-phase clock) Clk phase2 Clk phase2 odd number of magnets per clock group 40 of, 40x60x20 nm3 supermalloy magnets spaced 8 nm apart. 5mT-> B required an even number of magnets per clock group Random walk <- field coupling and thermal noise alone could be sufficient to initiate a state destroying case 7
8 OUTLINE Background Root cause - Origins of volatility Approach - Eliminate Random Walk - Selective Latching - Enhanced permeability dielectrics - Biaxial anisotropy Comparative Simulation: OOMMF (Object Oriented MicroMagnetic Framework) 8
9 Eliminate Random Walk By increasing magnet s aspect ratio: Quantifying ensemble stability the probability per unit time of reversal over the EB is 1/τ, where τ a exp(eb/kt) 3-magnet Quantifying ensembles 40x60x20 40x80x20 Required fields will increase from 5 mt (40x60x20 nm 3 ) to 50 mt (40x80x20 nm 3 )-> (i.e., B ~ µi/l : Ohmic losses->i 2 R increase by a factor of 100) 9
10 OPTIMIZING EXTERNAL FIELD Selective Latching: EG. A line of 40x60x20 nm 3 devices where select devices are replaced by higher aspect ratio, 40x80x20 nm 3 devices. Ohmic loss could be reduced such that 1 out three clk will need 10 time current. +1 Enhanced permeability dielectrics: Use surrounding devices with higher permeability [B=µH; µ ; H = I /L ] Eg. relative permeabilities of ~4.5X(superparamagnetic CoFe) improve clock energy by ~20X 10
11 OPTIMIZING EXTERNAL FIELD Biaxial anisotropy: additional energy -90 o 0 o, 0 o 90 o, 2 maximas [K u cos2(θ) + ¼K 1 sin2(2θ)] Aspect Ratio-apart K1 required B nm3-nm kj/m3 mt 60x90x x90x x90x
12 PAPER OVERVIEW Issue: - Nanomagnet Logic: greatest feature non-volatility (even at gate level). - Externally supplied switching energy is needed to re-evaluate a magnet ensemble, which could be done by multiphase clocking inherently pipelined manner for high throughput. However, this could arise bit conflicts (agitate random walk )make Nanomagnet Logic Volatile. Objective: To make Nanomagnet Logic Non-Volatile. Approach and Comparative Study: IMPROVING NON-VOLATILITY: Eliminate Random Walk: ( aspect ratio): drawback -> external energy - Selective Latching: Selected device to hold the data, needed to be non-volatile - Use surrounding devices with higher permeability [µ =B/H] - Use Biaxial anisotropic (magnetic)device [K u cos2(θ) + ¼ K 1 sin2(2θ)] 2
13 Making Non-Volatile Nanomagnet Logic Non-Volatile 13
Systematic Design of Nanomagnet Logic Circuits
Systematic Design of Nanomagnet Logic Circuits Indranil Palit, X. Sharon Hu, Joseph Nahas, and Michael Niemier Department of Computer Science and Engineering, University of Notre Dame Notre Dame, IN 46556,
More informationDesign of 3D Nanomagnetic Logic Circuits: a Full-Adder Case Study
Design of 3D Nanomagnetic Logic Circuits: a Full-Adder Case Study Robert Perricone, X. Sharon Hu, Joseph Nahas, and Michael Niemier Department of Computer Science and Engineering, University of Notre Dame
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationBridging the Gap between Nanomagnetic Devices and Circuits
Bridging the Gap between Nanomagnetic Devices and Circuits Michael Niemier 1,X.SharonHu 1, Aaron Dingler 1,M.TanvirAlam 2, G. Bernstein 2, and W. Porod 2 (1) Department of Computer Science and Engineering,
More informationFAULT MODELS AND YIELD ANALYSIS FOR QCA-BASED PLAS 1
FAULT MODELS AND YIELD ANALYSIS FOR QCA-BASED PLAS Michael Crocker, X. Sharon Hu, and Michael Niemier Department of Computer Science and Engineering University of Notre Dame Notre Dame, IN 46556, USA Email:
More informationNanomagnet Logic (NML)
Nanomagnet Logic (NML) Wolfgang Porod 1(&), Gary H. Bernstein 1, György Csaba 1, Sharon X. Hu 2, Joseph Nahas 2, Michael T. Niemier 2, and Alexei Orlov 1 1 Department of Electrical Engineering, University
More informationSequential Logic (3.1 and is a long difficult section you really should read!)
EECS 270, Fall 2014, Lecture 6 Page 1 of 8 Sequential Logic (3.1 and 3.2. 3.2 is a long difficult section you really should read!) One thing we have carefully avoided so far is feedback all of our signals
More informationA NML-HDL Snake Clock Based QCA Architecture
International Journal of Scientific and Research Publications, Volume 4, Issue 2, February 2014 1 A NML-HDL Snake Clock Based QCA Architecture 1 Mr. M. B. Kachare, 2 Dr. P. H. Zope 1 ME I st (Dig. Electronics),
More information9. Spin Torque Majority Gate
eyond MOS computing 9. Spin Torque Majority Gate Dmitri Nikonov Thanks to George ourianoff Dmitri.e.nikonov@intel.com 1 Outline Spin majority gate with in-pane magnetization Spin majority gate with perpendicular
More informationEEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top
More informationBoolean Logic Continued Prof. James L. Frankel Harvard University
Boolean Logic Continued Prof. James L. Frankel Harvard University Version of 10:18 PM 5-Sep-2017 Copyright 2017, 2016 James L. Frankel. All rights reserved. D Latch D R S Clk D Clk R S X 0 ~S 0 = R 0 ~R
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationDesigning Cellular Automata Structures using Quantum-dot Cellular Automata
Designing Cellular Automata Structures using Quantum-dot Cellular Automata Mayur Bubna, Subhra Mazumdar, Sudip Roy and Rajib Mall Department of Computer Sc. & Engineering Indian Institute of Technology,
More informationMemory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1
Memory Elements I CS31 Pascal Van Hentenryck CS031 Lecture 6 Page 1 Memory Elements (I) Combinational devices are good for computing Boolean functions pocket calculator Computers also need to remember
More informationDirections for simulation of beyond-cmos devices. Dmitri Nikonov, George Bourianoff, Mark Stettler
Directions for simulation of beyond-cmos devices Dmitri Nikonov, George Bourianoff, Mark Stettler Outline Challenges and responses in nanoelectronic simulation Limits for electronic devices and motivation
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour
More informationIMPLEMENTATION OF PROGRAMMABLE LOGIC DEVICES IN QUANTUM CELLULAR AUTOMATA TECHNOLOGY
IMPLEMENTATION OF PROGRAMMABLE LOGIC DEVICES IN QUANTUM CELLULAR AUTOMATA TECHNOLOGY Dr.E.N.Ganesh Professor ECE Department REC Chennai, INDIA Email : enganesh50@yahoo.co.in Abstract Quantum cellular automata
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Following the slides of Dr. Ahmed H. Madian Lecture 10 محرم 1439 ه Winter
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design
More informationSequential Logic Worksheet
Sequential Logic Worksheet Concept Inventory: Notes: D-latch & the Dynamic Discipline D-register Timing constraints for sequential circuits Set-up and hold times for sequential circuits 6.004 Worksheet
More informationIntroduction to Quantum Computing
Introduction to Quantum Computing The lecture notes were prepared according to Peter Shor s papers Quantum Computing and Polynomial-Time Algorithms for Prime Factorization and Discrete Logarithms on a
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationNovel Devices and Circuits for Computing
Novel Devices and Circuits for Computing UCSB 594BB Winter 2013 Lecture 4: Resistive switching: Logic Class Outline Material Implication logic Stochastic computing Reconfigurable logic Material Implication
More informationEECS 579: Logic and Fault Simulation. Simulation
EECS 579: Logic and Fault Simulation Simulation: Use of computer software models to verify correctness Fault Simulation: Use of simulation for fault analysis and ATPG Circuit description Input data for
More informationShift Register Counters
Shift Register Counters Shift register counter: a shift register with the serial output connected back to the serial input. They are classified as counters because they give a specified sequence of states.
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Original slides from Gregory Byrd, North Carolina State University Modified by C. Wilcox, M. Strout, Y. Malaiya Colorado State University Computing Layers Problems Algorithms
More informationMagnetic QCA systems
Microelectronics Journal 36 (2005) 619 624 www.elsevier.com/locate/mejo Magnetic QCA systems G.H. Bernstein a, *, A. Imre a, V. Metlushko c, A. Orlov a, L. Zhou a,l.ji a, G. Csaba b, W. Porod a a Center
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationA design methodology and device/circuit/ architecture compatible simulation framework for low-power magnetic quantum cellular automata systems
Purdue University Purdue e-pubs Department of Electrical and Computer Engineering Faculty Publications Department of Electrical and Computer Engineering January 2009 A design methodology and device/circuit/
More informationAvailable online at ScienceDirect. Procedia Computer Science 70 (2015 ) Bengal , India
Available online at www.sciencedirect.com ScienceDirect Procedia Computer Science 70 (2015 ) 153 159 4 th International Conference on Eco-friendly Computing and Communication Systems (ICECCS) Design of
More informationvidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A
More informationDELAY EFFICIENT BINARY ADDERS IN QCA K. Ayyanna 1, Syed Younus Basha 2, P. Vasanthi 3, A. Sreenivasulu 4
DELAY EFFICIENT BINARY ADDERS IN QCA K. Ayyanna 1, Syed Younus Basha 2, P. Vasanthi 3, A. Sreenivasulu 4 1 Assistant Professor, Department of ECE, Brindavan Institute of Technology & Science, A.P, India
More informationSequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory
More informationDifferent encodings generate different circuits
FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,
More informationCSE241 VLSI Digital Circuits Winter Lecture 07: Timing II
CSE241 VLSI Digital Circuits Winter 2003 Lecture 07: Timing II CSE241 L3 ASICs.1 Delay Calculation Cell Fall Cap\Tr 0.05 0.2 0.5 0.01 0.02 0.16 0.30 0.5 2.0 0.04 0.32 0.178 0.08 0.64 0.60 1.20 0.1ns 0.147ns
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC
More informationLecture 17: Designing Sequential Systems Using Flip Flops
EE210: Switching Systems Lecture 17: Designing Sequential Systems Using Flip Flops Prof. YingLi Tian April 11, 2019 Department of Electrical Engineering The City College of New York The City University
More informationSequential Logic. Handouts: Lecture Slides Spring /27/01. L06 Sequential Logic 1
Sequential Logic Handouts: Lecture Slides 6.4 - Spring 2 2/27/ L6 Sequential Logic Roadmap so far Fets & voltages Logic gates Combinational logic circuits Sequential Logic Voltage-based encoding V OL,
More informationSerial Parallel Multiplier Design in Quantum-dot Cellular Automata
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata Heumpil Cho and Earl E. Swartzlander, Jr. Application Specific Processor Group Department of Electrical and Computer Engineering The University
More informationLecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: EEE QUESTION BANK SUBJECT NAME: DIGITAL LOGIC CIRCUITS SUBJECT CODE: EE55 SEMESTER IV UNIT : Design of Synchronous Sequential Circuits PART
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More informationRoger L. Tokheim. Chapter 8 Counters Glencoe/McGraw-Hill
Digital Electronics Principles & Applications Sixth Edition Roger L. Tokheim Chapter 8 Counters 2003 Glencoe/McGraw-Hill INTRODUCTION Overview of Counters Characteristics of Counters Ripple Up Counter
More informationCh 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1
Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More informationNext, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on May 1, 2003 by Dejan Markovic (dejan@eecs.berkeley.edu) Prof. Jan Rabaey EECS
More informationClock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.
1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationFinite State Machine (FSM)
Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State CLK Current State
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationBINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCA
BINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCA Neha Guleria Department of Electronics and Communication Uttarakhand Technical University Dehradun, India Abstract Quantum dot Cellular Automata (QCA)
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More information2. Accelerated Computations
2. Accelerated Computations 2.1. Bent Function Enumeration by a Circular Pipeline Implemented on an FPGA Stuart W. Schneider Jon T. Butler 2.1.1. Background A naive approach to encoding a plaintext message
More informationAnalog to Digital Conversion
Analog to Digital Conversion ATmega Block Diagram Analog to Digital Converter Sample and Hold SA Converter Internal Bandgap eference 2 tj Analog to Digital Conversion Most of the real world is analog temperature,
More informationSpin Torque and Magnetic Tunnel Junctions
Spin Torque and Magnetic Tunnel Junctions Ed Myers, Frank Albert, Ilya Krivorotov, Sergey Kiselev, Nathan Emley, Patrick Braganca, Greg Fuchs, Andrei Garcia, Ozhan Ozatay, Eric Ryan, Jack Sankey, John
More informationVidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B
. (a). (b). (c) S.E. Sem. III [EXTC] igital Electronics Prelim Question Paper Solution ABC ABC ABC ABC ABC ABC ABC ABC = B LHS = ABC ABC ABC ABC ABC ABC ABC ABC But ( ) = = ABC( ) ABC( ) ABC( ) ABC( )
More informationChapter 4. Sequential Logic Circuits
Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of
More informationVLSI Signal Processing
VLSI Signal Processing Lecture 1 Pipelining & Retiming ADSP Lecture1 - Pipelining & Retiming (cwliu@twins.ee.nctu.edu.tw) 1-1 Introduction DSP System Real time requirement Data driven synchronized by data
More informationLecture 22 Chapters 3 Logic Circuits Part 1
Lecture 22 Chapters 3 Logic Circuits Part 1 LC-3 Data Path Revisited How are the components Seen here implemented? 5-2 Computing Layers Problems Algorithms Language Instruction Set Architecture Microarchitecture
More informationEE141. Lecture 28 Multipliers. Lecture #20. Project Phase 2 Posted. Sign up for one of three project goals today
EE141-pring 2008 igital Integrated ircuits Lecture 28 Multipliers 1 Announcements Project Phase 2 Posted ign up for one of three project goals today Graded Phase 1 and Midterm 2 will be returned next Fr
More informationCPS 104 Computer Organization and Programming Lecture 11: Gates, Buses, Latches. Robert Wagner
CPS 4 Computer Organization and Programming Lecture : Gates, Buses, Latches. Robert Wagner CPS4 GBL. RW Fall 2 Overview of Today s Lecture: The MIPS ALU Shifter The Tristate driver Bus Interconnections
More information5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L5: Sequential Logic, Slide #1 Something We Can t Build (Yet) What if you were
More informationSpiral 2-1. Datapath Components: Counters Adders Design Example: Crosswalk Controller
2-. piral 2- Datapath Components: Counters s Design Example: Crosswalk Controller 2-.2 piral Content Mapping piral Theory Combinational Design equential Design ystem Level Design Implementation and Tools
More informationSTUDY AND IMPLEMENTATION OF MUX BASED FPGA IN QCA TECHNOLOGY
STUDY AND IMPLEMENTATION OF MUX BASED FPGA IN QCA TECHNOLOGY E.N.Ganesh 1 / V.Krishnan 2 1. Professor, Rajalakshmi Engineering College 2. UG Student, Rajalakshmi Engineering College ABSTRACT This paper
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br
More information(Cat. No CFM) Product Data
(Cat. No. 1771-CFM) Product Data The CFM module interfaces Allen-Bradley programmable logic controllers (PLCs ) with magnetic pickups, single-channel shaft encoders, turbine flowmeters or any source of
More informationHold Time Illustrations
Hold Time Illustrations EE213-L09-Sequential Logic.1 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential Logic.2 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationSkew Management of NBTI Impacted Gated Clock Trees
International Symposium on Physical Design 2010 Skew Management of NBTI Impacted Gated Clock Trees Ashutosh Chakraborty and David Z. Pan ECE Department, University of Texas at Austin ashutosh@cerc.utexas.edu
More informationLecture 14: State Tables, Diagrams, Latches, and Flip Flop
EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University
More informationDigital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..
Indian Institute of Technology Jodhpur, Year 2017-2018 Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationLecture 13: Sequential Circuits, FSM
Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines Reminder: midterm on Tue 2/28 will cover Chapters 1-3, App A, B if you understand all slides, assignments,
More informationProblem Set 9 Solutions
CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You
More informationIntroduction to VLSI Testing
Introduction to 李昆忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan Class Problems to Think How are you going to test A 32 bit adder A 32 bit counter A 32Mb
More informationUNIVERSITY OF CALIFORNIA
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on April 14, 2004 by Brian Leibowitz (bsl@eecs.berkeley.edu) Jan Rabaey Homework
More informationIssues on Timing and Clocking
ECE152B TC 1 Issues on Timing and Clocking X Combinational Logic Z... clock clock clock period ECE152B TC 2 Latch and Flip-Flop L CK CK 1 L1 1 L2 2 CK CK CK ECE152B TC 3 Clocking X Combinational Logic...
More informationState Machines ELCTEC-131
State Machines ELCTEC-131 Switch Debouncer A digital circuit that is used to remove the mechanical bounce from a switch contact. When a switch is closed, the contacts bounce from open to closed to cause
More informationSPICE Modeling of STT-RAM for Resilient Design. Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu (Kevin) Cao School of ECEE, ASU
SPICE odeling of STT-RA for Resilient Design Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu (Kevin) Cao School of ECEE, ASU OUTLINE - 2 - Heterogeneous emory Design A Promising Candidate:
More informationCh 9. Sequential Logic Technologies. IX - Sequential Logic Technology Contemporary Logic Design 1
Ch 9. Sequential Logic Technologies Technology Contemporary Logic Design Overview Basic Sequential Logic Components FSM Design with Counters FSM Design with Programmable Logic FSM Design with More Sophisticated
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More informationIntroduction to Quantum Logic. Chris Heunen
Introduction to Quantum Logic Chris Heunen 1 / 28 Overview Boolean algebra Superposition Quantum logic Entanglement Quantum computation 2 / 28 Boolean algebra 3 / 28 Boolean algebra A Boolean algebra is
More informationSuccessive Approximation ADCs
Department of Electrical and Computer Engineering Successive Approximation ADCs Vishal Saxena Vishal Saxena -1- Successive Approximation ADC Vishal Saxena -2- Data Converter Architectures Resolution [Bits]
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationDesign for Testability
Design for Testability Outline Ad Hoc Design for Testability Techniques Method of test points Multiplexing and demultiplexing of test points Time sharing of I/O for normal working and testing modes Partitioning
More informationI. Motivation & Examples
I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables,
More informationLecture 10, ATIK. Data converters 3
Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering
More informationSpintronics in Nanoscale Devices. Edited by Eric R. Hedin Yong S. Joe
Spintronics in Nanoscale Devices Edited by Eric R. Hedin Yong S. Joe Spintronics in Nanoscale Devices Spintronics in Nanoscale Devices edited by Eric R. Hedin and Yong S. Joe Published by Pan Stanford
More informationCombinational Logic Design Combinational Functions and Circuits
Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders
More informationMagnetization reversal in the presence of thermal agitation and spin-transfer torques
Magnetization reversal in the presence of thermal agitation and spin-transfer torques Y.P. Kalmykov, W.T. Coffey, S.V. Titov, J.E. Wegrowe, D. Byrne Université de Perpignan Trinity College Dublin IREE
More informationCSE370: Introduction to Digital Design
CSE370: Introduction to Digital Design Course staff Gaetano Borriello, Brian DeRenzi, Firat Kiyak Course web www.cs.washington.edu/370/ Make sure to subscribe to class mailing list (cse370@cs) Course text
More informationChapter 19. Magnetism
Chapter 19 Magnetism The figure shows the path of a negatively charged particle in a region of a uniform magnetic field. Answer the following questions about this situation (in each case, we revert back
More informationQuantum-Dot Cellular Automata (QCA)
Quantum-Dot Cellular Automata (QCA) Quantum dots are nanostructures [nano-: one billionth part of] created from standard semiconductive material. A quantum dot can be visualized as a well. Electrons, once
More informationThe Design Procedure. Output Equation Determination - Derive output equations from the state table
The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationIntroduction to Computer Engineering. CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison
Introduction to Computer Engineering CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationChapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>
Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite
More informationData AND. Output AND. An Analysis of Pipeline Clocking. J. E. Smith. March 19, 1990
An Analysis of Pipeline locking J E Smith March 19, 1990 Abstract This note examines timing constraints on latches in pipelined systems The goal is to determine required clock characteristics based on
More information