IDT71V2556S/XS IDT71V2556SA/XSA

Transcription

1 Features 128K x 36 memory configuratio Supports high performance system speed MHz (3.5 Clock-to-Data Access) ZBT TM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control E Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applicatio 4-word burst capability (interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expaion 3.3 power supply (±5%), 2.5 I/ Supply () ptional - Boundary Scan JTAG Interface (IEEE complaint) Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP) and 119 ball grid array (BGA) Description The IDT is a 3.3 high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBT TM, or Zero Bus Turnaround. Pin Description Summary A0-A16 Address s CE1, CE2, CE2 E R/ W CEN BW1, BW2, BW3, W CLK AD/ LB TMS TDI TCK TD Chip Enables utput Enable Read/Write Signal Clock Enable B 4 Individual Byte Write Selects Clock Advance burst address / Load new address Linear / Interleaved Burst rder Test Mode Select Test Data Test Clock Test Data utput T RST JTAG Reset (ptional) ZZ I/0-I/ 31, I/ P1-I/ P4, Sleep Mode Data / utput Core Power, I/ Power Ground 128K x ZBT SRAMs 2.5 I/, Burst Counter Pipelined utputs utput I/ Supply Supply IDT712556S/XS IDT712556SA/XSA Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT contai data I/, address and control signal registers. utput enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pi (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when AD/ is low, no new memory operation can be initiated. However, any pending data trafers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT has an on-chip burst counter. In the burst mode, the IDT can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LB input pin. The LB pin selects between linear and interleaved burst sequence. The AD/ signal is used to load a new external address (AD/ = LW) or increment the internal burst counter (AD/ = HIGH). The IDT SRAMs utilize IDT's latest high-performance CMS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA). Asynchronous N/ A Static N/ A Asynchronous Static Static 2011 Integrated Device Technology, Inc tbl 01 APRIL 2011 DSC-4875/12

2 Pin Definitio (1) Symbol Pin Function I/ Active Description A0-A16 Address s I N/ A Address inputs. The address register is CLK, AD/ L D low, C EN low, and true chip enables. triggered by a combination of the rising edge of AD/ R/ W Advance / Load I N / A AD/ is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When AD/ is low with the chip deselected, any burst in progress is terminated. When AD/ is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when AD/ L D is sampled high. Read / Write I N / A R/ W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place two clock cycles later. CEN Clock Enable I LW Clock Enable. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock traition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. BW1-BW4 Individual Byte Write Enables I LW byte write enables. Each 9-bit byte has its own active low byte write enable. n load write cycles (When R/ W and AD/ L D are sampled low) the appropriate byte write signal ( BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. CE1, CE2 Chip Enables I L W active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT ( CE1 or CE2 sampled high or CE2 sampled low) and AD/ low at the rising edge of clock, initiates a TM deselect cycle. The ZBT has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. CE2 CLK Chip Enable I HIGH Clock I N/ A active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. This is the clock input to the IDT with respect to the rising edge of CLK. Except for E, all timing references for the device are made I/0-I/ 31 I/P1-I/ P4 Data /utput I/ N/ A data input/output (I/) pi. Both and triggered by the rising edge of CLK. the data input path and data output path are registere d LB Linear Burst rder I LW Burst order selection input. When LB is high the Interleaved burst sequence is selected. When LB is low the Linear burst sequence is selected. LB is a static input and it must not change during device operation. E utput Enable I L W Asynchronous output enable. E must be low to read data from the When E is high the I/ pi are in a high-impedance state. E does not need to be actively controlled for read and write cycles. In normal operation, E can be tied low. TMS TDI TCK TD Test Mode Select I N/ A Test Data I N/ A Test Clock I N/ A Test Data utput N/ A Gives input pullup. command for TAP controller. Sampled on rising edge of TDK. This pin has an internal Serial input of registers an internal pullup. placed between TDI and TD. Sampled on rising edge of TCK. This pin has Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup. Serial output of registers the TAP controller. placed between TDI and TD. This output is active depending on the state of TRST JTAG Reset (ptional) I LW ptional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs automatically at power up and also resets using TMS and TCK per IEEE If not used T RST can be left floating. This pin has an internal pullup. ZZ Sleep Mode I HIGH sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT to its lowest power coumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown Power Supply N/ A N / A 3.3 core power supply. Power Supply N/ A N / A 2.5 I/ Supply. Ground N/ A N / A Ground. NTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK tbl

3 Functional Block Diagram LB Address A [0:16] D Q 128Kx36 BIT MEMRY ARRAY Address CE1, CE2, CE2 R/W CEN D Q Control AD/ BWx Register DI D D Q Control Logic Clk Mux Sel Clock Clk D utput Register Q E Gate 4875 drw 01a, TMS TDI TCK TRST (optional) JTAG (SA ersion) TD Data I/ [0:31], I/ P[1:4] Recommended DC perating Conditio Symbol IH IH IL P arameter M in. T yp. Max. Unit Core Supply oltag e I/ Supply oltag e Supply oltag e High oltage - s. 7 High oltag e - / I. 7 Low oltag e ( 2) ( 1) IL (min.) = 1.0 for pulse width less than tcyc/2, once per cycle. 2. IH (max.) = +6.0 for pulse width less than tcyc/2, once per cycle tbl

4 Recommended perating Temperature and Supply oltage Grade 1) T emperature ( Commercial Industrial 0 C to +70 C 0 3.3±5% 2.5±5% -40 C to +85 C 0 3.3±5% 2.5±5% NTE: 1. TA is the "itant on" case temperature tbl 05 Pin Configuration 128K x 36 A6 A7 CE1 CE2 BW4 BW3 BW2 BW1 CE2 CLK R/W CEN E AD/ NC (2) NC (2) A8 A I/P3 I/16 I/17 I/18 I/19 I/20 I/21 I/22 I/23 (1) (1) I/24 I/25 I/26 I/27 I/28 I/29 I/30 I/31 I/P I/P2 I/15 I/14 I/13 I/12 I/11 I/10 I/9 I/8 (1) /ZZ (3) I/7 I/6 I/5 I/4 I/3 I/2 I/1 I/0 I/P drw 02, LB A5 A4 A3 A2 A1 A0 NC NC NC NC A10 A11 A12 A13 A14 A15 A16 Top iew TQFP 1. Pi 14, 16 and 66 do not have to be connected directly to as long as the input voltage is IH. 2. Pi 83 and 84 are reserved for future 8M and 16M respectively. 3. Pin 64 does not have to be connected directly to as long as the input voltage is IL; on the latest die revision this pin supports ZZ (sleep mode)

5 Absolute Maximum Ratings (1) 100 TQFP Capacitance (1) Symbol (2) TERM (3,6) TERM (4,6) TERM Rating Terminal oltage with Respect to GND Terminal oltage with Respect to GND Terminal oltage with Respect to GND Commercial & Industrial alues Unit -0.5 to to -0.5 to (TA = +25 C, f = 1.0MHz) Symbol CIN CI/ 1) P arameter Capacitanc e ( onditio C Max. N I I/ Capacitanc e UT Unit = 3d 5 pf = 3d 7 pf 4875 tbl 07 NTE: 1. This parameter is guaranteed by device characterization, but not production tested. (5,6) TERM Terminal oltage with Respect to GND Commerical perating TA ( 7) T BIAS TSTG Temperature Industrial perating Temperature Temperatur e Under Bias Storage Temperature -0.5 to to +70 o C -40 to +85 o C -55 to +125 o C -55 to +125 o C 119 BGA Capacitance (1) (TA = +25 C, f = 1.0MHz) Symbol CIN CI/ 1) P arameter Capacitanc e ( onditio C Max. N I I/ Capacitanc e UT Unit = 3d 7 pf = 3d 7 pf 4875 tbl 07a NTE: 1. This parameter is guaranteed by device characterization, but not production tested. PT I UT Power Dissipatio n 2. 0 W DC utput Current 50 ma 4875 tbl Stresses greater than those listed under ABSLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. terminals only. 3. terminals only. 4. terminals only. 5. I/ terminals only. 6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or I/ pin cannot exceed during power supply ramp up. 7. TA is the "itant on" case temperature

6 Recommended perating Temperature and Supply oltage Grade 1) T emperature ( Commercial Industrial 0 C to +70 C 0 3.3±5% 2.5±5% -40 C to +85 C 0 3.3±5% 2.5±5% NTE: 1. TA is the "itant on" case temperature tbl 05 Pin Configuration 128K x 36 A6 A7 CE1 CE2 BW 4 BW 3 BW 2 BW 1 CE2 CLK R/W CEN E AD/ NC (2) NC (2) A8 A I/P3 I/16 I/17 I/18 I/19 I/20 I/21 I/22 I/23 (1) (1) I/24 I/25 I/26 I/27 I/28 I/29 I/30 I/31 I/P I/P2 I/15 I/14 I/13 I/12 I/11 I/10 I/9 I/8 (1) /ZZ (3) I/7 I/6 I/5 I/4 I/3 I/2 I/1 I/0 I/P drw 02, LB A5 A4 A3 A2 A1 A0 NC NC NC NC A10 A11 A12 A13 A14 A15 A16 Top iew TQFP 1. Pi 14, 16 and 66 do not have to be connected directly to as long as the input voltage is IH. 2. Pi 83 and 84 are reserved for future 8M and 16M respectively. 3. Pin 64 does not have to be connected directly to as long as the input voltage is IL; on the latest die revision this pin supports ZZ (sleep mode)

7 Absolute Maximum Ratings (1) 100 TQFP Capacitance (1) Symbol (2) TERM (3,6) TERM (4,6) TERM Rating Terminal oltage with Respect to GND Terminal oltage with Respect to GND Terminal oltage with Respect to GND Commercial & Industrial alues Unit -0.5 to to -0.5 to (TA = +25 C, f = 1.0MHz) Symbol CIN CI/ 1) P arameter Capacitanc e ( onditio C Max. N I I/ Capacitanc e UT Unit = 3d 5 pf = 3d 7 pf 4875 tbl 07 NTE: 1. This parameter is guaranteed by device characterization, but not production tested. (5,6) TERM Terminal oltage with Respect to GND Commerical perating TA ( 7) T BIAS TSTG Temperature Industrial perating Temperature Temperatur e Under Bias Storage Temperature -0.5 to to +70 o C -40 to +85 o C -55 to +125 o C -55 to +125 o C 119 BGA Capacitance (1) (TA = +25 C, f = 1.0MHz) Symbol CIN CI/ 1) P arameter Capacitanc e ( onditio C Max. N I I/ Capacitanc e UT Unit = 3d 7 pf = 3d 7 pf 4875 tbl 07a NTE: 1. This parameter is guaranteed by device characterization, but not production tested. PT I UT Power Dissipatio n 2. 0 W DC utput Current 50 ma 4875 tbl Stresses greater than those listed under ABSLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. terminals only. 3. terminals only. 4. terminals only. 5. I/ terminals only. 6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or I/ pin cannot exceed during power supply ramp up. 7. TA is the "itant on" case temperature

8 Pin Configuration 128K x 36, 119 BGA A A6 A4 NC(2) A8 A16 B NC CE 2 A3 AD/ A9 CE2 NC C NC A7 A2 A12 A15 NC D I/16 I/P3 NC I/P2 I/15 E I/17 I/18 CE1 I/13 I/14 F I/19 E I/12 G I/20 I/21 BW 3 NC(2) BW 2 I/11 I/10 H I/22 I/23 R/W I/9 I/8 J (1) (1) K I/24 I/26 CLK I/6 I/7 L I/25 I/27 BW 4 NC BW 1 I/4 I/5 M I/28 CEN I/3 N I/29 I/30 A1 I/2 I/1 P I/31 I/P4 A0 I/P1 I/0 R NC A5 LB (1) A13 NC, T NC NC A10 A11 A14 NC NC/ZZ (5) U NC/TMS (3) NC/TDI (3) NC/TCK (3) NC/TD (3) NC/TRST (3,4) Top iew 4875 drw 13a 1. J3, J5, and R5 do not have to be directly connected to as long as the input voltage is IH. 2. G4 and A4 are reserved for future 8M and 16M respectively. 3. These pi are NC for the "S" version and the JTAG signal listed for the "SA" version. 4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to. 5. Pin T7 supports ZZ (sleep mode) on the latest die revision

9 Truth Table (1) C EN R/ W (5) C hip Enable AD/ BWx ADDRES S USED PREIUS CYCLE CURRENT CYCLE (6) I / (2 cycles later) L L Select L alid External X LAD WRITE D (7) L H Select L X External X LAD READ Q (7) L X X H alid I nternal LAD WRITE / BURST WRITE BURST WRITE Advance burst counter) (2) ( D (7) L X X H X I nternal LAD READ / BURST READ BURST READ Advance burst counter) (2) ( Q (7) ( 3) D HiZ L X Deselect L X X X ESELECT or STP L X X H X X DESELECT / NP NP HiZ H X X X X X X USPEND 4) S ( Previous alu e 4875 tbl L = IL, H = IH, X = Don t Care. 2. When AD/ signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and AD/ is sampled low at rising edge of clock. The data bus will tri-state two cycles after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/ s remai unchanged. 5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false. 6. Device utputs are eured to be in High-Z after the first rising edge of clock upon power-up. 7. Q - Data read from the device, D - data written to the device. Partial Truth Table for Writes (1) PERATIN R/ W BW1 BW2 BW3 BW4 READ H X X X X WRITE ALL BYTES L L L L L WRITE BYTE 1 (I/[0:7], I/P 1) ( 2) L L H H H WRITE BYTE 2 (I/[8:15], I/P 2) ( 2) L H L H H WRITE BYTE 3 (I/[16:23], I/P 3) ( 2) L H H L H WRITE BYTE 4 (I/[24:31], I/P 4) ( 2) L H H H L N WRITE L H H H H 1. L = IL, H = IH, X = Don t Care. 2. Multiple bytes may be selected during the same cycle tbl

10 Interleaved Burst Sequence Table (LB=) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address Second Address Third Address ( 1) F ourth Address NTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting tbl 10 Linear Burst Sequence Table (LB=) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address Second Address Third Address ( 1) F ourth Address NTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting tbl 11 Functional Timing Diagram (1) CYCLE n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 CLCK ADDRESS (2) (A0 - A16) A29 A30 A31 A32 A33 A34 A35 A36 A37 CNTRL (2) (R/W, AD/, BW x) C29 C30 C31 C32 C33 C34 C35 C36 C37 DATA (2) I/ [0:31], I/ P[1:4] D/Q27 D/Q28 D/Q29 D/Q30 D/Q31 D/Q32 D/Q33 D/Q34 D/Q35, 4875 drw This assumes CEN, CE1, CE2, CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_ut is valid after a clock-to-data delay from the rising edge of clock

11 Device peration - Showing Mixed Load, Burst, Deselect and NP Cycles (2) Cycle A ddress R/ W AD/ C E 1) ( CE N BWx E I/ Comments n A0 H L L L X X X Load read n+1 X X H X L X X X Burst read n+2 A1 H L L L X L Q0 Load read n+3 X X L H L X L Q Deselect or STP n+4 X X H X L X L Q1 NP n+5 A2 H L L L X X Z Load read n+6 X X H X L X X Z Burst read n+7 X X L H L X L Q2 Deselect or STP n+8 A3 L L L L L L Q Load write n+9 X X H X L L X Z Burst write n+10 A4 L L L L L X D3 Load write n+11 X X L H L X X D Deselect or STP n+12 X X H X L X X D4 NP n+13 A5 L L L L L X Z Load write n+14 A6 H L L L X X Z Load read n+15 A7 L L L L L X D5 Load write n+16 X X H X L L L Q6 Burst write n+17 A8 H L L L X X D7 Load read n+18 X X H X L X X D Burst read n+19 A9 L L L L L L Q8 Load write 1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 2. H = High; L = Low; X = Don t Care; Z = High Impedance tbl 12 Read peration (1) Cycle A ddress R/ W AD/ C E 2) ( CE N BWx E I/ Comments n A0 H L L L X X X Address and Control meet setup n+1 X X X X L X X X Clock Setup alid n+2 X X X X X X L Q0 Contents of Address A0 Read ut 1. H = High; L = Low; X = Don t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L tbl

12 Burst Read peration (1) Cycle A ddress R/ W AD/ C E 2) ( CE N BWx E I/ Comments n A0 H L L L X X X Address and Control meet setup n+1 X X H X L X X X Clock Setup alid, Advance Counte r n+2 X X H X L X L Q0 Address A0 Read ut, Inc. Count n+3 X X H X L X L Q + 1 n+4 X X H X L X L Q + 2 n+5 A1 H L L L X L Q Address A0+ 1 Read ut, Inc. Count 0 Address A0+ 2 Read ut, Inc. Count 0 Address A0+ 3 Read ut, Load A1 n+6 X X H X L X L Q0 Address A0 Read ut, Inc. Count n+7 X X H X L X L Q1 Address A1 Read ut, Inc. Count n+8 A2 H L L L X L Q Address A1+ 1 Read ut, Load A2 1. H = High; L = Low; X = Don t Care; Z = High Impedance.. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L tbl 14 Write peration (1) Cycle A ddress R/ W AD/ C E 2) ( CE N BWx E I/ Comments n A0 L L L L L X X Address and Control meet setup n+1 X X X X L X X X Clock Setup alid n+2 X X X X L X X D0 rite to Address A W 0 1. H = High; L = Low; X = Don t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L tbl 15 Burst Write peration (1) Cycle A ddress R/ W AD/ C E 2) ( CE N BWx E I/ Comments n A0 L L L L L X X Address and Control meet setup n+1 X X H X L L X X Clock Setup alid, Inc. Count n+2 X X H X L L X D0 Address A0 Write, Inc. Count n+3 X X H X L L X D + 1 n+4 X X H X L L X D + 2 n+5 A1 L L L L L X D Address A0+ 1 Write, Inc. Count 0 Address A0+ 2 Write, Inc. Count 0 Address A0+ 3 Write, Load A1 n+6 X X H X L L X D0 Address A0 Write, Inc. Count n+7 X X H X L L X D1 Address A1 Write, Inc. Count n+8 A2 L L L L L X D Address A1+ 1 Write, Load A2 1. H = High; L = Low; X = Don t Care;? = Don t Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L tbl

13 Read peration with Clock Enable Used (1) Cycle A ddress R/ W AD/ C E 2) ( CE N BWx E I/ Comments n A0 H L L L X X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 H L L L X X X Clock alid n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus. n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus. n+5 A2 H L L L X L Q0 Address A0 Read out (bus tra. ) n+6 A3 H L L L X L Q1 Address A1 Read out (bus tra. ) n+7 A4 H L L L X L Q2 Address A2 Read out (bus tra. ) 1. H = High; L = Low; X = Don t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L tbl 17 Write peration with Clock Enable Used (1) Cycle A ddress R/ W AD/ C E 2) ( CE N BWx E I/ Comments n A0 L L L L L X X Address and Control meet setup. n+1 X X X X H X X X Clock n+1 Ignored. n+2 A1 L L L L L X X Clock alid. n+3 X X X X H X X X Clock Ignored. n+4 X X X X H X X X Clock Ignored. n+5 A2 L L L L L X D0 rite Data D W 0 n+6 A3 L L L L L X D1 rite Data D W 1 n+7 A4 L L L L L X D2 rite Data D W 2 1. H = High; L = Low; X = Don t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L tbl

14 Read peration with Chip Enable Used (1) Cycle A ddress R/ W AD/ C E 2) ( CE N BWx E 3) I / ( Comments n X X L H L X X? Deselected. n+1 X X L H L X X? Deselected. n+2 A0 H L L L X X Z Address and Control meet setup n+3 X X L H L X X Z Deselected or STP. n+4 A1 H L L L X L Q0 Address A0 Read out. Load A1. n+5 X X L H L X X Z Deselected or STP. n+6 X X L H L X L Q1 Address A1 Read out. Deselected. n+7 A2 H L L L X X Z Address and control meet setup. n+8 X X L H L X X Z Deselected or STP. n+9 X X L H L X L Q2 Address A2 Read out. Deselected. 1. H = High; L = Low; X = Don t Care;? = Don t Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 3. Device utputs are eured to be in High-Z after the first rising edge of clock upon power-up tbl 19 Write peration with Chip Enable Used (1) Cycle A ddress R/ W AD/ C E 2) ( CE N BWx E 3) I / ( Comments n X X L H L X X? Deselected. n+1 X X L H L X X? Deselected. n+2 A0 L L L L L X Z Address and Control meet setup n+3 X X L H L X X Z Deselected or STP. n+4 A1 L L L L L X D0 Address D0 Write in. Load A1. n+5 X X L H L X X Z Deselected or STP. n+6 X X L H L X X D1 Address D1 Write in. Deselected. n+7 A2 L L L L L X Z Address and control meet setup. n+8 X X L H L X X Z Deselected or STP. n+9 X X L H L X X D2 Address D2 Write in. Deselected. 1. H = High; L = Low; X = Don t Care;? = Don t Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 3. Device utputs are eured to be in High-Z after the first rising edge of clock upon power-up tbl

15 DC Electrical Characteristics ver the perating Temperature and Supply oltage Range ( = 3.3±5%) Symbol Parameter T est Conditio M in. Max. Unit ILI Leakage Current = Max., IN = 0 to 5 µ A IL I LB, JTAG and ZZ (1) I nput Leakage Current = Max., IN = 0 to 30 µ A IL utput Leakage Current UT = 0 to, Device Deselected 5 µ A L utput Low oltag e IL = +6mA, D D = Min H utput High oltag e IH = -6mA, D D = Min NTE: 4875 tbl The LB, TMS, TDI, TCK & TRST pi will be internally pulled to and ZZ will be internally pulled to if it is not actively driven in the application. DC Electrical Characteristics ver the perating Temperature Supply oltage Range (1) ( = 3.3±5%) Symbol Parameter Test Conditio Com'l 166MHz 150MHz 133MHz 100MHz Ind' l Com' l Ind' l Com' l Ind' l Com' l Ind' l Unit IDD perating Power Supply Current Device Selected, utputs pen, AD/ = X, D D = Max., (2) > IH o r < IL, f = fmax I N ma ISB1 CMS Standby Power Supply Current Device Deselected, utputs pen, = Max., I N > HD or (2,3) <, f = ma ISB2 Clock Running Power Supply Current Device Deselected, utputs pen, = Max., I N > HD or < L D, (2.3) f = fmax ma ISB3 Idle Power Supply Current Device Selected, utputs pen, C EN > IH, D D = Max., (2,3) I N > HD o r <, f = fmax ma 1. All values are maximum guaranteed values. 2. At f = fmax, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 mea no input lines are changing. 3. For I/s HD = 0.2, = 0.2. For other inputs HD = 0.2, = tbl 22 AC Test Loads 6 5 I/ 50Ω Z0 = 50Ω Figure 1. AC Test Load / drw 04, AC Test Conditio ( = 2.5) Pulse Rise/Fall Timing utput Timing AC Test Load Levels Times Reference Levels Reference Levels 0 to ( D DQ/2) ( D DQ/2) See Figure tbl 23 ΔtCD 3 (Ty pical, ) Capacit ance (pf ) Figure 2. Lumped Capacitive Load, Typical Derating 4875 dr w 05,

16 AC Electrical Characteristics ( = 3.3±5%, ) 166MHz 150MHz 133MHz 100MHz Symbol P arameter M in. M ax. M in. M ax. M in. M ax. M in. Max. Unit t CYC Clock Cycle Time 6 _ tf ( 1) C lock Frequenc e MHz tc H ( 2) lock High Pulse Widt h C. 8 tc L ( 2) lock Low Pulse Widt h C utput Parameters tcd C lock High to alid Data _ 5 t CDC Clock High to Data Change 1 _ ,4,5) tclz ( lock High to utput Activ e C 1 _ t C te utput Enable Access Time _ 5 3,4) LZ ( utput Enable Low to Data Activ e t 0 _ ,4,5) CHZ ( lock High to Data High- Z 3,4) HZ ( utput Enable High to Data High- Z t _ 5 Set Up Times tse tsa tsd Clock Enable Setup Time. 5 Address Setup Time. 5 Data In Setup Time ts W ead/write (R/ R W) Setup Time t SAD Advance/Load (AD/ ) Setup Time 1.5 _ tsc Chip Enable/Select Setup Time tsb Byte Write Enable ( BWx) Setup Time 1.5 _ Hold Times the tha thd Clock Enable Hold Time. 5 Address Hold Time. 5 Data In Hold Time th W ead/write (R/ t R W) Hold Time. 5 H AD Advance/Load (AD/ ) Hold Time thc Chip Enable/Select Hold Time. 5 0 th B Byte Write Enable ( BWx) Hold Time tbl tf = 1/tCYC. 2. Measured as HIGH above 0.6 and LW below Traition is measured ±200m from steady-state. 4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 5. To avoid bus contention, the output buffers are designed such that tchz (device turn-off) is about 1 faster than tclz (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tclz is a Min. parameter that is worse case at totally different test conditio (0 deg. C, 3.465) than tchz, which is a Max. parameter (worse case at 70 deg. C, 3.135)

17 Timing Waveform of Read Cycle (1,2,3,4) tcyc CLK tch tcl tse the CEN tsad thad AD/ tsw thw R/W tsa tha ADDRESS A1 A2 CE1, CE2 (2) tsc thc BW 1 - BW 4 E (CEN high, eliminates tcdc (Burst Wraps around tclz tcdc tcd tcd current L-H clock edge) to initial state) tchz DATAUT Q(A1) 1(A2) Q(A2) Q(A2+1) 2(A2) Q(A2+2) Q(A2+2) Q(A2+3) Q(A2) Pipeline Read Burst Pipeline Read Pipeline Read 4875 drw Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LB input. 2. CE2 timing traitio are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling AD/ LW. 4. R/W is don't care when the SRAM is bursting (AD/ sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM

18 Timing Waveform of Write Cycles (1,2,3,4,5) tcyc CLK tch tcl tse the C EN AD/ tsad thad tsw thw R/W tsa tha ADDRESS A1 A2 tsc (2) thc C E1, C E2 BW 1 - BW 4 tsb thb E DATAIN tsd thd (CEN high, eliminates current L-H clock edge) tsd thd (Burst Wraps around to initial state) D(A1) D(A2) D(A2+1) D(A2+2) D(A2+3) D(A2) Pipeline Write Pipeline Write Burst Pipeline Write 4875 drw D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LB input. 2. CE2 timing traitio are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling AD/ LW. 4. R/W is don't care when the SRAM is bursting (AD/ sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LW. The byte write information comes in two cycles before the actual data is presented to the SRAM

19 Timing Waveform of Combined Read and Write Cycles (1,2,3) tcyc CLK tch tcl tse the CEN tsad thad AD/ tsw thw R/W ADDRESS tsa A1 A2 tha A3 A4 A5 A6 A7 A8 A9 CE1, CE2 (2) tsc thc tsb thb BW 1 - BW 4 E tsd thd D(A2) D(A4) D(A5) DATAIN Write Write tchz tclz tcdc tcd DATAUT Q(A1) Q(A3) Q(A6) Q(A7) Read Read Read 4875 drw Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing traitio are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LW. The byte write information comes in two cycles before the actual data is presented to the SRAM

20 Timing Waveform of CEN peration (1,2,3,4) tcyc CLK tch tcl tse the C EN tsad thad AD/ tsw thw R/W tsa tha ADDRESS A1 A2 A3 A4 A5 tsc thc C E1, C E2 (2) tsb thb B(A2) BW 1 - BW 4 E tsd thd DATAIN tchz D(A2) tcdc tcd DATAUT Q(A1) Q(A1) Q(A3) tclz 4875 drw Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing traitio are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H traition of the clock from propogating into the SRAM. The part will behave as if the L-H clock traition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LW. The byte write information comes in two cycles before the actual data is presented to the SRAM

21 Timing Waveform of CS peration (1,2,3,4) CLK tse tch tcl the C EN tsad thad AD/ tsw thw R/W tsa tha ADDRESS A1 A2 A3 A4 A5 C E1, C E2 (2) tsc thc tsb thb BW 1 - BW 4 E tsd thd DATAIN tchz D(A3) tcd tcdc DATAUT Q(A1) tclz Q(A2) Q(A4) 4875 drw Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3. 2. CE2 timing traitio are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H traition of the clock from propogating into the SRAM. The part will behave as if the L-H clock traition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LW. The byte write information comes in two cycles before the actual data is presented to the SRAM

22 JTAG Interface Specification (SA ersion only) tjf tjcl tjr tjcyc tjch TCK Device s (1) / TDI/TMS tjs tjh tjdc Device utputs (2) / TD tjrsr tjcd TRST (3) tjrst M4875 drw 01 x 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TD. 3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset. JTAG AC Electrical Characteristics (1,2,3,4) Symbol t JCYC t tjch tjcl tjr tjf JRST P arameter M in. Max. JTAG Clock Period 00 JTAG Clock HIGH 0 JTAG Clock Low 0 J TAG Clock Rise Time J TAG Clock Fall Time JTAG Reset Units 5 ( 1) 5 ( 1) 5 Scan Register Sizes Register Name Bit Size Itruction (IR) 4 Bypass (BYR) 1 JTAG Identification (JIDR) 32 B oundary Scan (BSR) Note (1) I4875 tbl 03 NTE: 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available by contacting your local IDT sales representative. t JRSR JTAG Reset Recovery 0 5 tjcd J TAG Data utput 20 tjdc tjs tjh JTAG Data utput Hold 0 JTAG Setup 5 JTAG Hold I4875 tbl Guaranteed by design. 2. AC Test Load (Fig. 1) on external output signals. 3. Refer to AC Test Conditio stated earlier in this document. 4. JTAG operatio occur at one speed (10MHz). The base device may run at any speed specified in this datasheet

23 JTAG Identification Register Definitio (SA ersion only) Itruction Field alue Description Revision Number (31:28) 0 x2 Reserved for version number. IDT Device ID (27:12) 0 x210, 0x212 Defines IDT part number SA, respectively. IDT JEDEC ID (11:1) 0 x33 Allows unique identification of device vendor as IDT. ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register. I4875 tbl 02 Available JTAG Itructio Itruction Description PCDE EXTEST SAMPLE/PRELAD DEICE_ID HIGHZ ( 1) u. Forces contents of the boundary scan cells onto the device o tputs Places the boundary scan register (BSR) between TDI and TD. Places the boundary scan register (BSR) between TDI and TD. 2) S AMPLE allows data from device inputs ( a nd output s( 1) to be capture d in the boundary scan cells and shifted serially through TD. PRELAD allows data to be input serially into the boundary scan cells via the TDI. Loads the JTAG ID register (JIDR) with t he register between TDI and TD. Places the bypass register (BYR) between device output drivers to a High-Z state. the vendor ID code TDI and and places TD. Forces all RESERED RESERED Several combinatio are reserved. Do not use codes other than those 0101 identified for EXTEST, SAMPLE/PRELAD, DEICE_ID, HIGHZ, CLAMP, RESERED ALIDATE and BYPASS itructio RESERED CLAMP RESERED Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TD RESERED 1010 Same as above. RESERED 1011 RESERED 1100 ALIDATE Automatically loaded into the itruction register whenever the TAP controller passes through the CAPTURE-IR state. The lower two bits '01' are mandated by the IEEE std specification R ESERED Same as above BYPASS The BYPASS itruction as a single bit in length. is used to truncate the boundary scan register 1111 I4875 tbl Device outputs = All device outputs except TD. 2. Device inputs = All device inputs except TDI, TMS, and TRST

24 Timing Waveform of E peration (1) E te thz tlz DATAUT alid NTE: 1. A read operation is assumed to be in progress drw 11 rdering Information XXXX X XX XX XX X X X Device Type Power Speed Package Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I Commercial (0 C to +70 C) Industrial (-40 C to +85 C) G Green PF** BG 100-pin Plastic Thin Quad Flatpack (TQFP) 119 Ball Grid Array (BGA) S SA Clock Frequency in Megahertz Standard Power Standard Power with JTAG Interface Blank X First generation or current die step Current generation die step optional Kx36 Pipelined ZBT SRAM with 2.5 I/ 4875 drw 12 ** JTAG (SA version) is not available with 100-pin TQFP package

25 Datasheet Document History 6/30/99 Updated to new format 8/23/99 Added Smart ZBT functionality Pg. 4, 5 Added Note 4 and changed Pi 38, 42, and 43 to DNU Pg. 6 Changed U2 U6 to DNU Pg. 14 Added Smart ZBT AC Electrical Characteristics Pg. 15 Improved tcd and te(max) at 166MHz Revised tchz(min) for f 133 MHz Revised thz (MAX) for f 133 MHz Improved tch, tcl for f 166 MHz Improved setup times for MHz Pg. 22 Added BGA package diagrams Pg. 24 Added Datasheet Document History 10/4/99 Pg. 14 Revised AC Electrical Characteristics table Pg. 15 Revised tchz to match tclz and tcdc at 133MHz and 100MHz 12/31/99 Removed Smart functionality Added Industrial Temperature range offerings at the 100 to 166MHz speed grades. 04/30/00 Pg. 5,6 Add clarification note to Recommended Temperature Ratings and Absolute Max Ratings table; Add note to TQFP Pin Configuratio Pg. 6 Add BGA Capacitance table Pg. 7 Add note to BGA Pin Configuratio Pg. 21 Iert TQFP Package Diagram utline 05/26/00 Add new package offering, 13 x 15mm 165fBGA Pg. 23 Correct 119 BGA Package Diagram utline 07/26/00 Pg. 5,6,7 Add zz, sleep mode reference note to TQFP, BG119 and BQ165 pinouts Pg. 8 Update BQ165 pinout Pg. 23 Update BG119 package diagram outlines 10/25/00 Remove Preliminary Status Pg. 8 Add note to pin N5, BQ165 pinout reserved for JTAG TRST 5/20/02 Pg. 1-8,15,22,23,27 Added JTAG "SA" version functionality & updated ZZ pin descriptio and notes. 10/15/04 Pg. 7 Updated pin configuration for the 119 BGA - reordered I/ signals on P6, P7 (128K x 36) and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18). 02/23/07 Pg. 27 Added X generation die step to ordering information. 10/13/08 Pg. 27 Removed "IDT" from orderable part number 05/24/10 Pg. 27 Added "Restricted hazardous substance device" to the ordering information 04/11/11 Pg Removed (EL), fbga 165 pin and 200MHz. Pg. 13,14 Added 150MHz data for Commercial & Industrial information. Pg. 22 Added 150MHz and Tape and Reel to rdering information and updated description of Restricted hazardous substance device to Green. CRPRATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek alley Rd or sramhelp@idt.com San Jose, CA fax: The IDT logo is a registered trademark of Integrated Device Technology, Inc. ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc