80386DX. 32-Bit Microprocessor FEATURES: DESCRIPTION: Logic Diagram

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32-Bit Microprocessor 21 1 22 1 2 10 3 103 FEATURES: 32-Bit microprocessor RAD-PAK radiation-hardened agait natural space radiation Total dose hardness: - >100 Krad (Si), dependent upon space mission

MeV/mg/cm 2 - SEU Cross section 1E-3 cm 2 /bit Package: - 1 Pin RAD-PAK quad flat pack 8, 1, 32-Bit data types 8 general purpose 32-Bit registers Hardware debugging support Very large address space:

for system development - Pipelined itructio - On-chip caches support address tralation - 32 megabytes/sec bus bandwidth DESCRIPTION: Logic Diagram DDC's high performance 32-bit microprocessor

1 32-Bit Microprocessor FEATURES: 32-Bit microprocessor RAD-PAK radiation-hardened agait natural space radiation Total dose hardness: - >100 Krad (Si), dependent upon space mission Single event effect: - SEL TH = 3-0 MeV/mg/cm 2 - SEU TH = 3. MeV/mg/cm 2 - SEU Cross section 1E-3 cm 2 /bit Package: - 1 Pin RAD-PAK quad flat pack 8, 1, 32-Bit data types 8 general purpose 32-Bit registers Hardware debugging support Very large address space: - gigabyte physical - terabyte Virtual - gigabyte maximum segment size Integrated memory management unit - Virtual memory support - Four levels of protection - Fully compatible with 80C28 Optimized for system development - Pipelined itructio - On-chip caches support address tralation - 32 megabytes/sec bus bandwidth DESCRIPTION: Logic Diagram DDC's high performance 32-bit microprocessor features a geater than 100 krad (Si) total dose tolerance, dependent upon space mission. It is designed for very high performance and multitasking operating systems. The integrated memory management and protection architecture includes address tralation registers, multitasking hardware and a protection mechanism to support operating systems. The allows simultaneous running of multiple operatio. In addition, the is capable of execution at sustained rates of between 3 and million itructio per second. It offers new testability and debugging features, including a self-test and direct access to the page tralation cache. DDC's patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 1 (31) Fax: (31)

2 TABLE 1. PIN DESCRIPTION PIN SYMBOL DESCRIPTION 1-, 9, 10, 12, 13, 1, 1, 20, 21, 2, 1-19, 12-1, 1-19, 113 8, 18, 19, 22, 23, 2, 28-30, 33, 3, 38-0,, 8,,, 8, 3,,, 82, 8, 8, 88, 103, 10, 10, 11, 12, 12, 129, 130,133, 13, 1, 1, 10, 1 11, 1, 2, 32, 3, 3, 1, 3,,, 1, 0, 92, 9, 100, 111, 118, 122, 138, 12, 11 1, 2, 31, 3,, 0, 2,,, 8, 2, 9, 91, 9, 99, 110, 11, 13, 11, 10, A1-A11, A9, A10, A, A8, A, A, A3, A, A2, A31-A28, A2-A2, A23-A22, A20-A18 NC V SS V CC Address Bus Not Connected Ground Power Supply 3 INTR Interupt Request 1 NMI Non-Maskable Interupt Request 2 PEREQ Processor Exteion Request ERROR Error Status RESET Reset 9 BUSY Busy Status 9 LOCK Bus Lock 0 W/R Write/ Read 3 M/IO I/O D/C Data Control, 1, 2, BE2, BE0, BE3, BE1 Byte Enables 8 BS1 Bus Size 1 NA Next Address 9 HOLD Bus Hold Request 80 CLK2 CPU Clock 2 81 ADS Address Staus 83 READY Bus Ready Input 8, 8, 89, 90, 93, 9, 9, 98, 102, 10, 10, 108, 109, 112, 113, 11, 11, 119, 120, 121, 123, 12, 12, 128, 131, 132, 13, 13, 139, 10, 13, 1, D1, D2, D, D0, D, D3, D8, D, D, D10, D9, D12, D11, D1, D13, D1, D1, D18, D1, D20, D22, D19, D2, D21, D2,D23, D2, D2, D29, D28, D31, D30, Data Bus 101 HLDA Bus Hold Acknowledge 2

3 TABLE 2. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNIT Supply Voltage with Respect to Ground V SS -0.. V Voltage on other pi -0. V CC +0. V Thermal Impedance Θ JC 1.9 C/W Operating Temperature Range (Ambient) T A - 12 C Storage Temperature Range (Ambient) T S - 10 C TABLE 3. DELTA LIMITS PARAMETER VARIATION I CC ±10% of specified value in Table I LI ±10% of specified value in Table I LO ±10% of specified value in Table TABLE. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNIT Digital Supply Voltage V CC..2 V Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V CLK2 Input Low Voltage V ILC 0.8 V CLK2 Input High Voltage V IHC V CC V Operating Temperature Range T A C TABLE. DC ELECTRICAL CHARACTERISTICS (V CC = +V ±%; T A = - C TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL CONDITION MIN MAX UNIT Input Leakage Current I LI All pi except BS1, PEREQ, BUSY, and ERROR 0V < V IN < V CC µ A Output Leakage Current I LO 0.V < V OUT < V CC µ A Output Low Voltage V OL I OL = ma: A2 - A31, D0 - D31 0. V I OL = ma: BE0 - BE3, W/R, D/C, M/IO, LOCK, ADS, HLDA 0. Output High Voltage V OH I OH = 1 ma: A2 - A31, D0 - D31 2. V I OH = 0.9 ma: BE0 - BE3, W/R, D/C, M/IO, LOCK, ADS, HLDA 2. 3

4 Power Supply Current I CC CLK2 = 32 MHz with 1 MHz Processor 0 ma CLK2 = 32 MHz with 20 MHz Processor 0 CLK2 = 32 MHz with 2 MHz Processor 80 Input Leakage Current I IH PEREQ Pin µ A I IL BS1, BUSY, ERROR Pi 2-00 µ A CLK2 Capacitance 3 C CLK F C = 1 MHz 20 pf Input or I/O Capacitance 1 C IN F C = 1 MHz 20 pf Output Capacitance 1 C OUT F C = 1 MHz 2 pf 1. V IH = 2.V. PEREQ input has an internal pulldown resistor. 2. V IL = 0.V. BS1, BUSY and ERROR inputs have an internal pulldown resistor. 3. Guaranteed by design. TABLE. DC ELECTRICAL CHARACTERISTICS (V CC = +V ±%; T A = - C TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL CONDITION MIN MAX UNIT TABLE. AC ELECTRICAL CHARACTERISTICS (V CC = +V ±10%; V PP = V SS ; T A = - C TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL CONDITION MIN MAX UNIT Operating Frequency Half of CLK2 Frequency MHz CLK2 Period t CLK2 High Time t 2a at 2V 9 8 CLK2 High Time 1 t 2b at (V CC - 0.8V) CLK2 Low Time t 3a at 2V 9 8 CLK2 Low Time 1 t 3b at (V CC - 0.8V)

5 TABLE. AC ELECTRICAL CHARACTERISTICS (V CC = +V ±10%; V PP = V SS ; T A = - C TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL CONDITION MIN MAX UNIT CLK2 Fall Time 1 t (V CC - 0.8V) to 0.8V 8 8 CLK2 Rise Time 1 t 0.8V to (V CC - 0.8V) 8 8 A2 - A31 Valid Delay t C L = 120pF (C L = 0pF for 2 MHz) A2 - A31 Float Delay 1, 2 BE0 - BE3, LOCK Valid Delay t t 8 C L = pf (C L = 0pF for 2 MHz) BE0 - BE3, LOCK Float Delay 1, 2 t W/R, M/IO, D/C and ADS Valid Delay t 10 C L = pf (C L = 0pF for 2 MHz) W/R, M/IO, D/C and ADS Float Delay 1, 2 t D0 - D31 Valid Delay t 12 C L = 120pF (C L = 0pF for 2 MHz) D0 - D31 Float Delay 1, 2 t HLDA Valid Delay t 1 C L = pf (C L = 0pF for 2 MHz)

6 TABLE. AC ELECTRICAL CHARACTERISTICS (V CC = +V ±10%; V PP = V SS ; T A = - C TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL CONDITION MIN MAX UNIT N/A Setup Time t N/A Hold Time t BS1 Setup Time t BS1 Hold Time READY Setup Time t t READY Hold Time t 20 D0 - D31 Read Setup Delay t D0 - D31 Read Hold Delay t 22 HOLD Setup Time t HOLD Hold Time t 2 3 RESET Setup Time t

7 TABLE. AC ELECTRICAL CHARACTERISTICS (V CC = +V ±10%; V PP = V SS ; T A = - C TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL CONDITION MIN MAX UNIT RESET Hold Time t 2 3 NMI, INTR Setup Time 3 t NMI, INTR Hold Time 3 t REREQ, ERROR, BUSY Setup Time 3 REREQ, ERROR, BUSY Hold Time 3 t t Guaranteed by design. 2. Float condition occurs when maximum when output current becomes less than ILO in magnitude. 3. These inputs are allowed to be asynchronous to CLK2. The setup and hold specificatio are given for testing purposes, to assure recognition within a specific CLK2 period.

8 32-Bit Microprocessor FIGURE 1. AC TEST LOADS FIGURE 2. CLK2 TIMING 8

9 32-Bit Microprocessor FIGURE 3. INPUT SETUP AND HOLD TIME 9

10 FIGURE. OUTPUT VALID DELAY TIMING FIGURE. WRITE DATA VALID DELAY TIMING (2 MHZ) 10

11 FIGURE. WRITE DATA HOLD TIMING (2 MHZ) FIGURE. WRITE DATA VALID DELAY TIMING (20 MHZ) 11

12 32-Bit Microprocessor FIGURE 8. TYPICAL OUTPUT VALID DELAY VERSUS LOAD CAPACITANCE AT MAXIMUM OPERATING TEMPERATURE (C L = 120 PF) FIGURE 9. TYPICAL OUTPUT VALID DELAY VERSUS LOAD CAPACITANCE AT MAXIMUM OPERATING TEMPERATURE (C L = PF) 12

13 32-Bit Microprocessor FIGURE 10. TYPICAL OUTPUT VALID DELAY VERSUS LOAD CAPACITANCE AT MAXIMUM OPERATING TEMPERATURE (C L = 0 PF) FIGURE 11. TYPICAL OUTPUT RISE TIME VERSUS LOAD CAPACITANCE AT MAXIMUM OPERATING TEMPERATURE 13

14 FIGURE 12. OUTPUT FLOAT DELAY AND HLDA AND DELAY TIMING FIGURE 13. RESET SETUP AND HOLD TIMING, AND INTERNAL PHASE 1

15 SYMBOL 1-PIN RAD-PAK QUAD FLAT PACKAGE DIMENSION MIN NOM MAX A b c D D BSC e 0.02 BSC S F F L L L A N 1 Q1-01 Note: All dimeio in inches 1

16 32-Bit Microprocessor Important Notice: These data sheets are created using the chip manufacturer s published specificatio. DDC verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specificatio presented within these data sheets represent the latest and most accurate information available to date. However, these specificatio are subject to change without notice and DDC assumes no respoibility for the use of this information. DDC's products are not authorized for use as critical components in life support devices or systems without express written approval from DDC. Any claim agait DDC must be made within 90 days from the date of shipment from DDC. DDC's liability shall be limited to replacement of defective parts. 1

17 Product Ordering Optio Model Number RP Q X XX Feature Option Details Processing Speed in MHz Screening Flow Monolithic S = DDC Class S B = DDC Class B E = Engineering +2 C) I = Industrial - C, +2 C, +12 C) Package Q = Quad Flat Pack Radiation Feature RP = RAD-PAK package Base Product Nomenclature 32-Bit Microprocessor 1

8-CHANNEL MULTIPLEXER DESCRIPTION: FEATURES: SEi 338RP

8-CHANNEL MULTIPLEXER DESCRIPTION: FEATURES: SEi 338RP A0 1 16 A1 V+ V- GND EN V- NO1 NO2 NO3 SEi 338RP A2 GND V+ NO5 NO6 NO1 NO2 NO3 NO4 NO5 NO6 NO7 NO8 COM NO4 NO7 CMOS DECODE LOGIC COM 8 9 NO8 A2 A1A0 EN FEATURES: DESCRIPTION: RAD-PAK Technology hardened