54F 74F410 Register Stack 16 x4ram TRI-STATE Output Register

Transcription

1 54F 74F410 Register Stack 16 x4ram TRI-STATE Output Register General Description The F410 is a register-oriented high-speed 64-bit Read Write Memory organized as 16-words by 4-bits An edgetriggered 4-bit output register allows new input data to be written while previous data is held TRI-STATE outputs are provided for maximum versatility The F410 is fully compatible with all TTL families Commercial Military Package Number Features Edge-triggered output register Typical access time of 35 TRI-STATE outputs Optimized for register stack operation 18-pin package 9410 replacement Package Description 74F410PC N18A 18-Lead (0 300 Wide) Molded Dual-In-Line 54F410DM (Note 1) J18A 18-Lead Ceramic Dual-In-Line August F410SC M20B 20-Lead (0 300 Wide) Molded Small Outline JEDEC 54F410LM W20A 20-Lead Cerpak Note 1 Military grade device with environmental and burn-in processing Use suffix e DMQB LMQB Logic Symbol TL F Pin Assignment for DIP and SOIC Connection Diagrams TL F Pin Assignment for LCC TL F F 74F410 Register Stack 16 x 4 RAM TRI-STATE Output Register TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9538 RRD-B30M105 Printed in U S A

2 Unit Loading Fan Out 54F 74F Pin Names Description U L Input I IH I IL HIGH LOW Output I OH I OL A 0 A 3 Address Inputs ma b0 6 ma D 0 D 3 Data Inputs ma b0 6 ma CS Chip Select Input (Active LOW) ma b1 2 ma OE Output Enable Input (Active LOW) ma b0 6 ma WE Write Enable Input (Active LOW) ma b0 6 ma CP Clock Input (Outputs Change on LOW-to-HIGH Traition) ma b1 2 ma Q 0 Q 3 TRI-STATE Outputs (33 3) b3 ma 24 ma (20 ma) Functional Description Write Operation When the three control inputs Write Enable (WE) Chip Select (CS) and Clock (CP) are LOW the information on the data inputs (D 0 D 3 ) is written into the memory location selected by the address inputs (A 0 A 3 ) If the input data changes while WE CS and CP are LOW the contents of the selected memory location follow these changes provided setup and hold time criteria are met Block Diagram Read Operation Whenever CS is LOW and CP goes from LOW-to-HIGH the contents of the memory location selected by the address inputs (A 0 A 3 ) are edge-triggered into the Output Register The (OE) input controls the output buffers When OE is HIGH the four outputs (Q 0 Q 3 ) are in a high impedance or OFF state when OE is LOW the outputs are determined by the state of the Output Register TL F

3 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specificatio Storage Temperature b65 Ctoa150 C Ambient Temperature under Bias b55 Ctoa125 C Junction Temperature under Bias b55 Ctoa175 C Plastic b55 Ctoa150 C V CC Pin Potential to Ground Pin b0 5V to a7 0V Input Voltage (Note 2) b0 5V to a7 0V Input Current (Note 2) b30 ma to a5 0 ma Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0 5V to V CC TRI-STATE Output b0 5V to a5 5V Current Applied to Output in LOW State (Max) twice the rated I OL (ma) Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditio is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol Parameter 54F 74F Min Typ Max Recommended Operating Conditio Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b55 Ctoa125 C 0 Ctoa70 C a4 5V to a5 5V a4 5V to a5 5V Units V CC Conditio V IH Input HIGH Voltage 2 0 V Recognized as a HIGH Signal V IL Input LOW Voltage 0 8 V Recognized as a LOW Signal V CD Input Clamp Diode Voltage b1 2 V Min I IN eb18 ma V OH Output HIGH 54F 10% V CC 2 5 I OH eb1ma Voltage 54F 10% V CC 2 4 I OH eb3ma 74F 10% V CC 2 5 V Min I OH eb1ma 74F 10% V CC 2 4 I OH eb3ma 74F 5% V CC 2 7 I OH eb3ma V OL Output LOW 54F 10% V CC 0 5 I V Min OL e 20 ma Voltage 74F 10% V CC 0 5 I OL e 24 ma I IH Input HIGH 54F 20 0 Current 74F 5 0 ma Max V IN e 2 7V I BVI Input HIGH Current 54F 100 Breakdown Test 74F 7 0 I CEX Output HIGH 54F 250 Leakage Current 74F 50 V ID I OD Input Leakage Test Output Leakage Circuit Current 74F 4 75 V F 3 75 ma 0 0 I IL Input LOW Current b0 6 b1 2 ma Max V IN e 7 0V ma Max V OUT e V CC ma Max I ID e 1 9 ma All Other Pi Grounded V IOD e 150 mv All Other Pi Grounded I OZH Output Leakage Current 50 ma Max V OUT e 2 7V I OZL Output Leakage Current b50 ma Max V OUT e 0 5V I OS Output Short-Circuit Current b60 b150 ma Max V OUT e 0V V IN e 0 5V (A n D n OE WE) V IN e 0 5V (CS CP) I ZZ Bus Drainage Test 500 ma 0 0V V OUT e 5 25V 3

4 DC Electrical Characteristics (Continued) Symbol Parameter 54F 74F Units V CC Conditio Min Typ Max I CCH Power Supply Current ma Max V O e HIGH I CCL Power Supply Current ma Max V O e LOW I CCZ Power Supply Current ma Max V O e HIGH Z AC Electrical Characteristics 74F 54F 74F Symbol Parameter T A ea25 C T A V CC e Mil T A V CC e Com V CC ea5 0V C L e 50 pf C L e 50 pf C L e 50 pf Min Max Min Max Min Max t PLH Propagation Delay t PHL CP to Q t PZH Enable Time t PZL OE to Q t PHZ Disable Time t PLZ OE to Q Units AC Operating Requirements Symbol READ MODE Parameter 74F 54F 74F T A ea25 C V CC ea5 0V T A V CC e Mil T A V CC e Com Units Min Max Min Max Min Max t s (H) Setup Time HIGH or LOW t s (L) A n to CP t h (H) Hold Time HIGH or LOW t h (L) A n to CP WRITE MODE t s (H) Setup Time HIGH or LOW t s (L) A n to WE t h (H) Hold Time HIGH or LOW t h (L) A n to WE t s (H) Setup Time HIGH or LOW t s (L) D n to WE t h (H) Hold Time HIGH or LOW t h (L) D n to WE t w WE Pulse Width Required to Write t w t w CS Pulse Width Required to Write CP Pulse Width Required to Write Note Military temperature range for this device is b40 C toa85 C

5 Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 74F 410 S C X Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP S e Small Outline (SOIC) D e Ceramic DIP L e Package Leadless Chip Carrier Special Variatio X e Devices shipped in 13 reels QB e Military grade device with environmental and burn-in processing Temperature Range C e Commercial (0 Ctoa70 C) M e Military (b55 Ctoa125 C) 5

6 Physical Dimeio inches (millimeters) 18-Lead Ceramic Dual-In-Line Package (D) NS Package Number J18A 20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M20B 6

7 Physical Dimeio inches (millimeters) (Continued) 18-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N18A 7

8 54F 74F410 Register Stack 16 x 4 RAM TRI-STATE Output Register Physical Dimeio inches (millimeters) (Continued) LIFE SUPPORT POLIC 20-Lead Cerpack NS Package Number W20A NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with itructio for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 c com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any respoibility for use of any circuitry described no circuit patent licees are implied and National reserves the right at any time without notice to change said circuitry and specificatio