54F 74F373 Octal Transparent Latch with TRI-STATE Outputs
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1 54F 74F373 Octal Traparent Latch with TRI-STATE Outputs General Description The F373 coists of eight latches with TRI-STATE outputs for bus organized system applicatio The flip-flops appear traparent to the data when Latch Enable (LE) is HIGH When LE is LOW the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state Features Y Y Y Eight latches in a single package TRI-STATE outputs for bus interfacing Guaranteed 4000V minimum ESD protection Commercial Military Package Number Package Description 74F373PC N20A 20-Lead (0 300 Wide) Molded Dual-In-Line 54F373DM (QB) J20A 20-Lead Ceramic Dual-In-Line 74F373SC (Note 1) M20B 20-Lead (0 300 Wide) Molded Small Outline JEDEC 74F373SJ (Note 1) M20D 20-Lead (0 300 Wide) Molded Small Outline EIAJ 74F373MSA (Note 1) MSA20 20-Lead Molded Shrink Small Outline EIAJ Type II 54F373FM (QB) W20A 20-Lead Cerpack 54F373LM (QB) E20A 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX SJX and MSAX Logic Symbols IEEE IEC Pin Assignment for DIP SOIC SSOP and Flatpak Connection Diagrams Pin Assignment for LCC May F 74F373 Octal Traparent Latch with TRI-STATE Outputs TL F TL F TL F TL F TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9523 RRD-B30M75 Printed in U S A
2 Unit Loading Fan Out 54F 74F Pin Names Description U L Input I IH I IL HIGH LOW Output I OH I OL D 0 D 7 Data Inputs ma b0 6 ma LE Latch Enable Input (Active HIGH) ma b0 6 ma OE Output Enable Input (Active LOW) ma b0 6 ma O 0 O 7 TRI-STATE Latch Outputs (33 3) b3 ma 24 ma (20 ma) Functional Description The F373 contai eight D-type latches with TRI-STATE output buffers When the Latch Enable (LE) input is HIGH data on the D n inputs enters the latches In this condition the latches are traparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW traition of LE The TRI-STATE buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches Truth Table Inputs Output LE OE D n O n H L H H H L L L L L X O n (no change) X H X Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance State Logic Diagram TL F Please note that this diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays 2
3 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specificatio Storage Temperature b65 Ctoa150 C Ambient Temperature under Bias b55 Ctoa125 C Junction Temperature under Bias b55 Ctoa175 C Plastic b55 Ctoa150 C V CC Pin Potential to Ground Pin b0 5V to a7 0V Input Voltage (Note 2) b0 5V to a7 0V Input Current (Note 2) b30 ma to a5 0 ma Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditio is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol Parameter 54F 74F Min Typ Max Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) Recommended Operating Conditio Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b0 5V to V CC b0 5V to a5 5V twice the rated I OL (ma) 4000V b55 Ctoa125 C 0 Ctoa70 C a4 5V to a5 5V a4 5V to a5 5V Units V CC Conditio V IH Input HIGH Voltage 2 0 V Recognized as a HIGH Signal V IL Input LOW Voltage 0 8 V Recognized as a LOW Signal V CD Input Clamp Diode Voltage b1 2 V Min I IN eb18 ma V OH Output HIGH 54F 10% V CC 2 5 I OH eb1ma Voltage 54F 10% V CC 2 4 I OH eb3ma 74F 10% V CC 2 5 I V Min OH eb1ma 74F 10% V CC 2 4 I OH eb3ma 74F 5% V CC 2 7 I OH eb1ma 74F 5% V CC 2 7 I OH eb3ma V OL Output LOW 54F 10% V CC 0 5 I V Min OL e 20 ma Voltage 74F 10% V CC 0 5 I OL e 24 ma I IH Input HIGH Current 54F F 5 0 I BVI Input HIGH Current 54F 100 Breakdown Test 74F 7 0 I CEX Output HIGH 54F 250 Leakage Current 74F 50 V ID I OD Input Leakage Test Output Leakage Circuit Current 74F 4 75 V F 3 75 ma 0 0 ma Max V IN e 2 7V ma Max V IN e 7 0V ma Max V OUT e V CC I IL Input LOW Current b0 6 ma Max V IN e 0 5V I ID e 1 9 ma All Other Pi Grounded V IOD e 150 mv All Other Pi Grounded I OZH Output Leakage Current 50 ma Max V OUT e 2 7V I OZL Output Leakage Current b50 ma Max V OUT e 0 5V I OS Output Short-Circuit Current b60 b150 ma Max V OUT e 0V I ZZ Bus Drainage Test 500 ma 0 0V V OUT e 5 25V I CCZ Power Supply Current ma Max V O e HIGH Z 3
4 AC Electrical Characteristics 74F 54F 74F Symbol Parameter T A ea25 C T A V CC e Mil T A V CC e Com V CC ea5 0V C L e 50 pf C L e 50 pf C L e 50 pf Min Typ Max Min Max Min Max t PLH Propagation Delay t PHL D n to O n t PLH Propagation Delay t PHL LE to O n t PZH Output Enable Time t PZL t PHZ Output Disable Time t PLZ Units AC Operating Requirements Symbol Parameter 74F 54F 74F T A ea25 C V CC ea5 0V T A V CC e Mil T A V CC e Com Units Min Max Min Max Min Max t s (H) Setup Time HIGH or LOW t s (L) D n to LE t h (H) Hold Time HIGH or LOW t h (L) D n to LE t w (H) LE Pulse Width HIGH Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F 373 S C X Temperature Range Family 74FeCommercial 54FeMilitary Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ MSA e Shrink Small Outline (EIAJ SSOP) Special Variatio QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13 reel Temperature Range CeCommercial (0 Ctoa70 C) MeMilitary (b55 Ctoa125 C) NOTE Not required for MSA package code 4
5 Physical Dimeio inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 5
6 Physical Dimeio inches (millimeters) (Continued) 20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M20B 20-Lead (0 300 Wide) Small Outline Package EIAJ (SJ) NS Package Number M20D 6
7 Physical Dimeio inches (millimeters) (Continued) 20-Lead Molded Shrink Small Outline Package EIAJ Type II (MSA) NS Package Number MSA20 20-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 7
8 54F 74F373 Octal Traparent Latch with TRI-STATE Outputs Physical Dimeio inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with itructio for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd Hong Kong Ltd Do Brazil Ltda (Australia) Pty Ltd 2900 Semiconductor Drive Livry-Gargan-Str 10 Sumitomo Chemical 13th Floor Straight Block Rue Deputado Lacorda Franco Building 16 P O Box D F4urstenfeldbruck Engineering Center Ocean Centre 5 Canton Rd 120-3A Business Park Drive Santa Clara CA Germany Bldg 7F Tsimshatsui Kowloon Sao Paulo-SP Monash Business Park Tel 1(800) Tel (81-41) Nakase Mihama-Ku Hong Kong Brazil Nottinghill Melbourne TWX (910) Telex Chiba-City Tel (852) Tel (55-11) Victoria 3168 Australia Fax (81-41) 35-1 Ciba Prefecture 261 Fax (852) Telex NSBR BR Tel (3) Tel (043) Fax (55-11) Fax (3) Fax (043) National does not assume any respoibility for use of any circuitry described no circuit patent licees are implied and National reserves the right at any time without notice to change said circuitry and specificatio
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