Redesigning The Element Of Random Access Memory (RAM) For Enhanced Computer Processing Speed

Size: px

Start display at page:

Download "Redesigning The Element Of Random Access Memory (RAM) For Enhanced Computer Processing Speed"

Anastasia King
5 years ago
Views:

1 Redesigning The Element Of Random Access Memory (RAM) For Enhanced Computer Processing Speed Samson O. Ogunlere 1, Olawale J. Omotosho 2 1 Computer Engineering Research Scholar, Computer Science Dept., Babcock University, Ogun State, Nigeria. 2 Professor, Computer Science Dept., Babcock University, Ogun State, Nigeria Abstract - The speed of operation of any computer is governed by the Processor and Memory. It becomes important therefore, that in order to improve the processing speed of a computer, both the Processor and Main Memory design must be improved. Hence, this study is aimed at increasing the Main Memory speed of a computer by redesigning the components that make upthe computer main memory from transistor level to memory element(flip Flop) level.in-depth analytical study of fundamentals of memory elements (Flip-Flops) from firstprinciples to conversion of one Flip-Flop type to another in order to determine which of thevarious possibilities would result in achieving the highest speed of the computer memory wasdone. The design of basic memory devices, using the different Set and Reset (SR) memory elements developedfrom the analytical and numerical frameworks, was also done.analysis of eachdesign was established using Propagation Time tool in order todetermine which of them gave greater prospects for higher computer speed. It was proved that the NEW SR-Flip Flop at 50% utilization presentsthe highest potential and high prospect for higher computer speed when compared with the conventional SR-Flip Flop judging from the number of transitions required to complete a propagation route. Keywords: Memory Element (Flip Flops), Propagation Time framework, NEW SET-RESET Flip Flop, Propagation route. 1.0 Introduction In earlier computers, the most common form of randomaccess storage for computer main memory employed an array of doughnut-shaped ferromagnetic loops referred to as cores. The basic element of a semiconductor memory is the memory cell (appropriately gated-flip Flop). Although a varietyof electronic technologies are used, all semiconductor memory cells share certain properties and characteristics, some of which are as follows; i. Exhibit two stable (or semi-stable), self-maintaining states that are used as storage/ memory elements capable of storing a binary digit (1 and 0). ii. Capable of being written into (at least once), to set the state. iii. Capable of being read to sense the state. v. Have three transition states known as Resting, Forbidden and Active states with four possible binary combinations of input variables [5], [6]. 1.1 Foundation of Memory Element Set and Reset (SR)Memory Elementbeing the foundation of all the Memory Elements known as Flip Flops (FF) can be constructed from a pair of cross-coupled NOR Logic Gates or cross-coupled NAND Logic Gates.There are twelve possible design options of an SR-FF; but two design options that are conventionally accepted configuration are in use today as shown in Figures 1a and 1b, respectively. The conventional SR-Flip Flops that contains only two gates obviously do not function fully as an SR-Flip Flop because there are four active/transitional states in any SR-Flip Flop which suggests a minimum number of gates that may be required to meet this requirement. The SR-Flip Flops have four binary combinations. Because of the sequential nature of Flip Flops (feedback), for each combination, there are eight transition states as shown in Table 1.1.The active states are identified and analyzed from the SR-Flip Flop Truth Table in Tables 1.1 using the NOR and NAND gates which are the two design active elements of SR-Flip Flips. For the SR-FF to function fully, four gates are required because only two active states are involved as observed in Table 1.1. The stored bit is present on the output marked Qn+1. Feedback maintains the Q n+1 and the complement Q n+1 output in a constant state, while the S and R inputs are both low. Hence, it is obvious that one of the transition states will be attached to two input combinations which in effect increase the usefulness of such Flip Flop from 25% to 50% active states utilization; that is: 4 active states transitional states = 50% iv. Derived from Sequential Logic Circuits which are the main electronics circuits that make the development of computers possible. 1

2 Table 1.1: Truth Table of SR-Flip Flop (Adopted from Omotosho, 2012; Volnei & Pedroni, 2008; Mano &Kime, 2004) NOR Configuration NAND Configuration S R Q n Q n+1 TransitionState S R Q n Q n+1 TransitionState Resting d Forbidden Resting d Forbidden Active Active Active Active Active Active Active Active D Forbidden Resting D Forbidden Resting NOTES: Q n = previous output, Q n+1 = present output, D = I don t care term (0,1) 1.2 Design Logic Circuit of an SR-Flip Flop The Truth Table of Table 1.1 is converted into a K-Map in order to obtain the minimized logic equations of the SR-Flip Flop as shown in Table 1.2. Table 1.2: K-Map of SR-Flip Flop (SR-FF) Using NOR Gates (SR-FF) Using NAND Gates Q n Q n d 1 0 d D 1 1 d QQ nn+11 = SS + RR QQ nn (22. 11) QQ nn+11 = RR + SS QQ nn (22. 22) QQ nn+11 = SS + RRQQ nn (22. 33) QQ nn+11 = RR + SSQQ nn (22. 44) Logic equations (2.1, 2.2) and (2.3, 2.4) are derived from the K-Map, and they can be used to construct the Flip Flop using the different gates as given by the equations. However, it is customary to use NOR and NAND gates to construct logic equations (2.1, 2.2) and (2.3, 2.4), respectively, by converting the equations into these gates. Themathematical analysis of these equations using DeMorgan s theorem and Boolean algebra rules is as follows: QQ nn+11 = SS + RR QQ nn (22. 11) RR QQ nn = RR + QQ nn (2.1aa) SS QQ nn = SS + QQnn (2.1dd) Substituting equations (2.1d) into (2.1a), we have QQ nn+1 = RR + SS + QQ nn (2.1ee) Complement equation (2.1e), we have QQ nn+11 = RR + SS + QQ nn ( ) Combining equations (2.1c) and (2.1f) results in the construction of SR-FF Logic Circuit Diagram, using only NOR gates as shown in Figure 1(a). Similarly the same procedure is followed to obtain the logic circuit diagram of SR-FF using NAND Gates as shown in Figure 1(b). Put equation (2.1a) into (2.1), we have QQ nn +1 = SS + RR + QQ nn (2.1bb) Complement equation (2.1b), we have QQ nn+11 = SS + RR + QQ nn ( ) Also; Since, QQ nn+11 = RR + SS QQ nn in equation 2.2, Fig. 1(a): SR NOR gates Flip Flop Then, 2

The device has two inputs, SET (S) and RESET (R) and two outputs which are complement of each other ( Q n+1 and Q n+1 ). 2.

3 5. SR-FF Boolean equation is Q n+1 = S + R Q nand Q n+1 = R + S Q n using NOR gates and Q n+1 = S + R Q n and Q n+1 = R + S Q n using NAND gates. Fig. 1(b): SR NAND gates Flip Flop Equation Equation The SR Flip Flop is credited with the following characteristics: 1. The device has two inputs, SET (S) and RESET (R) and two outputs which are complement of each other ( Q n+1 and Q n+1 ). 2. The device has three transition states known as Resting, Active and Forbidden states. 3. Analysis shows that it has 50% application utilization, hence these types of Flip-Flops have some design limitations in the forbidden states (invalid sates), when S = R = 1 simultaneously. 4. The SR Flip-Flop (SR-FF) serves as a good beginning in the design of memory element. 2.0 Designing Alternative SR-Flip Flops Possibilities of alternative SR-Flip Flops, to conventional SR-Flip Flop are proposed. The alternative SR-Flip Flops are tagged New SR-FF No 1, New SR-FF No 2, New SR-FF No 3, New SR-FF No 4, and New SR-FF No 5 as highlighted in Tables1.3and 1.7 respectively according to our adopted convention. The K-map of the NEW SR-FF No 2 is shown in Table 1.5based on Truth Table of Table 1.3. The mathematical simplification of equations (3.1 and 3.2) using DeMorgan s Theorem and Boolean algebra rules in which real circuit design of the NEW SR-FF is developed is shown in Figures 2. Table 1.3: Building Memory Cell Using Alternative SR-FF Configurations Table 1.4: K-Map for NEW SR-FF No 1 This design is not feasible because: (Changing from zero to one) does not exist (Changing from zero to zero) produces indeterminate condition 3

2) QQ nn+11 = SS + QQ nn RR... (3.1) QQ nn +1 = SS + QQ nn + RR... (3.1a) (3.3) (3.4) This is the mathematical simplification using DeMorgan s Theorem and Boolean algebra rules for NEW SR-FF No 3.

4 Table 1.5: K-Map for NEW SR-FF No 2 real circuit design of the NEW SR-FF No 3 is developed is shown in Figure 3. Table 1.6: K-Map for NEW SR-FF No 3..(3.1) The mathematical simplification using DeMorgan s Theorem and Boolean algebra rules for NEW SR-FF No 2 is as seen below. QQ nn RR = QQnn + RR QQ nn+1 = SS + QQ nn + RR (3.2) QQ nn+11 = SS + QQ nn RR... (3.1) QQ nn +1 = SS + QQ nn + RR... (3.1a) (3.3) (3.4) This is the mathematical simplification using DeMorgan s Theorem and Boolean algebra rules for NEW SR-FF No 3. QQ nn+1 = SS QQ nn + SS RR... (3.3) SS QQ nn = QQnn + SS SS RR = RR + SS QQ nn+1 = QQ nn + SS + RR + SS QQ nn +1 = QQ nn + SS + RR + SS... (3.3a) QQ nn+11 = SSQQ nn + SSRR... (3.2) SSSS nn = QQ nn + SS SSRR = RR + SS QQ nn+11 = QQ nn + SS + RR + SS QQ nn+11 = QQ nn + SS + RR + SS... (3.2a) QQ nn +1 = SS + QQ nn RR... (3.4) QQ nn RR = QQ nn + RR QQ nn+1 = SS + QQ nn + RR QQ nn+1 = SS + QQ nn + RR... (3.4a) Combining equations 3.3a and 3.4a gives the circuit diagram of Figure 3. Combining equations 3.1a and 3.2a gives the circuit diagram of Figure 2. R S R S Figure 3: Logic Circuit of NEW SR-FF No 3Using NOR gates configuration Figure 2: Logic Circuit of NEW SR-FF No 2 Using NOR gates configuration Now let us consider designing other NEW SR-FF using Table 1.7. Similarly, the K-map of the NEW SR-FF No 3 is shown in Table 1.6 based on Truth Table of Table 1.3. The mathematical simplification of equations (3.3 and 3.4) using DeMorgan s Theorem and Boolean algebra rules in which 4

Table 1.7: Building Memory Cell Using Alternative SR-FF Configurations This design is not feasible because: 1. 1 0 (Changing from zero to one) does not exist 2.

5 Table 1.7: Building Memory Cell Using Alternative SR-FF Configurations This design is not feasible because: (Changing from zero to one) does not exist (Changing from zero to zero) produces indeterminate condition The K-map of the NEW SR-FF No 4 is shown in Table 1.8 based on Truth Table of Table 1.7. The mathematical simplification of equations (3.5 and 3.6) using DeMorgan s Theorem and Boolean algebra rules in which real circuit design of the NEW SR-FF No. 4 is developed as shown in Figures 4. It should be noted that the NEW SR-FF No 5 is not feasible because 1 0 output does not exist and the condition required for 1 1 is indeterminate in the Truth Table of Table 1.7. Table 1.8: K-Map for NEW SR-FFs Nos 4 and 5 SR-FF No 4: 0[1,3]2 SR-FF No 5: 0[2,3] x x x x QQ nn+1 = SS RR + QQ nn SS QQ nn +1 = SS + QQ nn RR From the K-map of Table 1.8, equations 3.5 and 3.6 were derived concerning the NEW SR-FF No 4. The mathematical simplification using DeMorgan s Theorem and Boolean algebra rules for the NEW SR-FF No 4 is seen as follows:..(3.5) (3.6) QQ nn+1 = QQ nn RR + QQ nn SS QQ nn +1 = SSQQ nn + QQ nn RR QQ nn+1 = SS QQ nn + SS RR... (3.5) SS QQ nn = QQnn + SS SS RR = RR + SS QQ nn+1 = QQ nn + SS + RR + SS QQ nn +1 = QQ nn + SS + RR + SS... (3.5a) QQ nn +1 = SS + QQ nn RR... (3.6) QQ nn RR = QQ nn + RR R S QQ nn+1 = SS + QQ nn + RR QQ nn+1 = SS + QQ nn + RR... (3.6a) Figure 4: Logic Circuit of NEW SR-FF No 4Using NOR gates configuration Combining equations 3.5a and 3.6a will produce the circuit diagram of Figure 4. 5

6 3.0 Data Presentation and the Resulting Design of all SR-FFs at 50% Active States Considering using the Set and Reset (SR) Flip Flops as Basic Memory Element, the Data Presentation and the Resulting Design can be derived from the Input Combination Table 1.9. Table 1.9: Truth Table of Memory Elements on the NEW SR-FLIP FLOPs Nos. 2,3, 4 and the conventional SR-FF S/N S e I W Q Q n+1 S 2 R R R n 2 S 3 3 S 4 4 S Conv x x 0 x 0 x 0 X x x 1 x x X x x 0 x 0 x 0 X x x 1 x x X x x 0 x 0 x 0 X x x 1 x x X x x 0 x 0 x 0 X x x 1 x x X x x 0 x 0 x 0 X x x 1 x xx X x x 0 x 0 x 0 X x x 0 x 0 x 0 X x x 1 x x X x x 1 x 0 X X Input Combination Table SR-FF No 2 SR- No SR-FF No 4 SR-FF Conv. 3 The values of S and R are plotted into their respective K-Maps as shown in Table 1.10 from where the corresponding logic equations 4.1 and 4.2 are derived. Table 1.10: K-MAP FOR NEW SR-FF No 2 SS 2 = SS ee II WW. (4.1) RR 2 = SS ee II WW.. (4.2) S e I S e I WQ n 00 x 0 x 4 x 12 x 8 WQ n 00 x 0 x 4 x 12 x x 1 x 5 x 13 x x 3 x 7 x x 2 x x x 2 x x 10 When the values of S and R are plotted into their respective K-Maps as shown in Table 1.10, from where the corresponding logic equations (S = S e.i.w and R = S e. I.W) are derived, the logic network of Figure 5 is obtained for the NEW SR-FF No2 configuration. R Conv. Figure 5: Basic Memory Element (Using the NEW SR-FF No 2). Similarly, the same goes for the NEW SR-FF No 3 as can be seen in the K-Map Table 1.11.The values of S and R are plotted into their respective K-Maps as shown in Table 1.11 from where the corresponding logic equations 4.3 and 4.4 are derived. Table 1.11: K-MAP FOR NEW SR-FF No 3 SS 3 = SS ee IIII. (4.3) RR 3 = SS ee II WW.. (4.4) S e I S e I WQ n WQ n 00 x 0 x 4 x 12 x 8 01 x 1 x 5 x 13 x x 3 x 7 x x 2 x x 10 6

The resulting logic network diagram so obtained is shown in Figure 6. It should be known that the NEW SR-FFs Nos. 2 and 3 have similar logic network configuration with NAND gate in both.

7 The resulting logic network diagram so obtained is shown in Figure 6. It should be known that the NEW SR-FFs Nos. 2 and 3 have similar logic network configuration with NAND gate in both. Figure 6: Basic Memory Element (Using the NEW SR-FF No 3). Similarly, the NEW SR-FF No 4 K-Map is shown in Table 1.12 where their corresponding logic equations 4.5 and 4.6 are derived. Table 1.12: K-MAP FOR NEW SR-FF No 4 SS 3 = SS ee IIII. (4.5) RR 3 = SS ee.. (4.6) S e I S e I WQ n WQ n 00 x 0 x 4 x 12 x 8 01 x 1 x 5 x 13 x 9 01 x 1 x 5 x 13 x 9 11 x 3 x 7 x x 3 x 7 x x 2 x x 10 The resulting circuit diagram is shown in Figure 7. Figure 7: Basic Memory Element (Using the NEW SR-FF No 4). For the Conventional SR-FF designated S Conv. &R Conv. the values of S and R are plotted into their respective K-Maps as shown in Table 1.13 from where the corresponding logic equations 4.7 and 4.8 are derived. Table 1.13: K-Maps for Conventional SR- Flip Flop (50%) When the values of S and R are plotted into their respective K-Maps as shown in Table 4.13, from where the corresponding logic equations (S = S e.i.w and R = S e. I.W) are derived. The resulting circuit diagram for conventional SR-FF is shown in Figure 8. Figure 8: Basic Memory Element (Using Conventional 50% SR-FF). 3.1 Summary of Memory Elements Design The summary of Basic Memory Elements of all the different SR-Flip Flop Configurations is presented in Table

Table 1.14: Summary of the Different Memory Element Designs S/N TYPE OF FLIP FLOPS STORAGE DEVICE 1. Basic Memory Element made of SR-FF will be active only when SR = 00, 01 & 10 (50%) 2.

8 Table 1.14: Summary of the Different Memory Element Designs S/N TYPE OF FLIP FLOPS STORAGE DEVICE 1. Basic Memory Element made of SR-FF will be active only when SR = 00, 01 & 10 (50%) 2. Basic Memory Elements made of the NEW SR- FF Nos. 2, 3 and 4 will only be active when SR = 00, 01 & 10 (50%) 3. Basic Memory Elements made of the NEW SR- FF No 4 will be considered This is the conventional SR-FF used to build Storage Media This can be used to build Storage Media This presents fewer network gate(s). Just one AND gate as against three gates in SR-FF Nos. 2 and Comparative Performance Analysis of different Flip Flop Configurations with respect to Propagation Time Framework. In digital logic design, analysis of Propagation Time is a measure of performance, which in this case speed performance of Computer memory. The propagation time is determined by the number of transitions required to complete a propagation route in Flip Flop configuration. This is used toexamine the performance sensitivity of the variousflip Flop configurations in other to ascertain their comparative performances. To demonstrate the utility andflexibility of thisframework, it is important to know the number of transistors per gate that make up a basic memory element. This is paramount in determining the performance or how fast a memory element is. The following should be noted in a Bipolar Junction Transistor (BJT): i. Buffer has 2Transistors ii. Inverter gate has 1Transistor iii. AND gate has 3Transistors iv. OR gate has 3Transistors v. NAND gate has 2Transistors, and vi. NOR gate has 2Transistors It is important to know that: n - Input OR gate has (n+1) Transistor. n - Input NOR gate has (n) Transistor. n - Input AND gate has (n+1) Transistor. n - Input NAND gate has (n) Transistor. 4.1 Determination of Transition Routes Starting with SRconventional memory elements, the propagation time for this Flip Flop is examined in Figures 9 where T represents Transistor(s) and G represents Gate(s). Table 1.15 shows the number of transitions required to complete a propagation route in this Flip Flop configuration. Figure 9: Basic Memory Element (Using Conventional 50% SR-FF). 8

9 Table 1.15: Number of transitions required for the Conventional SR-FF Configuration SIGNAL TRANSITION ROUTE REMARKS Select, S e 3-Input AND-gate 1 Ext S 2-Input NOR-gate 1 2-Input NOR-gate 4 QQ Two 2-Input NOR-gate 1 & 4 has [4T] Total No of Gates [Transistors] = 3 Write Command, W Data to be written, I 3-Input AND-gate 1 Ext S 2-Input NOR-gate 3 QQ 3-Input AND-gate 2 Ext R 2-Input NOR-gate 2 2-Input NOR-gate 3 QQ 3-Input AND-gate 2 Ext R 2-Input NOR-gate 4 QQ 3-Input AND-gate 1 Ext S 2-Input NOR-gate 1 2-Input NOR-gate 4 QQ 3-Input AND-gate 1 Ext S 2-Input NOR-gate 3 QQ 3-Input AND-gate 2 Ext R 2-Input NOR-gate 2 2-Input NOR-gate 3 QQ 3-Input AND-gate 2 Ext R 2-Input NOR-gate 4 QQ Inverter 3-Input AND-gate 1 Ext S 2-Input NOR-gate 1 2-Input NOR-gate 4 QQ Inverter 3-Input AND-gate 1 Ext S 2-Input NOR-gate 3 QQ Inverter 3-Input AND-gate 2 Ext R 2-Input NOR-gate 2 2-Input NOR-gate 3 QQ Inverter 3-Input AND-gate 2 Ext R 2-Input NOR-gate 4 QQ [8T] One 2-Input NOR-gate 3 has [2T] Total No of Gates [Transistors] = 2 [6T] One 3-Input AND-gate 2 Ext has [4T] Two 2-Input NOR-gate 2 & 3 have [4T] Total No of Gates [Transistors] = 3 [8T] One 3-Input AND-gate 2 Ext has [4T] One 2-Input NOR-gate 4 has [2T] Total No of Gates [Transistors] = 2 [6T] Two 2-Input NOR-gate 1 & 4 have [4T] Total No of Gates [Transistors] = 3 [8T] One 2-Input NOR-gate 3 has [2T] Total No of Gates [Transistors] = 2 [6T] One 3-Input AND-gate 2 Ext has [4T] Two 2-Input NOR-gate 2 & 3 have [4T] Total No of Gates [Transistors] = 3 [8T] One 3-Input AND-gate 2 Ext has [4T] One 2-Input NOR-gate 4 has [2T] Total No of Gates [Transistors] = 2 [6T] One Inverter has [1T] Two 2-Input NOR-gate 1 & 4 have [4T] Total No of Gates [Transistors] = 4 [9T] One Inverter has [1T] One 2-Input NOR-gate 3 has [2T] Total No of Gates [Transistors] = 3 [7T] One Inverter has [1T] Two 2-Input NOR-gate 2 & 3 have [4T] Total No of Gates [Transistors] = 4 [9T] One Inverter has [1T] One 2-Input NOR-gate 4 has [2T] Total No of Gates [Transistors] = 2 [7T] NOTE: The maximum delay is caused by the data route passing through four (4) gates. In determining the transition route for conventional SR-FF, the propagation time is determined by the number of gates the signals have to pass through from the inputs of the Flip-Flop to its outputs. Having known the number of gates, the number of Transistors is determined as shown in Table 1.15 with 9 Transistors as maximum delay caused by data route passing through 4 gates. 9

10 For the NEW SR-FF, using NEW SR-FF No 4 configuration, the propagation time route is analysed as shown in Figure 10 Table External Network Figure 10: Basic Memory Element (Using NEW SR-FF Configuration) Table 1.16: Number of transitions required for the NEW SR-FF Configuration SIGNAL TRANSITION ROUTE REMARKS Select, S e 3-Input AND-gate 1 Ext S 2-Input NORgate 5 QQ One 2-Input NOR-gate has [2T] Write Command, W Data to be written, I 1 2-Input NOR-gate 3 QQ 2 2-Input NOR-gate 3 QQ R Inverter 2-Input NOR-gate 1 & 3 QQ R 2-Input NOR-gate 4 & 5 QQ 5 QQ 1 2-Input NOR-gate 3 QQ 2 2-Input NOR-gate 3 QQ 5 QQ 1 2-Input NOR-gate 3 QQ 2 2-Input NOR-gate 3 QQ Total No of Gates [Transistors] = 2 [6T] One Inverter has [1T] Two 2-Input NOR-gate has [4T] Total No of Gates [Transistors] = 3 [5T] Two 2-Input NOR-gate has [4T] Total No of Gates [Transistors] = 2 [4T] One 2-Input NOR-gate has [2T] Total No of Gates [Transistors] = 2 [6T] One 2-Input NOR-gate has [2T] Total No of Gates [Transistors] = 2 [6T] NOTE: RESET (R) Terminal is permanently connected to logic HIGH. So, it does not contribute to any delay that might be experienced by RAM built with this Flip-Flop. The maximum delay is caused by the data route passing through (3) gates with 8 Transistors. 4.2 Summary of Comparative Performance Analysis of different SR- Flip Flops From the above analysis, Figure 10 produces a Basic Memory Element that can be used to configure RAMs of different capacities towards faster computer processing speed. Take for instance, if a 10GB Dynamic RAM (DRAM) made of Flip Flop configuration in Figure 10 is used, 10G transistors are eliminated thereby increasing the speed of the RAM by a factor of 10 9 compared with 10

11 the commercially available DRAMs that are made up of conventional SR Flip Flop configuration of Figure 9. Comparing the number of transitions required to complete a propagation route in Flip Flop configuration of Figure 10 and that of Figure 9; it becomes evident that the Basic Memory Element of Figure 10 is having maximum delay caused by data route passing through 3 gates and operating with maximum number of 8 transistors as against Figure 9 with 9 transistors through 4 gates. [7] Volnei A. and Pedroni, (2008), Digital electronics and design with VHDL, Retrievedfrom [8] Wang D. T. (2005).Modern Dram Memory Systems: Performance Analysis and Scheduling Algorithm.PhD dissertation, University of Maryland, U.S.A Since the ultimate metric of memory system performance is related to how fast it can service critical requests from processors; the rationale used to justify the focus of this study is that by improving the Memory Element used for designing memory system, the average request service time can be reduced. This study shows remarkable speed improvement. 5.0 Conclusion This study has established that the developed design has a lot of added performance advantages over the conventional SR-Flip Flop in terms of speed (because fewer gates enhance speed; i.e., gate delay represents performance),portability (less transistors, smaller size design of devices) and reduction in cost(because it requires fewer transistors as against the conventional Flip Flops). It is an established fact that in digital device design, numbers of transistors represent hardware cost. References [1] Ogunlere S. O.,&Omotosho O. J. (2015). Design of a more efficient and effective Flip-Flop to JK- Flip Flop.International Research Journal of Engineering and Technology (IRJET),02(04), [2] Inouye J., Molloy P.,&Wisler M. (2012).Overcoming the Memory Wall. Oregon State University [3] Lawrence A. (2012). Processor Speed versus Memory. Retrieved fromwww.bleepingcomputer.com Computer Tutorials Hardware Tutorials [4] Mano M. M. &Kime C. R. (2004).Logic and Computer Design Fundamentals. 3 rd Edition. Upper Saddle River, NJ, USA, Pearson Education International [5] Omotosho O. J. (2012). Fundamentals of Digital Systems, Franco-Ola publishers, Ibadan, Niigeria [6] Stallings W. (2010). Computer Organization and Architecture Designing for performance. Eighth Edition. Pearson Prentice Hall publication 11

[Omotosho, 2(9): September, 2013] ISSN: Impact Factor: 1.852

[Omotosho, 2(9): September, 2013] ISSN: Impact Factor: 1.852 IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY Analysis and Design of Different Flip Flops, Extensions of Conventional JK-Flip Flops Prof. Olawale J. Omotosho *1, Engr. Samson