A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC constraints

Transcription

1 A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC constraints Ashish Hari, Sulabh Kumar Khare Accellera Systems Initiative 1

2 Agenda SOC implementation challenge with CDC paths Typical Design flow in presence of CDC paths Limitations of traditional methods Proposed automatic CDC constraints generation method Interpreting SDC constraints from CDC infromation Results Conclusions Accellera Systems Initiative 2

3 SOC implementation challenge with CDC paths Increasing System Integration Increasing Peripherals and External Interfaces Complex Power Management for Low Power More clocks More number of Domain crossing paths Increased effort for SOC implementation Time to Market Compromised Incorrect constraints Causing Chip failures

4 Typical Design flow in presence of CDC paths RTL Setup netlist Synthesis SDC Maximum delay requirement of CDC paths violated STA False Negative slack for CDC paths netlist SDC Place and Route Synchronizer flops placements issues netlist SDC 4

5 Limitations of Traditional methods Rely on manual work to define constraints for CDC paths Error prone Iterative and time consuming No single place to capture CDC intent in constraints CDC paths generate false errors Constraints added to ignore these paths Some CDC paths may never be captured May escape unconstrained Accellera Systems Initiative 5

6 Proposed flow: Automatic generation of CDC constraints SDC (Synopsys Design constraints) is standard for capturing design constraints Extend CDC tool to generate CDC constraints for Implementation tools in SDC format Avoid multiple iterations due to manual constraints Ensures CDC paths are handled correctly in synthesis, STA and place & Route Accellera Systems Initiative 6

7 Inputs and Outputs of CDC tools RTL Constraints CDC Verification DB Reports SDC Takes RTL and Constraints as input Once CDC verification is complete: Complete CDC constraints are available Accellera Systems Initiative 7

8 Proposed automatic CDC constraints generation flow RTL CDC SDC Setup Start with CDC constraints as part of SDC Synthesis netlist SDC STA CDC Paths constraints: Correct by construction netlist SDC Place and Route netlist SDC Accellera Systems Initiative 8

9 Interpreting SDC from CDC information Components of CDC to capture: 1. Clock and clock groups 2. Port constraints 3. False path (CDC crossing) 4. Constants 5. Maximum delay for synchronizer flops Each component can be specified using SDC commands Accellera Systems Initiative 9

10 SDC for CDC constraints: Clocks Defining clocks Defining asynchronous clock domains create_clock : Specifies primary Clocks create_generated_clock : Specifies derived clocks Infer all clocks as synchronous by default. Asynchronous domain categorization - set_clock_groups -asynchronous group <clocks> create_clock -name CLK_11 -period 90 -waveform { 0 45 } { CLK_11 } create_clock -name PHY_rx_clk -period 90 -waveform { 0 45 } { PHY_rx_clk } set_clock_groups -asynchronous -group { CLK_11 } group { CLK_12 } set_clock_groups -asynchronous -group { PHY_rx_clk } Accellera Systems Initiative 10

11 SDC for CDC constraints: Primary ports Constraining primary ports in correct clock domains May need to edit for actual delay Primary port constraints set_input_delay set_output_delay set_input_delay 0 -clock [get_clocks { PCLK_I }] [get_ports { DBG_rd_data }] set_input_delay 0 -clock [get_clocks { PCLK_I }] [get_ports { EE_addr_in_hw }] set_output_delay 0 -clock [get_clocks { PCLK_I }] [get_ports { HIF_tx_rx }] set_output_delay 0 -clock [get_clocks { PCLK_I }] [get_ports { HIF_tx_stat_vec_en }] Accellera Systems Initiative 11

12 SDC for CDC constraints: Constants Constraining constants Netlist constant Mode signals CLK1 Constant Port Information (Mode Signals) set_case_analysis set_logic_zero set_logic_one CLK2 Select set_case_analysis 0 { TEST_EN } set_case_analysis 0 { SCAN_EN } Accellera Systems Initiative 12

13 SDC for CDC constraints: False Paths Specify False Paths for Clock domain crossing paths Clock Domain Crossing paths CLK Tx Tx Rx Rx1 set_false_path from TX to RX CLK Rx set_false_path -from { HIF.HIF_OPI.MIB.MIB_bssid_5_2[15:8] } -to { MAC_CORE.MSCAN.MSCAN_CTRL.PS_bg_preauth_sleep_int_mode } -through { HIF.HIF_OPI.MIB.MIB_bssid[31:24] HIF.HIF_OPI.MIB_bssid[31:24] HIF.MIB_bssid[31:24] MAC_CORE.MIB_bssid[31:24] } Accellera Systems Initiative 13

14 SDC for CDC constraints: Maximum delay Constraining synchronizer for max delay requirement delay < 1 RX clk cycle Tx Rx Clock Domain Crossing paths set_max_delay Rx Rx 1 set_max_delay -from { HIF.MIB.MIB_bssid_5_2[15:8] } -to { MAC_CORE.MSCAN.sleep_int_mode } [get_attribute CLK_11 period] Accellera Systems Initiative 14

15 Results Traditional Method of CDC constraints identification Run Clocks False paths (CDC) Timing Not met Not met MHz 0 Number of negative slack paths Proposed Method to automatically generate CDC constraints Run Clocks False paths (CDC) Timing Number of negative slack paths MHz 0 Accellera Systems Initiative 15

16 Conclusion Easy and Reliable Setup with SDC Iterative nature of traditional methods is eliminated Acceptable constraints in initial run itself Automatic generations of constraints in standard format Avoid mistakes due to manual work Experiments with proposed methodology highlight all these benefits on customer designs. Accellera Systems Initiative 16

17 Questions Accellera Systems Initiative 17