Problem Formulation for Arch Sim and EM Model

Size: px
Start display at page:

Download "Problem Formulation for Arch Sim and EM Model"

Transcription

1 Problem Formulation for Arch Sim and EM Model 1 Problem Formulation 1.1 System Description The system consists of M modules, each module has L wire segments. The wire segments are routed in same or different metal layers available for a process technology. Figure 1 shows this system in the form of a tree structure. The system is at the root of the tree whereas the wire segments form the leaf nodes in the tree. The system, in our case, is a functional unit. Table 1 is a glossary of terminology used in the problem description and formulation. Figure 1: System Description as a tree. 1.2 Inputs to the EM Model 1. Foundry technology LEF with T re f, α re f and MT T F re f as in Table 1. The LEF describes design rules for current density limits, J peak,max, J rms,max and J avg,max based on these reference values. 2. The number of years, N, of operation after which probability of failure of the system is to be calculated. 1

2 Table 1: Glossary of terms Term Range Meaning T re f 105 C Foundry reference temperature α re f 0.2 Foundry reference switching activity MT T F re f 10 years Foundry reference Mean Time to Failure MT T F red - Reduced Mean Time to Failure J peak,max Foundry peak current density limit J rms,max J peak α re f Foundry RMS current density limit J J peak α re f Foundry avg current density limit avg,max (same for AC and DC) m i i = 1,2,..M module with index i p i i = 1,2,..M probability of failure of m i s j j = 1,2,..L wire segment with index j α j 0 < α j 1 switching activity of s j W min, j j = 1,2,..L Foundry min. wire width for s j W max, j j = 1,2,..L Foundry max. wire width for s j w 0, j W min, j w 0, j W max, j width of s j after initial place and route w red, j w 0, j w red, j W max, j width of s j when s j MTTF is MT T F red λ j j = 1,2,..K failure rate of s j p j j = 1,2,..L probability of failure of s j J peak, j j = 1,2,..L Peak current density of s j J rms, j j = 1,2,..L RMS current density of s j λ j j = 1,2,..L failure rate of s j T joule,max 5 Max incr in temperature due to Joule-heating T T j T re f + T joule,max s j temperature increase j due to Joule-heating (for AC stress) MT T F j 1/λ j MTTF of s j MT T F EQ, j - Equivalent MTTF of s j at α j and T j P re f 0 P re f 1 probability of failure of system with MT T F re f P red 0 P red 1 probability of failure of system with MT T F red MT T F - MTTF of the system N 1,2,..,MT T F re f Years of operation E a 0.7eV Activation energy of AlCu metal ions B ev /K Boltzmann s constant t ins 0.27µm Inter-layer dielectric (ILD) thickness K ins 28W/m K Thermal conductivity of ILD t m 0.125µm for M1, M2 Thickness of metal wire W m 0.07µm for M1, M2 Minimum width of metal wire ρ K 1 Resistivity of metal wire at 300K β K 1 Temperature coefficient of ρ ρ(t j ) ρ 0 (1 + βt joule,max ) Resistivity of metal wire at T j W e f f W m t ins Effective width for 2D heat conduction [2] t F ins tmwmρ(t j ) T h K ins W e f f Thermal factor 3. Switching activity of each wire segment, α j ( j = 1,2,..,L) 1.3 Model Assumptions The EM model assumes the system has been placed and routed within a given die area and has met timing constraints, i.e., has no paths with a negative slack. 1.4 Model Constraints 1. Temperature of a wire segment, T j can increase at most by T joule,max due to Joule-heating [2] under AC stress. T joule,max = 5K for most designs. 2. P red P re f 2

3 1.5 Model Objective Reduce MTTF under given inputs and constraints. 1.6 Model Outputs 1. Reduced MTTF, MT T F red. 2. Probability of failure of the system, P re f, P red and MTTF of the system, MT T F. 2 Model Development 2.1 Model with Foundry Guardband Algorithm 1 Probability of Failure of System Procedure ProbFail [1] For each module m i, i = 1,..,M [2] For each wire segment, s j, j = 1,..,L [3] J rms, j α j J peak,max ; [4] T j T re f + Jrms, 2 j F T h; ( Jrms,max [5] MT T F EQ, j MT T F re f J rms, j [6] λ j 1/MT T F EQ, j ; ) 2 e Ea B (1/T j 1/T re f ) ; [7] p j 1 e λ j N ; //because MTTF is exponentially distributed L [8] p i 1 (1 p j ); j=1 [9] if MT T F re f then M [10] P re f 1 (1 p i ); i=1 [11] MT T F N loge(1 P re f ) [12] else M [13] P red 1 (1 p i ); i=1 [14] MT T F N loge(1 P red ) In lines [1] and [2] of Algorithm 1, we iterate through all the M modules in the system and L wire segments in a module respectively. In line [3], we calculate the RMS current density for each wire segment from the peak AC density defined by the foundry for the metal layer to which the wire segment belongs. In line [4], we calculate the effective temperature on the wire segment after accounting for temperature rise due to Joule-heating. In line [5], we calculate the equivalent MTTF for the wire segment with its equivalent temperature as T j and RMS current density as J rms, j using Black s Law. In line [6], we calculate the failure rate of the wire segment which is the inverse of its MTTF calculated in line [5]. In line [7], we calculate the probability of failure of the wire segment using the fact that reliability of a wire after N years of operation follows an exponential distribution [1]. In line [8], we calculate the probability of failure of the module from the probability of failure of all wire segments that it contains [3]. In line [9], we check if ProbFail has been invoked with MT T F re f. In line [10], we calculate the probability of failure of the system after N years from the probability of failure of all the modules it contains, when the procedure is invoked with MT T F re f. In line [11], we calculate the overall MTTF of the system from its probability of failure calculated in line [10]. In line [13], we calculate the probability of failure of the system after N years from the probability of failure of all the 3

4 modules it contains, when the procedure is invoked with MT T F red. In line [14], we calculate the overall MTTF of the system from its probability of failure calculated in line [13]. 2.2 Model with MTTF Optimization Table 2 explains the tunable knobs for MTTF and their potential impact. Table 2: MTTF knobs Knob Impact J peak,max Affects J rms,max and J avg,max. Increasing J rms,max will cause increase in temperature due to Joule-heating and exponentially decrease MTTF. Wire Width Increasing wire width decreases J peak,max and wire delay but reduces TDDB. [Any other reliability downsides??] Driver Size Increasing driver size increases J peak,max and reduces gate delay and slew. MTTF Reducing the guardband on lifetime of operation can allow higher J peak,max or reduced wire widths. In this formulation, we minimize MT T F re f such that P red P re f. We cannot reduce switching activity since it is a function of the workload. We cannot reduce T re f since it is a foundry parameter. We can only increase J peak,max by sizing up drivers and reducing wire widths subject to temperature increase due to Joule-heating be T joule,max. One possible Algorithm is shown in 2. Algorithm 2 MTTF Optimization Procedure MTTFOpt [1] For each wire segment, s j, j = 1,..,LM 1 T [2] J peak, j joule,max α 2 F j T h [3] J if peak, j J 1 then peak,max [4] For w red, j = W max, j W min, j [5] Increase Driver size (gate width) until peak current is J peak, j w red, j [6] Perform STA to ensure no hold or setup violations. Go to Step [5] if there is a failure and re-size depending on failure. [7] J peak, j J peak, j w red, j w 0, j [8] MT T F red MT T F re f ( Jpeak,max minj peak, j L j=0 [9] Call Procedure ProbFail with MT T F red [10] if P red P re f then [11] return MT T F red [12] MT T F red MT T F re f [13] return MT T F red ) 2 e Ea B (1/(Tre f +T joule,max ) 1/T re f ) In line [1] of Algorithm 2, we iterate through all the L wire segments across M modules, LM. In line [2], we calculate the peak current density of the wire segment at its switching activity α j and maximum temperature due to Joule-heating as T joule,max. It is assumed that this peak current density is with the wire width after place and route, w 0, j. In line [3], we check if the peak current density calculated in line [2] is greater than foundry peak current density limit. If this is true, then in line [4], we choose an optimized wire width by iterating from the foundry maximum wire width to the foundry minimum wire width. In line [5], we increase the driver size so that the peak current is as close to the product of the peak current density and optimized wire width. In line [6], we perform STA to ensure no timing violations. If there are violations, go back to Step [5] and re-size drivers differently depending on the failure. In line [7], we re-calculate the peak current density of the wire segment based on the optimized value chosen, w red, j. In line [8], we calculate the reduced MTTF value of the system using the minimum peak current density 4

5 across all the wire segments. In line [9], we calculate the probability of failure of the system with the reduced MTTF, P red. In line [10], we check if the reduced probability of failure is less than the reference probability of failure at MT T F re f after N years. In line [12], if the condition in line [9] is true, then return this reduced MTTF. If not, then return the reference MTTF in line [13]. References [1] D. J. Smith, Reliability, Maintainability and Risk 6th edition. Butterworth Heinemann Publishers, Woburn, MA, [2] K. Banerjee and A. Mehrotra, Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets, Proc. ICCAD, 2001, pp [3] E. Karl, D. Blaauw, D. Sylvester and T. Mudge, Reliability Modeling and Management in Dynamic Microprocessor-Based Systems, Proc. DAC, 2006, pp

On Potential Design Impacts of Electromigration Awareness

On Potential Design Impacts of Electromigration Awareness On Potential Design Impacts of Electromigration Awareness Andrew B. Kahng, Siddhartha Nath and Tajana S. Rosing VLSI CAD LABORATORY, UC San Diego UC San Diego / VLSI CAD Laboratory -1- Outline Motivation

More information

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance

More information

Lecture 16: Circuit Pitfalls

Lecture 16: Circuit Pitfalls Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution

More information

System-Level Modeling and Microprocessor Reliability Analysis for Backend Wearout Mechanisms

System-Level Modeling and Microprocessor Reliability Analysis for Backend Wearout Mechanisms System-Level Modeling and Microprocessor Reliability Analysis for Backend Wearout Mechanisms Chang-Chih Chen and Linda Milor School of Electrical and Comptuer Engineering, Georgia Institute of Technology,

More information

Enhancing Multicore Reliability Through Wear Compensation in Online Assignment and Scheduling. Tam Chantem Electrical & Computer Engineering

Enhancing Multicore Reliability Through Wear Compensation in Online Assignment and Scheduling. Tam Chantem Electrical & Computer Engineering Enhancing Multicore Reliability Through Wear Compensation in Online Assignment and Scheduling Tam Chantem Electrical & Computer Engineering High performance Energy efficient Multicore Systems High complexity

More information

Lecture 25. Dealing with Interconnect and Timing. Digital Integrated Circuits Interconnect

Lecture 25. Dealing with Interconnect and Timing. Digital Integrated Circuits Interconnect Lecture 25 Dealing with Interconnect and Timing Administrivia Projects will be graded by next week Project phase 3 will be announced next Tu.» Will be homework-like» Report will be combined poster Today

More information

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 1 Lecture 04: Timing Analysis Static timing analysis STA for sequential circuits

More information

Interconnect Lifetime Prediction for Temperature-Aware Design

Interconnect Lifetime Prediction for Temperature-Aware Design Interconnect Lifetime Prediction for Temperature-Aware Design UNIV. OF VIRGINIA DEPT. OF COMPUTER SCIENCE TECH. REPORT CS-23-2 NOVEMBER 23 Zhijian Lu, Mircea Stan, John Lach, Kevin Skadron Departments

More information

Lecture 16: Circuit Pitfalls

Lecture 16: Circuit Pitfalls Lecture 16: Circuit Pitfalls Outline Variation Noise Budgets Reliability Circuit Pitfalls 2 Variation Process Threshold Channel length Interconnect dimensions Environment Voltage Temperature Aging / Wearout

More information

The Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1 The Wire transmitters receivers schematics physical 2 Interconnect Impact on

More information

CMOS device technology has scaled rapidly for nearly. Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI Interconnects

CMOS device technology has scaled rapidly for nearly. Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI Interconnects IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 6, JUNE 2005 849 Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI Interconnects

More information

Post-Routing Back-End-Of-Line Layout Optimization for Improved Time-Dependent Dielectric Breakdown Reliability

Post-Routing Back-End-Of-Line Layout Optimization for Improved Time-Dependent Dielectric Breakdown Reliability Post-Routing Back-End-Of-Line Layout Optimization for Improved Time-Dependent Dielectric Breakdown Reliability Abstract Tuck-Boon Chan and Andrew B. Kahng ECE and CSE Depts., University of California at

More information

Static Electromigration Analysis for Signal Interconnects

Static Electromigration Analysis for Signal Interconnects Static Electromigration Analysis for Signal Interconnects Chanhee Oh, David Blaauw*, Murat Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta** Motorola, Inc, Austin TX, *University of Michigan,

More information

CSE241 VLSI Digital Circuits Winter Lecture 07: Timing II

CSE241 VLSI Digital Circuits Winter Lecture 07: Timing II CSE241 VLSI Digital Circuits Winter 2003 Lecture 07: Timing II CSE241 L3 ASICs.1 Delay Calculation Cell Fall Cap\Tr 0.05 0.2 0.5 0.01 0.02 0.16 0.30 0.5 2.0 0.04 0.32 0.178 0.08 0.64 0.60 1.20 0.1ns 0.147ns

More information

Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks

Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks Sanjay Pant, David Blaauw Electrical Engineering and Computer Science University of Michigan 1/22 Power supply integrity issues

More information

MODEL MECHANISM OF CMOS DEVICE FOR RELIBILITY ENHANCEMENT

MODEL MECHANISM OF CMOS DEVICE FOR RELIBILITY ENHANCEMENT MODEL MECHANISM OF CMOS DEVICE FOR RELIBILITY ENHANCEMENT Sandeep Lalawat and Prof.Y.S.Thakur lalawat_er2007@yahoo.co.in,ystgecu@yahoo.co.in Abstract This paper present specific device level life time

More information

Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out

Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out Dimitris Bekiaris, Antonis Papanikolaou, Dimitrios Soudris, George Economakos and Kiamal Pekmestzi 1 1 Microprocessors

More information

Interconnect s Role in Deep Submicron. Second class to first class

Interconnect s Role in Deep Submicron. Second class to first class Interconnect s Role in Deep Submicron Dennis Sylvester EE 219 November 3, 1998 Second class to first class Interconnect effects are no longer secondary # of wires # of devices More metal levels RC delay

More information

Circuit Delay Variability Due to Wire Resistance Evolution Under AC Electromigration

Circuit Delay Variability Due to Wire Resistance Evolution Under AC Electromigration Circuit Delay Variability Due to Wire Resistance Evolution Under AC Electromigration Vivek Mishra and Sachin S. Sapatnekar Department of Electrical and Computer Engineering University of Minnesota Minneapolis,

More information

Static Electromigration Analysis for On-Chip Signal Interconnects

Static Electromigration Analysis for On-Chip Signal Interconnects IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 1, JANUARY 2003 39 Static Electromigration Analysis for On-Chip Signal Interconnects David T. Blaauw, Member,

More information

PARADE: PARAmetric Delay Evaluation Under Process Variation *

PARADE: PARAmetric Delay Evaluation Under Process Variation * PARADE: PARAmetric Delay Evaluation Under Process Variation * Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi Dept. of Electrical Engineering Dept. of Computer Science Texas A&M University

More information

Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion

Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion Amir H. Ajami, Kaustav Banerjee *, and Massoud Pedram Dept. of EE-Systems, Univ. of Southern California, os Angeles, CA 99, {aajami,

More information

The Wire EE141. Microelettronica

The Wire EE141. Microelettronica The Wire 1 Interconnect Impact on Chip 2 Example: a Bus Network transmitters receivers schematics physical 3 Wire Models All-inclusive model Capacitance-only 4 Impact of Interconnect Parasitics Interconnect

More information

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 7, JULY

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 7, JULY IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 7, JULY 2006 1273 Statistical Interconnect Metrics for Physical-Design Optimization Kanak Agarwal, Member, IEEE,

More information

Research Challenges and Opportunities. in 3D Integrated Circuits. Jan 30, 2009

Research Challenges and Opportunities. in 3D Integrated Circuits. Jan 30, 2009 Jan 3, 29 Research Challenges and Opportunities in 3D Integrated Circuits Ankur Jain ankur.jain@freescale.com, ankurjain@stanfordalumni.org Freescale Semiconductor, Inc. 28. 1 What is Three-dimensional

More information

Reliability-aware Thermal Management for Hard Real-time Applications on Multi-core Processors

Reliability-aware Thermal Management for Hard Real-time Applications on Multi-core Processors Reliability-aware Thermal Management for Hard Real-time Applications on Multi-core Processors Vinay Hanumaiah Electrical Engineering Department Arizona State University, Tempe, USA Email: vinayh@asu.edu

More information

PARADE: PARAmetric Delay Evaluation Under Process Variation * (Revised Version)

PARADE: PARAmetric Delay Evaluation Under Process Variation * (Revised Version) PARADE: PARAmetric Delay Evaluation Under Process Variation * (Revised Version) Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi Dept. of Electrical Engineering Dept. of Computer Science Texas

More information

Noise and Delay Uncertainty Studies for Coupled RC Interconnects

Noise and Delay Uncertainty Studies for Coupled RC Interconnects Noise and Delay Uncertainty Studies for oupled R Interconnects Andrew B. Kahng, Sudhakar Muddu and Devendra idhani ULA omputer Science Department, Los Angeles, A 995, abk@cs.ucla.edu Silicon Graphics,

More information

RELIABILITY MODELING FOR ULSI INTERCONNECTS HOU YUEJIN

RELIABILITY MODELING FOR ULSI INTERCONNECTS HOU YUEJIN RELIABILITY MODELING FOR ULSI INTERCONNECTS HOU YUEJIN School of Electrical and Electronic Engineering A thesis submitted to the Nanyang Technological University in partial fulfillment of the requirement

More information

CMPEN 411 VLSI Digital Circuits Spring 2012

CMPEN 411 VLSI Digital Circuits Spring 2012 CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

More information

Design for Variability and Signoff Tips

Design for Variability and Signoff Tips Design for Variability and Signoff Tips Alexander Tetelbaum Abelite Design Automation, Walnut Creek, USA alex@abelite-da.com ABSTRACT The paper provides useful design tips and recommendations on how to

More information

Smart Non-Default Routing for Clock Power Reduction

Smart Non-Default Routing for Clock Power Reduction Smart Non-Default Routing for Clock Power Reduction Andrew B. Kahng, Seokhyeong Kang and Hyein Lee ECE and CSE Departments, University of California at San Diego abk@ucsd.edu, shkang@vlsicad.ucsd.edu,

More information

Fast Buffer Insertion Considering Process Variation

Fast Buffer Insertion Considering Process Variation Fast Buffer Insertion Considering Process Variation Jinjun Xiong, Lei He EE Department University of California, Los Angeles Sponsors: NSF, UC MICRO, Actel, Mindspeed Agenda Introduction and motivation

More information

Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED

Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www.analog.com www.hittite.com Report Title: Report Type: Date: Qualification Test Report See Attached

More information

Semiconductor Reliability

Semiconductor Reliability Semiconductor Reliability. Semiconductor Device Failure Region Below figure shows the time-dependent change in the semiconductor device failure rate. Discussions on failure rate change in time often classify

More information

Luis Manuel Santana Gallego 31 Investigation and simulation of the clock skew in modern integrated circuits

Luis Manuel Santana Gallego 31 Investigation and simulation of the clock skew in modern integrated circuits Luis Manuel Santana Gallego 31 Investigation and simulation of the clock skew in modern egrated circuits 3. Clock skew 3.1. Definitions For two sequentially adjacent registers, as shown in figure.1, C

More information

Physics-Based Full-Chip TDDB Assessment for BEOL Interconnects

Physics-Based Full-Chip TDDB Assessment for BEOL Interconnects Physics-Based Full-Chip TDDB Assessment for BEOL Interconnects Xin Huang, Valeriy Sukharev, Zhongdong Qi, Taeyoung Kim, and Sheldon X.-D. Tan Department of Electrical Engineering, University of California,

More information

Thermal-reliable 3D Clock-tree Synthesis Considering Nonlinear Electrical-thermal-coupled TSV Model

Thermal-reliable 3D Clock-tree Synthesis Considering Nonlinear Electrical-thermal-coupled TSV Model Thermal-reliable 3D Clock-tree Synthesis Considering Nonlinear Electrical-thermal-coupled TSV Model Yang Shang 1, Chun Zhang 1, Hao Yu 1, Chuan Seng Tan 1, Xin Zhao 2, Sung Kyu Lim 2 1 School of Electrical

More information

10/16/2008 GMU, ECE 680 Physical VLSI Design

10/16/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter VI Coping with Interconnect 1 Impact of Interconnect Parasitics Reduce Robustness Affect Performance Increase delay Increase power dissipation Classes of Parasitics

More information

Static Timing Analysis Considering Power Supply Variations

Static Timing Analysis Considering Power Supply Variations Static Timing Analysis Considering Power Supply Variations Sanay Pant, David Blaauw University of Michigan, Ann Arbor, MI Abstract Power supply integrity verification has become a key concern in high performance

More information

ET 162 Circuit Analysis. Current and Voltage. Electrical and Telecommunication Engineering Technology. Professor Jang

ET 162 Circuit Analysis. Current and Voltage. Electrical and Telecommunication Engineering Technology. Professor Jang ET 162 Circuit Analysis Current and Voltage Electrical and Telecommunication Engineering Technology Professor Jang Acknowledgement I want to express my gratitude to Prentice Hall giving me the permission

More information

EE141-Spring 2007 Digital Integrated Circuits. Administrative Stuff. Last Lecture. Wires. Interconnect Impact on Chip. The Wire

EE141-Spring 2007 Digital Integrated Circuits. Administrative Stuff. Last Lecture. Wires. Interconnect Impact on Chip. The Wire EE141-Spring 2007 Digital Integrated Circuits ecture 10 Administrative Stuff No ab this week Midterm 1 on Tu! HW5 to be posted by next Friday Due Fr. March 2 5pm Introduction to wires 1 2 ast ecture ast

More information

Buffer Insertion for Noise and Delay Optimization

Buffer Insertion for Noise and Delay Optimization Buffer Insertion for Noise and Delay Optimization Charles J Alpert IBM Austin esearch Laoratory Austin, TX 78660 alpert@austinimcom Anirudh Devgan IBM Austin esearch Laoratory Austin, TX 78660 devgan@austinimcom

More information

EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis

EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top

More information

Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.

Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC. Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact

More information

Optimal Reliability-Constrained Overdrive Frequency Selection In Multicore Systems

Optimal Reliability-Constrained Overdrive Frequency Selection In Multicore Systems Optimal Reliability-Constrained Overdrive Frequency Selection In Multicore Systems Andrew B. Kahng and Siddhartha Nath CSE and ECE Departments, University of California at San Diego, USA {abk, sinath}@ucsd.edu

More information

Lecture #39. Transistor Scaling

Lecture #39. Transistor Scaling Lecture #39 ANNOUNCEMENT Pick up graded HW assignments and exams (78 Cory) Lecture #40 will be the last formal lecture. Class on Friday will be dedicated to a course review (with sample problems). Discussion

More information

Buffered Clock Tree Sizing for Skew Minimization under Power and Thermal Budgets

Buffered Clock Tree Sizing for Skew Minimization under Power and Thermal Budgets Buffered Clock Tree Sizing for Skew Minimization under Power and Thermal Budgets Krit Athikulwongse, Xin Zhao, and Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology

More information

Chapter 6. a. Open Circuit. Only if both resistors fail open-circuit, i.e. they are in parallel.

Chapter 6. a. Open Circuit. Only if both resistors fail open-circuit, i.e. they are in parallel. Chapter 6 1. a. Section 6.1. b. Section 6.3, see also Section 6.2. c. Predictions based on most published sources of reliability data tend to underestimate the reliability that is achievable, given that

More information

Introduction. HFSS 3D EM Analysis S-parameter. Q3D R/L/C/G Extraction Model. magnitude [db] Frequency [GHz] S11 S21 -30

Introduction. HFSS 3D EM Analysis S-parameter. Q3D R/L/C/G Extraction Model. magnitude [db] Frequency [GHz] S11 S21 -30 ANSOFT Q3D TRANING Introduction HFSS 3D EM Analysis S-parameter Q3D R/L/C/G Extraction Model 0-5 -10 magnitude [db] -15-20 -25-30 S11 S21-35 0 1 2 3 4 5 6 7 8 9 10 Frequency [GHz] Quasi-static or full-wave

More information

An Efficient Transient Thermal Simulation Methodology for Power Management IC Designs

An Efficient Transient Thermal Simulation Methodology for Power Management IC Designs An Efficient Transient Thermal Simulation Methodology for Power Management IC Designs Karthik Srinivasan, Stephen Pan, Zhigang Feng, Norman Chang, Tim Pawlak ANSYS Inc., 2645 Zanker Road, San Jose, CA-95134,

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay

More information

TAU 2014 Contest Pessimism Removal of Timing Analysis v1.6 December 11 th,

TAU 2014 Contest Pessimism Removal of Timing Analysis v1.6 December 11 th, TU 2014 Contest Pessimism Removal of Timing nalysis v1.6 ecember 11 th, 2013 https://sites.google.com/site/taucontest2014 1 Introduction This document outlines the concepts and implementation details necessary

More information

PRODUCT RELIABILITY REPORT FOR

PRODUCT RELIABILITY REPORT FOR 2/11/2015 PRODUCT RELIABILITY REPORT FOR DS2432 Rev C2 Maxim Integrated 14460 Maxim Dr. Dallas, TX 75244 Approved by: Sokhom Chum MTS, Reliability Engineering Conclusion: The following qualification successfully

More information

Announcements. EE141- Fall 2002 Lecture 25. Interconnect Effects I/O, Power Distribution

Announcements. EE141- Fall 2002 Lecture 25. Interconnect Effects I/O, Power Distribution - Fall 2002 Lecture 25 Interconnect Effects I/O, Power Distribution Announcements Homework 9 due next Tuesday Hardware lab this week Project phase 2 due in two weeks 1 Today s Lecture Impact of interconnects»

More information

EE 330 Lecture 3. Basic Concepts. Feature Sizes, Manufacturing Costs, and Yield

EE 330 Lecture 3. Basic Concepts. Feature Sizes, Manufacturing Costs, and Yield EE 330 Lecture 3 Basic Concepts Feature Sizes, Manufacturing Costs, and Yield Review from Last Time Analog Flow VLSI Design Flow Summary System Description Circuit Design (Schematic) SPICE Simulation Simulation

More information

DS1210, Rev C1. Dallas Semiconductor

DS1210, Rev C1. Dallas Semiconductor 3/19/23 RELIABILITY REPORT FOR DS121, Rev C1 Dallas Semiconductor 441 South Beltwood Parkway Dallas, TX 75244-3292 Prepared by: Ken Wendel Reliability Engineering Manager Dallas Semiconductor 441 South

More information

Lecture: Workload Models (Advanced Topic)

Lecture: Workload Models (Advanced Topic) Lecture: Workload Models (Advanced Topic) Real-Time Systems, HT11 Martin Stigge 28. September 2011 Martin Stigge Workload Models 28. September 2011 1 System

More information

Through Silicon Via-Based Grid for Thermal Control in 3D Chips

Through Silicon Via-Based Grid for Thermal Control in 3D Chips Through Silicon Via-Based Grid for Thermal Control in 3D Chips José L. Ayala 1, Arvind Sridhar 2, Vinod Pangracious 2, David Atienza 2, and Yusuf Leblebici 3 1 Dept. of Computer Architecture and Systems

More information

Chapter 8. Low-Power VLSI Design Methodology

Chapter 8. Low-Power VLSI Design Methodology VLSI Design hapter 8 Low-Power VLSI Design Methodology Jin-Fu Li hapter 8 Low-Power VLSI Design Methodology Introduction Low-Power Gate-Level Design Low-Power Architecture-Level Design Algorithmic-Level

More information

TRADITIONAL stress-based reliability qualification techniques,

TRADITIONAL stress-based reliability qualification techniques, 476 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 4, APRIL 2008 Multi-Mechanism Reliability Modeling and Management in Dynamic Systems Eric Karl, Student Member, IEEE,

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance,

More information

Analysis of Temporal and Spatial Temperature Gradients for IC Reliability

Analysis of Temporal and Spatial Temperature Gradients for IC Reliability 1 Analysis of Temporal and Spatial Temperature Gradients for IC Reliability UNIV. OF VIRGINIA DEPT. OF COMPUTER SCIENCE TECH. REPORT CS-24-8 MARCH 24 Zhijian Lu, Wei Huang, Shougata Ghosh, John Lach, Mircea

More information

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large

More information

Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations

Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations Chinese Journal of Electronics Vol.4, No.1, Jan. 015 Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations LI Jianwei 1,,DONGGang 3, WANG Zeng 4 and YE Xiaochun (1.Faculty

More information

Adding a New Dimension to Physical Design. Sachin Sapatnekar University of Minnesota

Adding a New Dimension to Physical Design. Sachin Sapatnekar University of Minnesota Adding a New Dimension to Physical Design Sachin Sapatnekar University of Minnesota 1 Outline What is 3D about? Why 3D? 3D-specific challenges 3D analysis and optimization 2 Planning a city: Land usage

More information

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder R. W. Erickson Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder 15.3.2 Example 2 Multiple-Output Full-Bridge Buck Converter Q 1 D 1 Q 3 D 3 + T 1 : : n 2 D 5 i

More information

Modeling and optimization of noise coupling in TSV-based 3D ICs

Modeling and optimization of noise coupling in TSV-based 3D ICs LETTER IEICE Electronics Express, Vol.11, No.20, 1 7 Modeling and optimization of noise coupling in TSV-based 3D ICs Yingbo Zhao, Yintang Yang, and Gang Dong a) School of Microelectronics, Xidian University,

More information

Skew Management of NBTI Impacted Gated Clock Trees

Skew Management of NBTI Impacted Gated Clock Trees International Symposium on Physical Design 2010 Skew Management of NBTI Impacted Gated Clock Trees Ashutosh Chakraborty and David Z. Pan ECE Department, University of Texas at Austin ashutosh@cerc.utexas.edu

More information

Skew Management of NBTI Impacted Gated Clock Trees

Skew Management of NBTI Impacted Gated Clock Trees Skew Management of NBTI Impacted Gated Clock Trees Ashutosh Chakraborty ECE Department The University of Texas at Austin Austin, TX 78703, USA ashutosh@cerc.utexas.edu David Z. Pan ECE Department The University

More information

An Automated Approach for Evaluating Spatial Correlation in Mixed Signal Designs Using Synopsys HSpice

An Automated Approach for Evaluating Spatial Correlation in Mixed Signal Designs Using Synopsys HSpice Spatial Correlation in Mixed Signal Designs Using Synopsys HSpice Omid Kavehei, Said F. Al-Sarawi, Derek Abbott School of Electrical and Electronic Engineering The University of Adelaide Adelaide, SA 5005,

More information

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

Coulomb s constant k = 9x10 9 N m 2 /C 2

Coulomb s constant k = 9x10 9 N m 2 /C 2 1 Part 2: Electric Potential 2.1: Potential (Voltage) & Potential Energy q 2 Potential Energy of Point Charges Symbol U mks units [Joules = J] q 1 r Two point charges share an electric potential energy

More information

Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion

Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion Youngmin Kim a, Dusan Petranovic b, Dennis Sylvester a a EECS, University of Michigan b Mentor Graphics 1 Outline Introduction

More information

Elementary Process of Electromigration at Metallic Nanojunctions in the Ballistic Regime

Elementary Process of Electromigration at Metallic Nanojunctions in the Ballistic Regime Elementary Process of Electromigration at Metallic Nanojunctions in the Ballistic Regime Kaz Hirakawa Institute of Industrial Science, University of Tokyo CREST, JST collaborators: Akinori Umeno, Kenji

More information

Assessment of Current Density Singularity in Electromigration of Solder Bumps

Assessment of Current Density Singularity in Electromigration of Solder Bumps Assessment of Current Density Singularity in Electromigration of Solder Bumps Pridhvi Dandu and Xuejun Fan Department of Mechanical Engineering Lamar University PO Box 10028, Beaumont, TX 77710, USA Tel:

More information

Real-Time Course. Clock synchronization. June Peter van der TU/e Computer Science, System Architecture and Networking

Real-Time Course. Clock synchronization. June Peter van der TU/e Computer Science, System Architecture and Networking Real-Time Course Clock synchronization 1 Clocks Processor p has monotonically increasing clock function C p (t) Clock has drift rate For t1 and t2, with t2 > t1 (1-ρ)(t2-t1)

More information

AOS Semiconductor Product Reliability Report

AOS Semiconductor Product Reliability Report AOS Semiconductor Product Reliability Report AO4466/AO4466L, rev B Plastic Encapsulated Device ALPHA & OMEGA Semiconductor, Inc 49 Mercury Drive Sunnyvale, CA 948 U.S. Tel: (48) 83-9742 www.aosmd.com Jun

More information

Reliability Datasheet

Reliability Datasheet HLMP-LG70/71,HLMP-LB71 HLMP-LM71 4 mm Oval Precision Optical Performance LED Reliability Datasheet Description The following cumulative test results have been ob tained from testing performed at Avago

More information

AOS Semiconductor Product Reliability Report

AOS Semiconductor Product Reliability Report AOS Semiconductor Product Reliability Report AO64/AO64L, rev C Plastic Encapsulated Device ALPHA & OMEGA Semiconductor, Inc 49 Mercury Drive Sunnyvale, CA 948 U.S. Tel: (48) 83-9742 www.aosmd.com Mar 8,

More information

Aerospace Performances of IPDiA -250 C up to 250 C Grade Silicon Capacitors

Aerospace Performances of IPDiA -250 C up to 250 C Grade Silicon Capacitors Aerospace Performances of IPDiA -250 C up to 250 C Grade Silicon Capacitors Laurent Lengignon, IPDiA, 2 rue de la Girafe, 14000 Caen, France Alter Technology, Madrid, Spain, Demetrio Lopez ESA/ESTEC, Noordwijk,

More information

Variation-aware Clock Network Design Methodology for Ultra-Low Voltage (ULV) Circuits

Variation-aware Clock Network Design Methodology for Ultra-Low Voltage (ULV) Circuits Variation-aware Clock Network Design Methodology for Ultra-Low Voltage (ULV) Circuits Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, and Sung Kyu Lim School of ECE, Georgia Institute of Technology,

More information

IN the past, circuit delay has been due mostly to transistors.

IN the past, circuit delay has been due mostly to transistors. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998 449 Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and Three-Dimensional

More information

EE 330 Lecture 3. Basic Concepts. Feature Sizes, Manufacturing Costs, and Yield

EE 330 Lecture 3. Basic Concepts. Feature Sizes, Manufacturing Costs, and Yield EE 330 Lecture 3 Basic Concepts Feature Sizes, Manufacturing Costs, and Yield Review from Last Time Analog Flow VLSI Design Flow Summary System Description Circuit Design (Schematic) SPICE Simulation Simulation

More information

Problems in VLSI design

Problems in VLSI design Problems in VLSI design wire and transistor sizing signal delay in RC circuits transistor and wire sizing Elmore delay minimization via GP dominant time constant minimization via SDP placement problems

More information

Making Fast Buffer Insertion Even Faster via Approximation Techniques

Making Fast Buffer Insertion Even Faster via Approximation Techniques Making Fast Buffer Insertion Even Faster via Approximation Techniques Zhuo Li, C. N. Sze, Jiang Hu and Weiping Shi Department of Electrical Engineering Texas A&M University Charles J. Alpert IBM Austin

More information

Effects of electrical, thermal and thermal gradient stress on reliability of metal interconnects

Effects of electrical, thermal and thermal gradient stress on reliability of metal interconnects Graduate Theses and Dissertations Graduate College 2014 Effects of electrical, thermal and thermal gradient stress on reliability of metal interconnects Srijita Patra Iowa State University Follow this

More information

White Paper. Temperature Dependence of Electrical Overstress By Craig Hillman, PhD

White Paper. Temperature Dependence of Electrical Overstress By Craig Hillman, PhD White Paper Temperature Dependence of Electrical Overstress By Craig Hillman, PhD 1. What is Electrical Overstress (EOS)? Electrical overstress is typically defined as an over voltage or over current event

More information

Alternating Currents. The power is transmitted from a power house on high voltage ac because (a) Electric current travels faster at higher volts (b) It is more economical due to less power wastage (c)

More information

Backend Low-k TDDB Chip Reliability Simulator

Backend Low-k TDDB Chip Reliability Simulator Backend Low-k TDDB Chip Reliability Simulator Muhammad Bashir, Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim and Linda Milor School of Electrical and Computer Engineering Georgia Institute of Technology

More information

A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC constraints

A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC constraints A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC constraints Ashish Hari, Sulabh Kumar Khare Accellera Systems Initiative 1 Agenda SOC implementation challenge with CDC paths

More information

SOLIDWORKS Simulation Time Based Thermal Stress

SOLIDWORKS Simulation Time Based Thermal Stress SOLIDWORKS Simulation Time Based Thermal Stress Overview Given that SOLIDWORKS Simulation is capable of running a transient thermal analysis on models it leads to the question of whether the transient

More information

Time Depending Dielectric Breakdown. NVM Endurance, Data Retention, and. Negative Bias Temperature Instability. Human Body Model / Machine Model

Time Depending Dielectric Breakdown. NVM Endurance, Data Retention, and. Negative Bias Temperature Instability. Human Body Model / Machine Model For integrated circuits or discrete semiconductors select below: Mark change with an "x" Amkor-Kr to ASECL Assembly Transfer with Cu wire bonds Assessment of impact on Supply Chain regarding following

More information

Vt Variation Effects on

Vt Variation Effects on Vt Variation Effects on Lifetime eliability Smruti. Sarangi Josep Torrellas University of Illinois at Urbana-Champaign Motivation Chips are wearing out faster as technology scales >>180nm: 20 year design

More information

THE UNIVERSITY OF MICHIGAN. Faster Static Timing Analysis via Bus Compression

THE UNIVERSITY OF MICHIGAN. Faster Static Timing Analysis via Bus Compression Faster Static Timing Analysis via Bus Compression by David Van Campenhout and Trevor Mudge CSE-TR-285-96 THE UNIVERSITY OF MICHIGAN Computer Science and Engineering Division Department of Electrical Engineering

More information

Power Consumption in CMOS CONCORDIA VLSI DESIGN LAB

Power Consumption in CMOS CONCORDIA VLSI DESIGN LAB Power Consumption in CMOS 1 Power Dissipation in CMOS Two Components contribute to the power dissipation:» Static Power Dissipation Leakage current Sub-threshold current» Dynamic Power Dissipation Short

More information

Tradeoff between Reliability and Power Management

Tradeoff between Reliability and Power Management Tradeoff between Reliability and Power Management 9/1/2005 FORGE Lee, Kyoungwoo Contents 1. Overview of relationship between reliability and power management 2. Dakai Zhu, Rami Melhem and Daniel Moss e,

More information

CSE493/593. Designing for Low Power

CSE493/593. Designing for Low Power CSE493/593 Designing for Low Power Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.].1 Why Power Matters Packaging costs Power supply rail design Chip and system

More information

Lecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects

Lecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects Lecture 5 MOS Inverter: Switching Characteristics and Interconnection Effects Introduction C load = (C gd,n + C gd,p + C db,n + C db,p ) + (C int + C g ) Lumped linear capacitance intrinsic cap. extrinsic

More information

TAU 2015 Contest Incremental Timing Analysis and Incremental Common Path Pessimism Removal (CPPR) Contest Education. v1.9 January 19 th, 2015

TAU 2015 Contest Incremental Timing Analysis and Incremental Common Path Pessimism Removal (CPPR) Contest Education. v1.9 January 19 th, 2015 TU 2015 Contest Incremental Timing nalysis and Incremental Common Path Pessimism Removal CPPR Contest Education v1.9 January 19 th, 2015 https://sites.google.com/site/taucontest2015 Contents 1 Introduction

More information