Polarization Induced 2DEG in AlGaN/GaN HEMTs: On the origin, DC and transient characterization. Ramakrishna Vetury. Committee

Transcription

1 Polarization Induced 2DEG in AlGaN/GaN HEMTs: On the origin, DC and transient characterization by Ramakrishna Vetury Committee Dr. James Ibbetson Prof. Evelyn Hu Prof. Robert York Prof. Umesh Mishra

2 Acknowledgements Professors Umesh Mishra, Robert York, Evelyn Hu, Dr. James Ibbetson Prof. Steve DenBaars, Prof. Jim Speck Mishra and York Groups: Lee, Peter, James, Gia, Naiqain, Dr. Wu, Ching Hui, Primit, Prashant, Rob U, Rob C, Dan, DJ, Anand, Sten, Tim, Can, Likun, Huili, Ilan, Dario.. Amit, Jane, Vicki, Bruce, Paolo, PC Jia, Erich, Troy, Pete, Padmini, Thai, Jim.. Dr. Stacia Keller, Dr.Yulia Smorchkova Naiqain Zhang, Darron Young, Chris Elsass, Ben Heying, Hugues Marchand, Paul Fini, Dave Kapolnek Bob Hill and Jack Whaley and everybody in the clean room UCSB Nitride Community Cathy and Lee Anil, Minu, Sri, Doli, Smitha, Karthik, Shri, Otto Sridevi & Rohit Joshi ONR AFOSR

3 Outline 1. Non-Idealities in GaN HEMTs, traps in GaN buffer, AlGaN dislocations 2. The free surface of AlGaN Surface potential, Polarization, Origin of 2DEG 3. Current Collapse Virtual gate, Transient characterization, Passivation

4 What makes a good GaN HEMT? S G AlGaN n s --- GaN Buffer D I DS A Q Bias Point I MAX Substrate B V DS V KNEE V BREAKDOWN Max Power = I MAX. (V BREAKDOWN V KNEE ) 8 Obtaining power from the device. Biasing and load line for maximum power output

5 What makes a good GaN HEMT? I DS A Q BIAS POINT I MAX S G AlGaN n s --- GaN Buffer D B Substrate V KNEE V DS V BREAKDOWN Maximize I Maximize n s, µ I MAX α n s. µ Maximize n s Maximize P SP, P PE Maximize Al mole fraction without strain relaxation Maximize f τ Minimize effective gate length, Minimize L g and gate length extension Maximize µ Minimize dislocations, smooth interface

6 Non Idealities in GaN HEMTs Choose the high power RF device ma/mm 2V/div Predicted Output Power (W/mm/ V DS bias) 3.15 / / / /20

7 Non Idealities in GaN HEMTs Choose the high power RF device ma/mm 2V/div Predicted Output Power (W/mm/ V DS bias) 3.15 / / / /20 Measured Output Power (W/mm/ V DS bias) 1.06 / / / /20 What limits output power?

8 Non Idealities in GaN HEMTs I d (5 ma/div) DC Dispersion AC Load line Maximum Output Power decreases, as voltage swing and current swing reduce Drain efficiency decreases as knee voltage increases DE = (V max -V knee )/(V knee +V max ) Power added efficiency V ds (V) Due to the trapping effect, V AC increased from 5 V to 12 V. PAE=(1-1/G)DE

9 Non Idealities in GaN HEMTs V GS V on V DS Vp TIME The sequence of biases used to obtain a pulsed I-V curve from the Tektronix curve tracer. The drain current is sampled during each gate pulse. This biasing sequence is used to obtain the lighter pulsed (AC) I-V curves shown previously

10 Non Idealities in GaN HEMTs A I MAX I DS Bias Point I DS Q B V K1 V DS V KNEE (a) V BREAKDOWN

11 Non Idealities in GaN HEMTs A I MAX I MAX 2 < I MAX1 V K2 > V K1 I DS Bias Point I DS I MAX 2 Q B V K1 V DS V K2 V DS V KNEE (a) V BREAKDOWN (b) The consequence of trapping effects: the device I-V characteristic changes from (a) (b).

12 Non Idealities in GaN HEMTs Where can the traps be? ϕ S ~ 200 Å 2-3 µm Al x Ga 1-x N GaN 2DEG 1. S.I. Substrate (if SiC) 2. Substrate-GaN buffer interface 3. S.I. GaN buffer 4. AlGaN bulk 5. Free surface of AlGaN Sapphire/ S.I.SiC E C Possible trapping sites Deep level Fermi level

13 Source of the Buffer Traps GaN NOMINALLY UNDOPED GaN IS n-type (~1x10 16 cm -3 ) Sapphire/SiC/Si S G D For a 1 µm Thick Buffer AlGaN GaN n s --- Substrate n Buffer Buffer Conduction n Buffer ~ cm -3 x 10-4 cm = cm -2 n Channel I Buffer I Channel ~ n S ~ cm -2 ~ 10% (Unacceptable) HIGH RESISTIVITY BUFFER IS ACHIEVED THROUGH COMPENSATION SOURCE OF TRAPS

14 Non Idealities in GaN HEMTs Making a S.I.Buffer - Compensation Fermi Level (ev) N D = cm -3 E C N D N AA N AA Deep Acceptor Concentration E V Electron Concentration Conduction Band (cm -3 )

15 Non Idealities in GaN HEMTs Making a S.I.Buffer - Compensation Fermi Level (ev) N D = cm -3 E C N D N AA 0 N AA Deep Acceptor Concentration E V #of Empty Acceptors (fraction) 0 N AA N AA Strategy Minimize Background Donors

16 Non Idealities in GaN HEMTs Making a S.I.Buffer Background donors V N, O From: Compensating centers Carbon, Dislocation related deep levels water vapor, Ambient (loading, leaks) impurities in gases used, NH 3, precursors Sapphire substrate Fine tune growth conditions to Minimize background donors Minimum necessary concentration of compensating centers Optimize S G AlGaN n s GaN --- Buffer Substrate D

17 Non Idealities in GaN HEMTs High quality AlGaN Maximize I Maximize n s, µ Maximize n s Maximize f τ Maximize µ Maximize P SP, P PE Maximize Al mole fraction without strain relaxation Minimize effective gate length, Minimize L g and gate length extension Minimize dislocations, smooth interface Optimized AlGaN growth high Al % high structural quality minimum unintentional defect incorporation Optimize S G AlGaN n s --- GaN Buffer Substrate D

18 Non Idealities in GaN HEMTs Impact of Dislocations on Current Collapse S G AlGaN n s --- GaN Buffer D I d (5 ma/div) DC Dispersion AC Load line Substrate V ds (V) Optimized : GaN buffer, AlGaN layer Question : Are dislocations the dominant source of deep levels causing current collapse?

19 Non Idealities in GaN HEMTs Impact of Dislocations on Current Collapse Dislocations propagate vertically in seed GaN LEO is dislocation free SiO 2 (a) (b) HFET on regular GaN (c) HFET on LEO GaN AlGaN (d) (e) LEO FETs Growth technique

20 Non Idealities in GaN HEMTs 2 µm 3 nm(c) Dislocation mediated structural defects on Al 0.3 Ga 0.7 N on regular GaN Dislocation density reduced from to < 10 6 in LEO GaN

21 Non Idealities in GaN HEMTs 2 µm 3 nm(c) Dislocation mediated structural defects absent in Al 0.3 Ga 0.7 N on LEO GaN

22 Non Idealities in GaN HEMTs HFETs on LEO and regular GaN Pulsed Measurement on LEO device DC AC HFETs on LEO and regular GaN showed similar DC I-V characteristics Typical max I DS ~ 250 ma/mm, max g m ~ 60 ms/mm. Pulsed measurement on HFETs on LEO GaN showed significant current collapse Dislocations are not the primary source of current collapse

23 Non Idealities in GaN HEMTs The story so far S G AlGaN n s GaN --- Buffer Substrate D After.. Optimized GaN buffer Optimized AlGaN layer Dislocations are not the primary source ~ 200 Å Al x Ga 1-x N Substrate interface too far away 2-3 µm GaN Trapping effects still present Sapphire/ S.I.SiC Is AlGaN surface important?

24 Non Idealities in GaN HEMTs The story so far S G AlGaN n s GaN --- Buffer Substrate D Power W/mm UCSB on Al 2 O 3 x Al > 0.3 X improved AlGaN 0 thick S.I. GaN buffer ~ 200 Å Al x Ga 1-x N time 2-3 µm GaN Hitherto undiscussed improvement to surface AlGaN surface is important! Sapphire/ S.I.SiC

25 The free AlGaN surface Measurement of surface potential - indicates existence of surface states Why should surface states exist? Polarization effects Surface states give rise to 2DEG Surface states also give current collapse - passivation

26 The free AlGaN surface Measurement of surface potential Experiment L G L FG L 1 L 2 undoped Al x Ga 1-x N 200 Å S G FG D Al x Ga 1-x N undoped i-gan 2 µm GaN Sapphire Substrate Device Layer Structure Device Layout

27 The free AlGaN surface Floating gate voltage scan V FG D 0 Measurement of surface potential V GD V T V GD G S V FG Regime 1 [ V GD < V T ] Regime 2 [ V GD > V T ] V T E X y=0 E X y=0 V GD S G FG D S G FG D Regime 1 [ V GD < V T ] Regime 2 [ V GD > V T ]

28 The free AlGaN surface Measurement of surface potential Clamping of Peak Electric Field V T 1000 D1025vfg 100 E X y= L 1 S G FG D 600 I G V FG Regime 2 [ V GD > V T ] V DG 0 I G limited Peak Electric Field at gate edge is clamped

29 The free AlGaN surface Measurement of surface potential E X y=0 V T 0 Floating gate voltage scan L 1a < L 1b < L 1c S G FG D Regime 2 [ V GD > V T ] L V T increases with L 1 V FG (V) a V GD (V) V T dependence on L 1 tells us the how the depletion region extends with gate-drain reverse bias b a) 0.5 µm b)1.5 µm c) 1.7 µm c

30 The free AlGaN surface Measurement of surface potential Lateral extent of depletion region S G D V T (V) Measured Simulated L 1 (µm) S G Negative charge on surface D Measurements show that Average E limited Large extension of depletion region Negative charge on surface extends depletion region

31 The free AlGaN surface What can the free AlGaN surface look like? Energy E E E E C E C E C E C Donor Acceptor Donor Donor E V E V E V E V Density of States DOS DOS DOS BUT Strongly ionic semiconductors should not have surface states.. (Kurtin et. al.) Ga-N and Al-N bonds have strong ionic character (Ga, Al strongly electro +ve, N - strongly electro ve)

32 The free AlGaN surface Influence of Polarization Wurtzite group lacks inversion symmetry in c plane (0001 ) Spontaneous polarization coefficient is large Presence of polarization dipole and electric field in an unstrained crystal (0001) Wurtzite lattice group

33 The free AlGaN surface Large lattice mismatch between GaN, AlN, InN Influence of Polarization Piezo-electric polarization coefficient is large Presence of piezoelectric polarization dipole and electric field in a strained crystal

34 The free AlGaN surface Influence of Polarization Crystal structure of GaN Difference in spontaneous polarization coefficients Lattice mismatch Between GaN and AlGaN Spontaneous Polarization Induced Charge Sheet in AlGaN For Ga-face crystal the two sheets add up Piezolectric Polarization Induced Charge Sheets in AlGaN Built in Sheet Charge and Electric fields in an AlGaN/GaN heterostructure AlGaN GaN Ga-face crystal

35 The free AlGaN surface Influence of Polarization Origin of Charge S G D Al x Ga 1-x N -σ Pol E F σ channel +σ Pol GaN Hall measurements on undoped AlGaN/GaN structures show that there exists a 2DEG at the AlGaN/GaN interface

36 The free AlGaN surface Influence of Polarization Origin of Charge S G D σ Pol +σ Metal? E F Al x Ga 1-x N d -σ channel +σ Pol GaN A metal (gate) can provide positive charge to satisfy charge neutrality. What happens when the surface is free? As in the access regions

37 The free AlGaN surface 2DEG formation - (1) Ideal Surface Presence of polarization charge is not sufficient for 2DEG to form Built-in field due to Unscreened dipole 2DEG d < d CR d > d CR + σ Pol + σ Holes Reduced field E=(σ PZ qn s )/ε + σ Pol - σ Pol - σ Pol - σ 2DEG In the absence of any donors, 2DEG electrons must come from the VB Critical thickness depends on bandgap Polarization is not directly responsible for the 2DEG at AlGaN/GaN interface

38 The free AlGaN surface 2DEG formation - (2) Surface Donors Presence of polarization charge is not sufficient for 2DEG to form Built-in field due to Unscreened dipole Partially filled surface donors 2DEG d < d CR Reduced field E=(σ PZ qn s )/ε d > d CR + σ Pol + σ Surface donor + σ Pol - σ Pol - σ Pol - σ 2DEG No 2DEG until the surface donors can empty into the GaN Critical thickness depends on donor level, fermi level in notch n s depends on the AlGaN thickness, surface donor level, polarization dipole

39 The free AlGaN surface Simulated 2DEG charge density Sheet charge (#/cm 2 ) AlGaN thickness (Angstroms) Surface Barrier ( ev) ϕ S E c q.n s = σ Pol.(1-d CR /d) - ε E fo /d + N d d/2 q.n s = σ Pol.(1-d CR /d) d CR d E fo d CR = ε.(q.ϕ S - E c )/σ Pol

40 The free AlGaN surface AlGaN/GaN Heterostructures by MBE Sheet carrier density N S (10 12 cm -2 ) (a) vs AlGaN barrier width x = 0.27 T = 13 K AlGaN thickness d (nm) Sheet carrier density N S (10 12 cm -2 ) (b) vs Al content d = 31 nm T = 13 K Alloy composition x theoretically calculated N S assuming surface barrier height qφ B = 1.42 ev theoretically calculated N S assuming eφ B = 1.42 ev for all x least square linear fit, dn S /dx = 5.45x10 13 cm -2

41 The free AlGaN surface Measurement of surface potential - indicates existence of surface states Why should surface states exist? Polarization effects Surface states give rise to 2DEG Surface states also give current collapse - passivation

42 Current Collapse Concept of Virtual Gate Q. How can traps affect device characteristics? Directly trapping electrons in the channel i.e depleting the 2DEG density (collapse should not be affected by surface treatment) OR Trapping charge elsewhere, creating a potential barrier to current flow (a virtual gate, spatially distinct from the metal gate) OR Trapping charge underneath the metal gate, effectively changing the gate bias. (pinch-off voltage changes, collapse should not depend on surface treatment) ( V P =q. n s / C AlGaN )

43 Current Collapse Effect of Surface Traps Polarization Dipole is Charge Neutral Surface Donors 2 DEG E F S G D Electrons can be injected from the gate into the very donor states that provide channel electrons.

44 Current Collapse Concept of Virtual Gate Virtual Gate e AlGaN GaN V VG V G Drain Source X V G Drain R Source Extended depletion region V VG controls the drain current What is V VG, the potential on the virtual gate? Time constants to charge/discharge the virtual gate

45 Current Collapse Potential of Virtual Gate A Drain I DS Q Increasing trap occupancy, V VG more reverse biased V VG B V G Source V DS Trend of increasing reverse bias or increasing trap occupancy on the I-V plane of the device On the load line, V VG is most negative at B and least negative at A. Metal gate can decrease I DS, but not increase I DS

46 Current Collapse Time constants of Virtual Gate Negative virtual gate Occupancy of surface traps OR Reverse bias on V VG f 1 f 2 f 3 No virtual gate time Fully Open Channel f 3 > f 2 > f 1 Drain Current Channel does not fully open. time average (DC) drain current Pinch Off time Time constant of interest T DETRAP

47 Current Collapse Frequency dependence of Maximum drain current I MAX I DS I MAX? Ideal device Dispersive device V DS f f 1 0 f 2 DC (low frequency) High frequency f 1 f 2 : T DETRAP short : T DETRAP long Expected plot of maximum drain current as a function of frequency

48 Current Collapse Experimental set up Max drain current SIGNAL SOURCE MICROWAVE TRANSITION ANALYZER(sampling oscilloscope) 50 ohm load AMPLIFIER Z in = 50 ohm Measure waveform here 8000 BIAS TEE DUT BIAS TEE Vpp (V) R DC GATE BIAS DRAIN BIAS V PP / 50 = I PP = I MAX I DS V DS

49 Current Collapse Measure Max I DRAIN V PP / 50 = I PP = I MAX I DS 50 ohm load V DS Measure waveform here Ma ximum Drain Current (ma) st iteration nd iteration E+02 1.E+03 1.E+04 1.E+05 Frequency (Hz) Transient response is being measured

50 Current Collapse Trapping Transient V GS 50Ω V DD V DD V DS V DD V DS V GS V GS Formation of virtual gate Formation of virtual gate I DS I DS time f 1 f 2 f 3 time Bias and drive conditions cause formation of the virtual gate Transient response not a true frequency dependence

51 Current Collapse Effect of UV light V GS 50Ω V DD V DD V GS UV Light OFF ON OFF Trapping Transient I DS time Drain current recovers when UV light is incident

52 Current Collapse How does collapse occur? (1) (2) e - E C E C Gate + σ SURFACE DONOR + σ POL + σ SURFACE DONOR + σ Pol Net Positive Charge Drain - σ POL - σ 2DEG - σ Pol - σ TRAPPED SURFACE CHARGE 1 2 E c, when surface states are charged E c when virtual gate is non-existent Arrow indicates the transition from a non-existent virtual gate to negatively charged virtual gate. After virtual gate formed, The surface negative charge compensates the surface donor 2DEG channel is depleted

53 Current Collapse What does UV light do? E C Incident photons hν > E G E C + + σ SURFACE DONOR + σ Pol + σ SURFACE DONOR + σ HOLES + σ POL - σ Pol - σ TRAPPED SURFACE CHARGE - σ POL - σ 2DEG - σ TRAPPED SURFACE CHARGE The effect of incident photons. Holes generated in the GaN channel are swept to the surface. The positive charge due to the holes neutralizes the virtual gate

54 Current Collapse Bias Dependence of Virtual Gate V DD V DD1 70 V GS Formation of virtual gate Ids (ma) I DS 10 time V DD1, V DD2 Vds (V) Scan across the IV plane by choosing different V DD, the drain supply voltage, to observe the effect of drain bias on the extent and potential of the virtual gate.

55 Current Collapse Trapping Transient V DD V GS I DS V DD1 time Peak to Peak current (normalized units) Initial value 10kHz signal unpassivated NQZ HP wafer n_100_1 - n#1 100,1.5,0.5 Fit to 5V decay exp(-t/150)^0.47 Fit to 10V decay exp(-t/30)^0.45 Fit to 18V decay exp(-t/5)^0.40 (K) 2nd Fit to 18V decay (J) exp(-t/8)^0.43 5V 10V 18V fit to 5V decay fit to 10V decay (J) fit to 18V decay (K) 2nd fit to 18V decay Ids (ma) time after bias applied (s) Collapse depends on bias Vds (V) V DD1, V DD2 Trapping transient fits stretched exponential I = I 0 + I 1. e -(t/τ)β

56 Current Collapse Trapping Transient e - GATE Virtual Gate AlGaN GaN E C e Virtual gate forms DRAIN Peak to Peak current (normalized units) Initial value 10kHz signal unpassivated NQZ HP wafer n_100_1 - n#1 100,1.5,0.5 Fit to 5V decay exp(-t/150)^0.47 Fit to 10V decay exp(-t/30)^0.45 Fit to 18V decay exp(-t/5)^0.40 (K) 2nd Fit to 18V decay (J) exp(-t/8)^ time after bias applied (s) 5V 10V 18V fit to 5V decay fit to 10V decay (J) fit to 18V decay (K) 2nd fit to 18V decay Electric field that induces leakage reduces Active traps located continuously further away from gate Trapping transient fits stretched exponential I = I 0 + I 1. e -(t/τ)β

57 Current Collapse Surface Passivation S G AlGaN D S n s n s GaN Buffer G AlGaN GaN Buffer SiN D Substrate Substrate Surface passivation to prevent formation of virtual gate

58 Current Collapse Effect of Passivation V DD1 V DD V GS I DS Ids (ma) time Peak Drain Current (normalized units) Initial value Time (seconds) Passivated (10V) 2 - Passivated (14V) 3 - Passivated (18V) 4 - Unpassivated (5V) 5 - Unpassivated (10V) 6 - Unpassivated (18V) Vds (V) V DD1, V DD2

59 Current Collapse Effect of Passivation on Microwave Power Peak Drain Current (normalized units) Initial value Passivated (10V) 2 - Passivated (14V) 3 - Passivated (18V) 4 - Unpassivated (5V) 5 - Unpassivated (10V) 6 - Unpassivated (18V) Time (seconds) Output Power(dBm) / Gain(dB) W/mm Pout (dbm) Gain (db) PAE (%) Input Power (dbm) PAE (%) Extent of current collapse dramatically reduced on passivated devices Measured output power close to maximum available at that bias point

60 Conclusions Existence of a polarization dipole induces surface donor-like states Surface donors give rise to the 2DEG Surface donor states accept electrons making surface potential negative Accumulation of negative charge in gate drain region creates a virtual gate The spatial extent and potential of the virtual gate depends on bias and drive conditions Current collapse is due to inability to modulate the virtual gate Passivating the surface prevents formation of virtual gate, hence reducing current collapse