EVLSTNRG-1KW. 1 kw SMPS digitally controlled multiphase interleaved converter using STNRG388A. Description. Features
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1 EVLSTNRG-KW kw SMPS digitally controlled multiphase interleaved converter using STNRGA Description Data brief Features Digital controller: STNRGA -phase interleaved DC/DC architecture Full load power: 000 W (scalable up to kw) Efficiency: more than % from 0% to full load Peak efficiency:.% at full load Stand-by consumption: mw Input voltage range: 0 0 V dc CC/CV output regulation Output voltage regulation: V Output current regulation:. A Maximum output current for each phase:. A Modular power and control board The EVLSTRNG-KW evaluation board is intended for evaluating the STNRGA digital controller in offline power conversion applications such as EV battery chargers, UPS and industrial power supplies. The architecture is based on a multiphase interleaved DC/DC converter using the half bridge SAB ( Single Active Bridge ) topology supporting more than 000 W of power. The interleaved topology balances the power through parallel stages. Also, the solution delivers high efficiency during the whole load range by enabling one, two or three stages depending on the load. The STNRGA power conversion dedicated peripherals (SMEDs) offer the flexibility to drive the interleaved power stages while guaranteeing the correct phase realignment during the activation and deactivation of each stage. Thanks to the digital core of the STNRGA, it is also possible to monitor, control and debug the EVLSTRNG-KW board via a convenient HyperTerminal control. May 0 DocID0 Rev / For further information contact your local STMicroelectronics sales office.
2 Schematic diagrams EVLSTNRG-KW Schematic diagrams Figure. Power board schematic diagram - power section and feedback / DocID0 Rev
3 EVLSTNRG-KW Schematic diagrams Figure. Power board schematic diagram - auxiliary supply and protections BCC Q Q0 BCC U LD0DTTR VOUT CP_minus C 0n R k Q BCC L 0u R.k Vpf c C 00n 0VAC D PKC- D D C 0p NWS C 0u STTH0A Vaux R C R k u R 0k R 0k C n Ipk ON-OFF D OVS-00 R 0k R 00k L C u R 0k C 00u VIN C0 0u 0u L D OVS-00 0u T D0 STTH0A C 0u Vaux_sec_p D C 0u E/N Vaux_sec_m L u STTH0A R 00k R 0k D OVS-00 BCC Q D B- C0 ISO Vout_prot n R SFHA- k R R 0k.k C u VDDA C u Vout R.k U VIPER0HS 0 C 00n C u Q STNPF0 D NWS R.k R 0k R L u C 00u.k R0 0k CP_minus C 00u Vaux_sec_p R 0k R0.k D OVS-00 Q BCC Q BCC Q BCC AM0 DocID0 Rev /
4 Schematic diagrams EVLSTNRG-KW Figure. Power board schematic diagram - connector to control board J _POWER PWM0 PWM ON-OFF _SIGNAL PWM Enable Enable Enable VDDA Iavg R 0 OCP_OVP Enable VFB Vbrown_out Enable _POWER R 00k R 0k R 0k Enable Vaux CON0A R R R.k.k.k D OVS-00 D OVS-00 D OVS-00 _POWER AM0 Figure. Power board schematic diagram - gate driver subcircuit ^ Vh R.R Q0 PBSS0NT ^ Vm C 00n R R k R R R Vg ^ R Vl Q PBSS0PT 00k ^ AM0 / DocID0 Rev
5 EVLSTNRG-KW Schematic diagrams Figure. Control board schematic diagram VCC J0 C0 n.m. X0 n.m. C0 n.m. Near the power pin VCCA VCC L0 PIN0 PIN HSE - MHz PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN NOT USED WE-CBF J0 C0 00nF C0 00nF C0 00nF C0 00nF C0 uf RS--00 C0 uf RS--00 PIN R0 R0 PIN R0 R0 PIN R0 R0 PIN R0 R0 PIN R 0 R0 PIN R R PIN R R PIN PIN R0 R PIN R R PIN0 R 0 R0 PIN PIN R R PIN PIN R R PIN PIN0 R R PIN R R PIN R 0 R0 PIN R R PIN PIN R R PIN R R PIN R R PIN R 0 R0 PIN R R PIN R R PIN R R PIN R R PIN R0 0 R PIN _A _A VCC VCCA RESn C0 0nF P0 RESET PIN PIN VDDA U0 VCC C0 uf SWIM I/F PIN PIN PIN PIN PIN PIN PIN DIGIN[0]/CCO_clk DIGIN[] DIGIN[] DIGIN[] DIGIN[] DIGIN[] VOUT J0 _A R NRST 0 SWIM SWIM PIN PIN0 RESn CON0A R R R R R GPIO[0]/PWM[0] GPIO[]/PWM[] GPIO[]/PWM[] GPIO[]/PWM[] GPIO[]/PWM[] GPIO[]/PWM[] PIN PIN PIN PIN PIN R PIN SWIM I/F R PIN CPP[] CPP[] CMP CPP[] CPP[0] R R PIN PIN C 00p C 00p C 00p C 00p C 00p Near STLUX pins GPIO0[0]/UART_TX GPIO0[]/UART_RX GPIO0[]/IC_sda/HSEOscOut GPIO0[]/IC_scl/HSEOscIn GPIO0[]/DALI_tx GPIO0[]/DALI_rx 0 UART_TX UART_RX PIN PIN ADCIN[] ADCIN[] ADCIN[] ADCIN[] ADCIN[] ADCIN[] ADCIN[] ADCIN[0] PIN0 PIN USB to UART TTL (,V) RS-- USB cable _A PIN PIN UART_TX R R R R R R R R C 00p A IO UART_RX STNRGA 0 So cket TSSOP PIN0 PIN R J0 UART I/F C 00p C 00p C0 00p C 00p C 00p C 00p C 00p R0 _A J0 J0 PIN0 PIN PIN PIN PIN PIN0 _A PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN_STRIP_ PIN PIN 0 PIN J0 J0 J0 PIN_STRIP_ PIN PIN PIN PIN PIN0 PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN 0 PIN_STRIP_0 PIN_STRIP_ PIN_STRIP_0 AM00 DocID0 Rev /
6 Revision history EVLSTNRG-KW Revision history Table. Document revision history Date Revision Changes -May-0 Initial release. / DocID0 Rev
7 EVLSTNRG-KW IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 0 STMicroelectronics All rights reserved DocID0 Rev /
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NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD) plastic package.
Rev. 03 11 December 2009 Product data sheet 1. Product profile 1.1 General description NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device
Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.
Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
Dual N-channel field-effect transistor. Two N-channel symmetrical junction field-effect transistors in a SOT363 package.
Rev. 2 15 September 211 Product data sheet 1. Product profile 1.1 General description Two N-channel symmetrical junction field-effect transistors in a SOT363 package. CAUTION This device is sensitive to
PSMN013-80YS. N-channel LFPAK 80 V 12.9 mω standard level MOSFET
Rev. 1 25 June 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 C. This product is designed and qualified for use in a
PMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1.
Rev. 2 24 March 25 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features
2-input EXCLUSIVE-OR gate
Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
65 V, 100 ma NPN/PNP general-purpose transistor. Table 1. Product overview Type number Package NPN/NPN PNP/PNP Nexperia JEITA
Rev. 1 17 July 29 Product data sheet 1. Product profile 1.1 General description NPN/PNP general-purpose transistor pair in a very small Surface-Mounted Device (SMD) plastic package. Table 1. Product overview
N-channel TrenchMOS logic level FET
Rev. 2 3 November 29 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
PSMN8R3-40YS. N-channel LFPAK 40 V 8.6 mω standard level MOSFET
Rev. 1 25 June 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 C. This product is designed and qualified for use in a
XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger
Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
PSMN2R6-40YS. N-channel LFPAK 40 V 2.8 mω standard level MOSFET
Rev. 1 23 June 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 C. This product is designed and qualified for use in a
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
STTH5L06RL. Turbo 2 ultrafast high voltage rectifier. Main product characteristics. Features and benefits. Order codes.
STTH5L6 Turbo 2 ultrafast high voltage rectifier Main product characteristics K I (V) 5 V RRM 6 V I R (max) 125 µ / 15 µ T j (max) 175 C V (max) 1.5 V K TO-22C STTH5L6D K TO-22PC STTH5L6P t rr (max) 95
BCM857BV; BCM857BS; BCM857DS
BCM857BV; BCM857BS; BCM857DS Rev. 05 27 June 2006 Product data sheet 1. Product profile 1.1 General description in small Surface-Mounted Device (SMD) plastic packages. The transistors are fully isolated
PSMN4R5-40PS. N-channel 40 V 4.6 mω standard level MOSFET. High efficiency due to low switching and conduction losses
Rev. 2 25 June 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in TO22 package qualified to 175 C. This product is designed and qualified for use in a wide
Measurements are taken on a number of positions (N) and combined to find the unknowns (offsets, gains and cross-axis gains).
DT0059 Design Tip Ellipsoid or sphere fitting for sensor calibration By Andrea Vitali Main components* LSM303AGR LSM6DS3 Ultra compact high-performance e-compass: ultra-low-power 3D accelerometer and 3D
150 V, 2 A NPN high-voltage low V CEsat (BISS) transistor
Rev. 0 November 2009 Product data sheet. Product profile. General description NPN high-voltage low V CEsat Breakthrough In Small Signal (BISS) transistor in a medium power SOT223 (SC-73) Surface-Mounted
N-channel TrenchMOS standard level FET. Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance
Rev. 2 3 February 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.
Rev. 1 17 November 25 Product data sheet 1. Product profile 1.1 General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features
PTC04-DB-HALL02. Daughter Board for Melexis PTC devices. Features and Benefits. Applications. Ordering Information. Accessories. 1. Functional Diagram
PTC0-DB-HALL0 Features and Benefits PTC0 interface board for testing devices: 0 0 0 Applications Experimental tool for Lab and Prototyping Production Equipment for Serial Programming Ordering Information
FHR
FHR 2- FEATURES Resistances from 0.001 Ohm to 0.01 Ohms Power rating to Watt Resistance tolerances to ±1% TCR to ±30 ppm/k Load stability to 0.5% Customized resistance values TABLE 1 SPECIFICATIONS TYPE