All-inkjet printed electronic circuits: Dielectrics and surface passivation techniques for improved operational stability and lifetime

Transcription

1 All-inkjet printed electronic circuits: Dielectrics and surface passivation techniques for improved operational stability and lifetime M. C. R. Medeiros 1, F. Villani 2, A. T. Negrier 3, F. Loffredo 2, R. Miscioscia 2 C. Martinez-Domingo 5, E. Ramon 5, E. Sowade 6, K. Y. Mitra 6, R. R. Baumann 6, I. McCulloch 7, J. Carrabina 4 and H. L. Gomes 3,4

2 Outline All-inkjet printed organic electronics. Improving device operational stability. How to asses dielectrics for printed electronics. Trapping and detrapping experiments. Conclusions.

3 Printed electronics

4 All-inkjet printed electronics Flexink FS027 Ag Ag c-pvp Ag PEN substrate Individual TFT Ring oscillators Cross-linked Poly-4-Vinylphenol (c-pvp) dielectric cured in Convection oven at 100 ºC. Triarylamine semiconducting polymer

5 All-inkjet printed organic inverter

6 All-inkjet printed TFTs Dimatix Materials Printer 2831 (DMP2831! Gate Electrode Dielectric Source and drain contacts Semiconductor

7 Printed TFTs - Transfer curve in linear region is perfect straight without hysteresis - no traps - Mobility: 0.1 cm²/vs - Threshold voltage: < 2 V - Yield: 70%

8 Gate-bias stress / (figure of merit) τ is a figure of merit that measures stability A. Sharma et al. Appl. Phys. Lett. 99, (2011)

9 Dielectric passivation Pentafluorothiophenol (PFTP) Dielectric Silver PEN (plastic foil)

10 Improved stability All-inkjet printed in air Param. Not passivated Passivated β τ 0 2x10 3 s 2x10 4 s

11 Assessing printed dielectrics How to select a suitable dielectric? Dielectric Silver PEN (plastic foil) Two years of hard work To learn what?

12 Assessing printed dielectric/ semiconductor interfaces How to asses dielectrics for printed electronics? Convential way: Reproduce what has been done for silicon Usually this fails Semiconductor Dielectric Gold RCL E c E F E V Reasons: Printed semiconductor layers layers are usually too thick this implies a low relaxation frequency preventing impedance measurements n + -Si Gs C s Oxide Ci C2 C1 Gd Cd Ri R2 R1 Accumulation channel Rb Bulk

13 Filling and emptying traps Trap emptying by light Trap filled by bias The TFT is most sensitive to energies corresponding to the semiconductor band-gap. The recovering time is directly proportional to the optical power.

14 Light-induced current transients The optical induced transient is a detrapping current (charge neutralization)

15 Optical detrapping experiments hν= 2.31 ev (polymer band-gap) Photo-generated electrons recombine with the trapped charges and neutralize them. S H + H + H + H + G D - + V DS = -20 V + - V G = +20 V (depletion mode) A

16 Quantifying trapped charges Charge density = 3.7x10 11 /cm 2

17 Filling and emptying traps 240 K

18 Filling and emptying traps

19 Assessing dielectrics for TFTs (Message) Techniques to address impurity states in silicon are based on the fact that traps fill fast and empty fast. In amorphous or in organic semiconductors the filling is fast but the empty is so slow than most of the techniques available do not apply in a reasonable temperature range. MESSAGE: We have to change the receipts : We must study the traps during the filling and not during the empting process.

20 Conclusions Pentafluorothiophenol (PFTP) can be printed and used as a surface passivation layer. The TFT operational stability improves substantially. Maping deep traps dielectric/semiconductor interfaces has been hampered because they are too deep and distributed in energy. These traps are responsible for the gate-bias stress and by the so called Contact effects. The density of trap-sites can estimated from ligth-induced recovering experiments...

21 Acknowledgements Maria Medeiros (UC-IT) Carme Martinez-Domingo (UAB)! Fulvia Villani (ENEA)! Fausta Loffredo (ENEA) Eloi Ramon (UAB)! Riccardo Miscioscia (ENEA) Enrico Sowade (TUC) Kalyan Y. Mitra (TUC)

22 University of the Algarve Thank you for your attention!