83a. i 0 = I (2.105) v n = R n i n, 1 n N. (2.102) Next, the application of KCL to either node yields. i 0 + i 1 + i N = 0 (2.103)

Transcription

1 example 2.2 an N resistor current divider Now consider the more general current divider having N resistors, as shown in Figure It can be analyzed in the same manner as the tworesistor current divider. To begin, the element laws are i = I (2.11) v n = R n i n, 1 n N. (2.12) Next, the application of KCL to either node yields i i 1 i N = (2.13) and the application of KVL to the N 1 internal loops yields v n = v n 1, 1 n N. (2.14) Finally, Equations 2.11 through 2.14 can be solved to yield i n = v n = where G n 1/R n. This completes the analysis. i = I (2.15) G n G 1 G 2 G N I, 1 n N (2.16) 1 G 1 G 2 G N I, n N (2.17) As was the case for the tworesistor current divider, the preceding analysis shows that parallel resistors divide current in proportion to their conductances. This follows from the G n in the numerator of the righthand side of Equation Additionally, the analysis again shows that parallel conductances add. To see this, let G P be the equivalent conductance of the N parallel resistors. Then, from Equation 2.17 we see that from which it also follows that G P = I v n = G 1 G 2 G N (2.18) 1 = (2.19) R P R 1 R 2 R N where R P 1/G P is the equivalent resistance of the N parallel resistors. The latter result is summarized in Figure a

2 ... FIGURE 2.4 The equivalence of parallel resistors; for N = 2, R P = R 1 R 2 /(R 1 R 2 ). R 1 R 2 R 1 p R N = R N... R 1 R 2 Finally, the two currentdivider examples illustrate an important point, namely that parallel elements all have the same voltage across their terminals because their terminals are connected directly across one another. This results in the KVL seen in Equations 2.8, 2.81, and 2.14, which state the equivalence of the terminal voltages. 83b

3 example 2.28 basic circuit analysis method Solve the circuit in Figure 2.58 using the basic method. Step 1 is to assign the branch variables. Figure 2.59 shows the circuit with the variables properly assigned. In Step 2, we write the constituent relations: v S = V (2.153) v 1 = i 1 R 1 (2.154) v 2 = i 2 R 2 (2.155) v 3 = i 3 R 3 (2.156) v 4 = i 4 R 4 (2.157) v 5 = i 5 R 5. (2.158) In Step 3, we write the KVL and KCL equations. The KVL equations with respect to the loop choice shown in Figure 2.6, are v S v 1 v 2 v 4 = (2.159) v 2 v 3 = (2.16) v 4 v 5 = (2.161) R 1 R 2 V R 3 FIGURE 2.58 Circuit example. R 4 R 5 97a

4 v i 1 FIGURE 2.59 Circuit with properly assigned variables. v S V R 1 v v 2 1 R 2 i 2 i 3 R 3 v 3 i S R 4 v 4 i 4 R 5 i 5 v 5 (a) L1 L2 FIGURE 2.6 Loop and node choice. V (b) (d) L3 (c) 97b

5 At node (a), the KCL equation is i 1 i 2 i 3 =. (2.162) Notice that nodes (b) and (c) are connected by a wire, so they yield only one KCL equation Lastly, at node (d), we have i 2 i 3 i 4 i 5 =. (2.163) i 4 i 5 i S =. (2.164) Combining the constituent relations with KVL equations, we obtain By adding Equations , we have V i 1 R 1 i 2 R 2 i 4 R 4 = (2.165) i 2 R 2 i 3 R 3 = (2.166) i 4 R 4 i 5 R 5 =. (2.167) i S = i 1. (2.168) Eliminating i 2 and i 4 and substituting back into Equations gives us i 3 = i S R 2 R 2 R 3 (2.169) R 4 i 5 = i S R 4 R 5 (2.17) ( ) V = i S R 1 R 2 R 4 R2 2 R2 4 R 2 R 3 R 4 R 5 (2.171) ( = i S R 1 R 2R 3 R ) 4R 5. R 2 R 3 R 4 R 5 (2.172) As a quick sanity check of the solution, one might notice that the equivalent resistance of the network around the voltage source is R 1 R 2 R 3 R 4 R 5, which is correctly shown by Equation c

6 example 2.33 voltagecontrolled resistor Thus far we have dealt with resistors that have a fixed resistance. However, like dependent sources, we can also have resistors whose values depend on other parameters. As an example, Figure 2.71 depicts a voltagecontrolled resistor whose resistance R X is a function of v I. Let us suppose we are interested in determining v O as a function of v I for R X = f (v I ) = R o v I where R o is some known constant. Let R o = 5k /V. First, R 1 and R 2 form a simple voltage divider, and since R 1 = R 2, we have v I = V/2. Second, R L and R X also form a voltage divider. Therefore, v O = V R X R L R X = V R ov I R L R o v I 5k /v I = V 1 k 5k /v I = V v I 2 v I V 2 = V 2 V 2 = V2 4 V. Substituting V = 5 V, we find that v O = 25/9 V. R 1 = 1 kω R L = 1 kω FIGURE 2.71 Circuit with voltagedependent resistor. V 5 V v I R 2 = 1 kω v O R X = f(v I ) 17a

7 2.7 A FORMULATION SUITABLE FOR A COMPUTER SOLUTION * Thus far we have seen several circuit examples that we solved by writing a set of equations based on the constituent relations for the elements, KVL, and KCL. There were as many independent equations as unknown variables, which allowed us to solve for any variable by simple algebra. The same set of equations can be written in matrix form so that they are amenable to a computer solution. For example, the circuit in Figure 2.1 analyzed using the basic method in Section resulted in ten equations and ten unknowns. These ten equations are summarized as follows: v 1 = i 1 R 1 (2.22) v 2 = i 2 R 2 (2.23) v 3 = i 3 R 3 (2.24) v 4 = i 4 R 4 (2.25) v 5 = V (2.26) v 5 v 1 v 2 = (2.27) v 2 v 3 v 4 = (2.28) i 5 i 1 = (2.29) i 1 i 2 i 3 = (2.21) i 3 i 4 =. (2.211) The ten unknowns are v 1, v 2, v 3, v 4, v 5, i 1, i 2, i 3, i 4, and i 5. The equations can be rewritten so that constant voltages and currents appear on the lefthand side of the equation. = v 1 i 1 R 1 (2.212) = v 2 i 2 R 2 (2.213) = v 3 i 3 R 3 (2.214) = v 4 i 4 R 4 (2.215) V = v 5 (2.216) = v 1 v 2 v 5 (2.217) = v 2 v 3 v 4 (2.218) = i 5 i 1 (2.219) = i 1 i 2 i 3 (2.22) = i 3 i 4. (2.221) 17b

8 This set of equations can be written in matrix form as follows: 1 R 1 1 R 2 1 R 3 1 R 4 V = This matrix equation is in the form b = Ax v 1 v 2 v 3 v 4 v 5 i 1 i 2 i 3 i 4 i 5 (2.222) where x is a column vector of unknowns and b is the column vector of drive voltages and currents. This vector of unknowns can be solved by a computer using standard linear algebraic techniques such as Cramer s rule. In fact, the well known SPICE software package uses methods such as these to solve circuits The examples in this chapter focused on linear circuits, which result in a set of linear simultaneous equations. However, the fundamental method of solving circuits based on KVL, KCL, and constituent relations applies equally well to nonlinear circuits. A nonlinear circuit might contain nonlinear circuit elements with constituent relations such as v = i 3 R, or, i = K(e v/v T 1). The resulting set of equations that arise will be nonlinear. Computer solution of such circuits makes use of another technique called linearization, which is discussed in Chapter 4. Further discussions of linearity are in Chapter 3, and a further treatment of nonlinear circuits is in Chapter 4. 17c

9 example 3.9 even more on the node method As we discussed earlier, it is often inefficient to use only Kirchhoff s laws to analyze complicated circuits. For example, if we simply modify the example we saw on page 192 to the circuit shown in Figure 3.18, Kirchhoff s laws alone will not be able to solve it easily. We will use the node method to solve the problem and the node assignment in Figure With respect to the node assignment in Figure 3.19, we have the following equations: V e 1 e 2 e 1 e 3 e 1 = R 1 R 2 R 3 (3.29) e 2 e 1 e 2 e 3 e 2 = R 4 R 2 R 6 (3.3) e 1 e 3 e 2 e 3 e 3 =. R 3 R 6 R 5 (3.31) We can rearrange the terms and express the equations in matrix form: V e 1 R 1 R 2 R 3 R 2 R 3 R ( ) R 2 R 2 R 4 R 6 R 6 e 2 ( ) = R 3 R 6 R 3 R 5 R 6 e 3 i 1 R 1 v 2 i 3 i S V R 4 v 4 v 1 R 2 i 2 i 6 i 4 R 5 R 3 v 6 R 6 i 5 v 3 FIGURE 3.18 Circuit with appropriate branch variables. v 5 135a

10 e 1 R 1 R 2 v 2 v 1 FIGURE 3.19 Node assignments of the circuit. V R 4 v 4 e 2 R 5 R 6 R 3 v 6 v 3 v 5 e 3 Standard matrix techniques can be used to solve for the unknowns. Let us assign the following values to the resistors and voltage source: V = 5V R 1 = 5 R 2 = 1 R 3 = 1 R 4 = 75 R 5 = 75 R 6 = 15. Then we have: e e 15 2 = 3 1 e 3 135b Solving for e 1, e 2, and e 3, we have e 1 = 35/11 V, e 2 = 15/11 V, and e 3 = 15/11 V. Notice that e 2 = e 3, that is, there is no current going through resistor R 6. Since R 2 = R 3 and R 4 = R 5, the symmetry of the network between node e 1 and ground splits the current going into node e 1 evenly, thus causing the same voltage drop.

11 example 3.12 a more complex dependentcurrent source problem As a more complex example of the node analysis of a circuit containing dependent sources, consider the analysis of the circuit shown in Figure This circuit has two dependent sources: one VCCS and one CCVS. In addition, its resistors are labeled with their conductances for convenience. To analyze the circuit in Figure 3.28, we redraw it as shown in Figure Here, the VCCS is replaced by an independent current source having value Ĩ, and the CCVS is replaced by an independent voltage source having value Ṽ. Note that the new independent voltage source is not a floating voltage source because it is connected to ground through the known voltage V. The circuit in Figure 3.29 can be analyzed by the node method presented earlier. Since ground is already defined in the figure at Node 5, Step 1 is already complete. To complete Step 2, the node voltages are labeled as shown. The voltages at Nodes 1 and 2 are the unknown node voltages e 1 and e 2. The voltage at Node 3 is set by the original independent voltage source, and is labeled accordingly. The voltage at Node 4 is also known since the new voltage source is an independent source, and it is labeled as such. Next, we perform Step 3, writing KCL for Nodes 1 and 2 in the process. This yields G 1 (e 1 V Ṽ) G 2 (e 1 e 2 ) I = (3.64) Node 4 v e 1 Node 1 G 1 ri Node 3 V i G 3 G 2 e 2 I Node 2 FIGURE 3.28 A circuit with two dependent sources. V G 4 gv Node 5 145a

12 V Ṽ Node 4 v e 1 Node 1 G 1 FIGURE 3.29 The circuit from Figure 3.28 redrawn with independent sources. Ṽ Node 3 V i G 3 G 2 e 2 I Node 2 V G 4 Ĩ Node 5 for Node 1, and G 2 (e 2 e 1 ) G 3 (e 2 V ) G 4 e 2 I Ĩ = (3.65) for Node 2. Equations 3.64 and 3.65 can be restated as [ ][ ] [ ] I G1 G 2 G 2 e 1 1 G1 G 1 V = G 2 G 2 G 3 G 4 e 2 1 G 3 1 Ĩ. (3.66) Ṽ Following Step 4, Equation 3.66 is solved for e 1 and e 2. This yields [ ] [ ][ ] I e 1 = 1 G2 G 3 G 4 G 2 1 G1 G 1 V e 2 G 2 G 1 G 2 1 G 3 1 Ĩ Ṽ [ ] (G3 G 4 )I(G 1 (G 2 G 3 G 4 )G 2 G 3 )VG 2 ĨG 1 (G 2 G 3 G 4 )Ṽ = 1 G 1 I(G 1 G 2 G 1 G 3 G 2 G 3 )V(G 1 G 2 )ĨG 1 G 2 Ṽ (3.67) 145b

13 where = (G 1 G 2 )(G 2 G 3 G 4 ) G 2 2. (3.68) Finally, we use Equations 3.67 and 3.68 to solve for i and v, the branch variables that control the CCVS and the VCCS, respectively. This yields i = Ĩ G 4 e 2 = 1 [ ] G 1 G 4 I (G 1 G 2 G 1 G 3 G 2 G 3 )(G 4 V Ĩ ) G 1 G 2 G 4 Ṽ (3.69) v = e 1 V Ṽ = 1 [ ] (G 3 G 4 )I G 2 G 4 V G 2 Ĩ G 2 (G 3 G 4 )Ṽ, (3.7) which completes the node analysis of the circuit in Figure Note that KCL was used at Node 5 to derive the first equality in Equation To find the actual values for Ĩ and Ṽ, we now substitute Equations 3.69 and 3.7 into the element laws for the CCVS and the VCCS, respectively. This yields Ṽ = ri = r [ ] G 1 G 4 I (G 1 G 2 G 1 G 3 G 2 G 3 )(G 4 V Ĩ ) G 1 G 2 G 4 Ṽ (3.71) for the CCVS, and Ĩ = gv = g [ ] (G 3 G 4 )I G 2 G 4 V G 2 Ĩ G 2 (G 3 G 4 )Ṽ (3.72) for the VCCS. Finally, Equations 3.71 and 3.72 are jointly written as [ ][Ĩ ] gg 2 gg 2 (G 3 G 4 ) r(g 1 G 2 G 1 G 3 G 2 G 3 ) rg 1 G 2 G 4 Ṽ [ ][ ] g(g3 G 4 ) gg 2 G 4 I = rg 1 G 4 rg 4 (G 1 G 2 G 1 G 3 G 2 G 3 ) V (3.73) and then solved simultaneously to yield [ ] Ĩ = Ṽ [ ][ ] g(g3 G 4 ) gg 2 G 4 (1 rg 3 ) I r(g 1 G 4 gg 3 ) rg 4 (G 1 G 2 G 1 G 3 G 2 G 3 ) V. (3.74) rg 1 G 2 G 4 gg 2 (1 rg 3 ) The actual values of the dependent sources are now known. Finally, to complete the node analysis, at least to the point of determining e 1 and e 2, Equation 3.74 is substituted 145c

14 into Equation 3.67 to yield [ ][ ] G3 (1 rg) G 4 (1 rg 1 ) G 2 G 4 rg 1 G 3 G 4 gg 2 (1 rg 3 ) I [ ] e 1 g G 1 G 1 G 2 G 1 G 3 G 2 G 3 gg 2 (1 rg 3 ) V =. e 2 rg 1 G 2 G 4 gg 2 (1 rg 3 ) (3.75) Now, with Equations 3.74 and 3.75, all node voltages are known and so all branch variables may be computed explicitly. As was the case for the circuit in Figure 3.26, it is also possible to apply the simple node analysis described in Subsection 3.3 to the circuit in Figure However, for the latter circuit, the savings in time is not as great because some effort and thought is needed to express i and v explicitly in terms of e 1 and e 2. Furthermore, since these expressions can be obtained in several different ways, the simple analysis becomes somewhat ad hoc when applied to the circuit in Figure To begin the simple node analysis of the circuit in Figure 3.28, we express i and v explicitly in terms of e 1 and e 2. The ability to do so will be needed to carry out the spirit of Step 3. From the definition of v in Figure 3.28, it is apparent that v = e 1 V ri. (3.76) Thus, v can easily be expressed explicitly in terms of e 1 and e 2 once i is so expressed. One relatively convenient way to express i explicitly in terms of e 1 and e 2 is to combine KCL applied at Nodes 1, 3, and 4. This results in i = I G 2 (e 2 e 1 ) G 3 (e 2 V). (3.77) The first term on the righthand side of Equation 3.77 is the current through the independent current source, and the second term on the righthand side is the current through the resistor labeled G 2. These two currents combine at Node 1, and their sum exits Node 1 through the resistor labeled G 1. Finally, the combined current passes through Node 4 and the CCVS, before entering Node 3. At Node 3, the combined current also combines with the current through the resistor labeled G 3, and together they exit Node 3 as i. The last term on the righthand side of Equation 3.77 is the current through the resistor labeled G 3. Thus, Equation 3.77 does express KCL applied to Nodes 1, 3, and 4. Finally, the substitution of Equation 3.77 into Equation 3.76 yields v = e 1 V r (I G 2 (e 2 e 1 ) G 3 (e 2 V)), (3.78) which expresses v explicitly in terms of e 1 and e 2. Next, we apply the simple node method, beginning with Step 3, yielding = G 1 v G 2 (e 1 e 2 ) I, (3.79) 145d

15 for Node 1 and = I G 2 (e 2 e 1 ) G 3 (e 2 V ) G 4 e 2 gv (3.8) for Node 2. At this point Equations 3.79 and 3.8 still contain v. However, upon substitution of Equation 3.78, they can be rewritten as [ ][ ] G1 G 2 rg 1 G 2 G 2 rg 1 (G 2 G 3 ) e 1 G 2 g rgg 2 G 4 (1 rg)(g 2 G 3 ) e 2 [ ][ ] 1 rg1 G 1 (1 rg 3 ) I =. (3.81) 1 rg G 3 (1 rg) g V Finally, following Step 4, Equation 3.81 can be solved to yield [ ][ ] G3 (1 rg) G 4 (1 rg 1 ) G 2 G 4 rg 1 G 3 G 4 gg 2 (1 rg 3 ) I [ ] e 1 g G 1 G 1 G 2 G 1 G 3 G 2 G 3 gg 2 (1 rg 3 ) V =, e 2 rg 1 G 2 G 4 gg 2 (1 rg 3 ) (3.82) which is identical to Equation 3.75, as it should be. The main point here is that while the application of the simple node analysis described in Section 3.3 to circuits containing dependent sources can result in less work, it also generally becomes less structured. This is because, as part of the analysis, it is necessary to determine the variables that control the dependent sources explicitly in terms of the unknown node voltages before the node analysis is actually completed. It may not always be obvious how to do this in a simple way. For this reason, when it is necessary to carry out a wellstructured node analysis, such as when the analysis is to be computerized, then the node analysis presented in this subsection is preferred. 145e

16 3.3.4 THE CONDUCTANCE AND SOURCE MATRICES * As we saw earlier in Equation 3.27, when a resistive circuit is linear (that is, when its resistors and dependent sources are all linear), the equations resulting from Step 3 of a node analysis can be formulated as a matrix equation, which takes the form Ḡ ē = S s. (3.83) Here, ē is a vector of the unknown node voltages, s is a vector of the known independent source amplitudes, and Ḡ and S are known matrices, referred to here as the conductance and source matrices, respectively. Examples of such equations can be seen in Equations 3.27 and As previewed in the discussion following Equation 3.27, the matrices Ḡ and S have a very special structure. This structure allows us to skip the details of Step 3 of a node analysis, and derive the two matrices directly from the topology of the circuit. This also facilitates the computerization of a node analysis. Alternatively, the special structure of the two matrices can be used to check our work during Step 3. For simplicity, in this subsection we will examine the structure of Ḡ and S that arises from circuits that contain neither floating voltage sources nor dependent sources. However, it is possible to extend our observations to accommodate these sources as well. The special structure of Ḡ and S can be exposed by studying the partial circuit shown in Figure 3.3. By the end of Step 3 of a node analysis, one expression of KCL has been derived in terms of the unknown node voltages for each node having an unknown node voltage. In the case of the partial circuit in Node 1 e 1 G 1 e 2 e 3 I FIGURE 3.3 A partial circuit. G 2 Node 2 V V G 3 Node 3 145f

17 Figure 3.3, the corresponding expression of KCL for Node 3 is G 1 (e 3 e 1 ) G 2 (e 3 e 2 ) G 3 (e 3 V ) I =. (3.84) In writing Equation 3.84, KCL has been taken to state that the sum of the currents exiting a node must vanish. Next, we rearrange Equation 3.84 as G 1 e 1 G 2 e 2 (G 1 G 2 G 3 )e 3 = G 3 V I. (3.85) By writing KCL as in Equation 3.85, the special structure of the expression becomes apparent. For example, the conductance of each resistor connected to Node 3 contributes positively to the coefficient of e 3, and negatively to the coefficient of the node voltage at the other end of the resistor. This is because e 3 acts to drive currents out from Node 3, while the other node voltages act to drive currents in to Node 3. The same observation holds for the coefficient of the grounded independent voltage source, except for a change in sign due to the fact that the corresponding term is moved to the opposite side of the equal sign. We also see that the current source enters positively into Equation 3.85, once its term is moved to the opposite side of the equal sign, since it sources current into Node 3. Now consider assembling Equation 3.85, and its counterparts from the other nodes in the circuit, in the form of Equation Each expression of KCL becomes a row within Equation For the sake of discussion, let us assume that these rows are ordered according to the number of the node for which they are written, and further that the node voltages in ē are listed in order of their corresponding node numbers. In this case, Equation 3.85 enters into Equation 3.83 as. e 1.. e 2. I. e 3. V G 1 G 2 G 1 G 2 G 3 e 4 = 1 G (3.86) Thus, we see that Ḡ is a matrix of conductances. A diagonal element at the position [m, m] inḡ is the sum of the conductances connected Node m. An offdiagonal element at the position [m, n] inḡ, m = n, is the negative of the conductance connecting Nodes m and n. This is true even for the zero elements within Ḡ since a zero conductance indicates the absence of a resistor, 145g

18 145h or no connection. As a consequence of this structure, Ḡ is symmetric about its main diagonal, at least in the absence of dependent sources. Similarly, the matrix S contains the coefficients of the sources. For each independent current source, there will be a 1 in its column in S at Row m if the source enters Node m, a 1 if the source exits Node m, and a otherwise. For each grounded independent voltage source, the conductance connecting it to Node m will appear in Row m of its column in S, including zeros to indicate the absence of a connecting resistor. Again, the structure of Ḡ and S can be seen in Equations 3.27 and Consider, for example, the matrices in Equation The [1,1] element of Ḡ is G 1 G 2 G 3 because the resistors labeled G 1, G 2, and G 3 are all connected to Node 1. Similarly, the [2,2] element in Ḡ is G 3 G 4 because the resistors labeled G 3 and G 4 are both connected to Node 2. The [1,2] and [2,1] elements in Ḡ are both G 3 since G 3 connects Nodes 1 and 2. Since the voltage source connects to Node 1 through the resistor labeled G 1, but does not connect to Node 2, the [1,1] element of S is G 1 and the [2,1] element is zero. Similarly, since the current source enters Node 2, but does not connect to Node 1, the [2,2] element of S is 1 and the [1,2] element is zero. Thus, the matrices in Equation 3.27 could have been derived by inspection of the circuit topology only.

19 3.4 LOOP METHOD * We have already seen several examples of a complementary relationship between voltage and current, so it should come as no surprise that there is a simplified analysis method based on an astute choice of current variables that closely parallels the method in the preceding section. Here we choose current variables that flow in loops, that is, in closed paths. By this definition, the current flowing into any node will always be identically equal to the current flowing out, so KCL is identically satisfied. As in Chapter 2, we continue to define loop currents until every element is traversed by at least one loop current. To illustrate, let us define a set of current loops for the circuit we previously analyzed, as in Figure KCL at Node 1 gives (i 1 i 2 ) i 1 i 2 = (3.87) which is identically zero for all values of i. Thus because KCL is automatically satisfied for this choice of current variables, we have to write only KVL and the constituent relations. Combining these in one step, we obtain V (i 1 i 2 )R 1 i 1 R 2 = (3.88) i 1 R 2 i 2 R 3 (i 2 I )R 4 =. (3.89) Now rewrite to place the source terms on the left: V = i 1 (R 1 R 2 ) i 2 R 1 (3.9) IR 4 = i 1 R 2 i 2 (R 3 R 4 ). (3.91) i 2 R 1 Node R 3 1 Node 2 V R 2 R 4 I I i 1 FIGURE 3.31 Loop currents. 145i

20 By Cramer s Rule, i 1 = V(R 3 R 4 ) IR 4 R 1 (R 1 R 2 )(R 3 R 4 ) R 1 R 2. (3.92) The voltage across R 2 can now be found from Equation 3.92 and e 1 = i 1 R 2. (3.93) Equations 3.92 and 3.93 can be reduced to Equation 3.8 by simple algebra. 145j

21 example 3.13 loop method Let us use the loop method to analyze the circuit depicted in Figure 3.18 in our previous example. Figure 3.32 shows our choice of the loops for this circuit. The corresponding loop equations are V i 1 R 1 (i 1 i 2 )R 2 (i 1 i 3 )R 4 = (3.94) (i 2 i 1 )R 2 i 2 R 3 (i 2 i 3 )R 6 = (3.95) (i 3 i 1 )R 4 (i 3 i 2 )R 6 i 3 R 5 =. (3.96) By rearranging the terms into matrix form, we obtain R 1 R 2 R 4 R 2 R 4 i 1 V R 2 R 2 R 3 R 6 R 6 i 2 =. R 4 R 6 R 4 R 5 R 6 i 3 Assigning the same values to the voltage source and resistors, V = 5V R 1 = 5 (a) R 1 R 2 i 1 i 2 R 3 V R 4 (b) FIGURE 3.32 Circuit with properly assigned current loops. R 6 i 3 (d) (c) R 5 145k

22 R 2 = 1 R 3 = 1 R 4 = 75 R 5 = 75 R 6 = 15 we obtain i i 2 = i 3 Solving, we have i 1 = 2/55 A, i 2 = 1/55 A, and i 3 = 1/55 A. As a sanity check, the current flowing through R 6 is i 2 i 3 =, as desired. 145l

23 example 3.17 superposition applied to a beehive network Superposition and a bit of creativity can also be used to solve more complicated resistive networks. Figure 3.45 shows a resistive network containing an infinite plane of resistors in a beehive shape. Each of the resistors have a resistance value R. What is the equivalent resistance R eqv when looking into port AB? One of the key ideas of this problem is to properly choose a reference node or a ground node for measuring voltages of the internal nodes in the network. Referring to Figure 3.46, we take ground at infinity. Then, we introduce a current I P into node A using a current source, and draw I P out of node B using another current source. If we can compute the resulting voltage V P between nodes A and B, then we can obtain the effective resistance between A and B as R eqv = V P I P. Our circuit has two sources, one injecting a current I P into the network, and the other drawing a current I P out of the network. We will determine the voltage V P using superposition by adding the voltages across A and B resulting from each of the current sources acting alone. Figure 3.47 shows the circuit with the current source at B A B FIGURE 3.45 An infinite plane resistive network. Each resistor has a resistance value R. 153a

24 I P FIGURE 3.46 Introducing ground into the network. V P A B I P i 3 I P FIGURE 3.47 The circuit with only the current source at A being applied. i 2 i 1 V P1 A B 153b

25 i 5 i 4 V P2 A B FIGURE 3.48 The circuit with only the current source at B being applied. i 6 I P turned off, and Figure 3.48 shows the circuit with the current source at A turned off. Let V P1 be the voltage across A and B when the current source at A acts alone, and let V P2 be the voltage across A and B when the current source at B acts alone. By superposition, we know that V P = V P1 V P2. Referring to Figure 3.47, the current I P injected into node A will split evenly into three currents, i 1, i 2, and i 3. We know that i 1 = i 2 = i 3 because the injected current faces a symmetric situation in each of the three directions. Since, by KCL, I P = i 1 i 2 i 3, we can write i 1 = i 2 = i 3 = I P c

26 Since the current through the resistor connecting nodes A and B is i 1 = I P /3 and since the resistance value of the resistor is R, we can write V P1 = Ri 1 = R I P 3. Similarly, referring to Figure 3.48, the current I P drawn out of node B comprises three components i 4, i 5, and i 6, where Since, by KCL, we can write i 4 = i 5 = i 6. I P = i 4 i 5 i 6, i 4 = i 5 = i 6 = I P 3. And in like manner, since the current through the resistor connecting nodes A and B is i 4 = I P /3, and since the resistance value of the resistor is R, we can write V P2 = Ri 4 = R I P 3. Composing the expressions for V P1 and V P2 we get Therefore, V P = V P1 V P2 = 2I P 3 R. R eqv = V P I P = 2 3 R. 153d

27 example 4.5 node method This example uses the device shown in Figure 4.5. Recall that this device is characterized by the following device equation: i D =.1v 2 D for v D, (4.17) V v 1 i D D1 i D is given to be for v D <. Referring to the series connected nonlinear devices in Figure 4.14, determine i D, v 1, and v 2, given that V = 2V. v 2 D2 We will use the node method to solve this problem. We first select a ground node and label node voltages as shown in Figure We have one unknown node voltage v 2. FIGURE 4.14 Nonlinear devices connected in series. Next, we write KCL for the node with the unknown node voltage. Recall that the KCL equations in the node method are written directly in terms of the node voltages. Accordingly,.1v 2 2 =.1(V v 2) 2. V The term on the lefthand side is the current through device D2. Similarly, the term on the righthand side is the current through device D1. Solving, we get V i D D1 v 2 = V 2. v 2 Given that V = 2V, we get v 2 = 1V. We now obtain the remaining voltages and currents by applying KVL and the relevant device laws. Thus, D2 and v 1 = V v 2 = 1V FIGURE 4.15 Circuit with node voltages labeled. i D =.1v 2 2 =.1 A. Notice that we could have also solved the circuit intuitively by realizing that the same current flows through two identical nonlinear devices. Thus, the same voltage must drop across both. In other words, Furthermore, by KVL Or, v 1 = v 2 = 1V. v 1 = v 2. 2V= v 1 v 2. 21a

28 example 4.8 making simplifying assumptions Sometimes, there are a few special cases of interest that can be solved analytically by making appropriate simplifying assumptions. The circuit in Figure 4.19 is one such example. Here for variety, we will solve the circuit by a direct application of KVL and KCL. KVL around the path containing the voltage sources and the diodes yields and KCL at the junction of the two diodes gives 2E v D1 v D2 = (4.28) i D1 i D2 = I A. (4.29) These two equations, together with the equations for the diodes of the form of Equation 4.1, can be solved for the diode currents, assuming identical diodes. Now, if we assume that the diode voltages are always positive enough to make the 1 term in the diode equation negligible (for Equation 4.1, true within less than one percent for all v D larger than 125 mv), then i D1 becomes I A i D1 = 1 e 2E/V. (4.3) TH We can obtain this equation by following these steps. First, substitute in Equation 4.28 expressions for v D1 and v D2 in terms of i D1 and i D2 derived from the diode equations (neglecting the 1 term). Second, obtain i D2 in terms of i D1 from this equation, substitute in Equation 4.29, and simplify to get Equation 4.3. The diode current is thus a hyperbolic tangent function of the voltage E, except for an offset of I A /2. E I A i D1 v D1 FIGURE 4.19 Hyperbolic tangent generator. E i D2 v D2 23a

29 example 4.9 voltagecontrolled nonlinear resistor Let us now determine v O as a function of v I for the circuit in Figure 2.71 when where R o = 1 k V. R X = f (v I ) = R o v I 1V. We have, v O = V R X R L R X R o v = V I 1 v R L R o v I 1 v R o = V. R L (v I 1V) R o Substituting, R o = 1 k V and R L = 1 k, 1 k V v O = V 1 k (v I 1V) 1 k V = V v I = ( V ) V 2 = 2V. 23b

30 example 4.13 halfwave rectifier reexamined As another example of piecewise linear analysis, we reexamine the halfwave rectifier circuit for a sinusoidal input previously analyzed using graphical analysis in Section 4.1. This time around, we will use a piecewise linear model for the diode, but use the same graphical approach of Section 4.1. Thus we start with the same circuit topology as in Figure 4.21a, except that the diode is modeled using its piecewise linear approximation, the ideal diode, as shown in Figure 4.32a. Assuming as before a tenvolt sinusoidal input voltage, as might be typical in power supplies, we draw a succession of load lines on the piecewise linear characteristics, Figure 4.32b, for representative values of the input wave, and plot the output voltage point by point. The desired output voltage is v R, which in the graph is the horizontal E = E o cos( ωt) (a) R v R i D Slope = 1/R FIGURE 4.32 Halfwave rectifier: ideal diode piecewise linear analysis. (b) v R E v D v R (c) t 214a

31 distance from the operation point intersection to the input voltage. The resulting output wave is shown in Figure 4.32c. Comparison with the previous analysis, Section 4.1 and Figure 4.21, indicates that at least for this problem, the simple ideal diode approximation yields a reasonably accurate answer. As one would expect, the error mainly derives from the neglect of the.6v drop across the diode. Clearly, the error would be more objectionable if the input sinusoid had been of one volt peak rather than 1 volts. 214b

32 4.4.1 IMPROVED PIECEWISE LINEAR MODELS FOR NONLINEAR ELEMENTS * The accuracy of the results of a piecewise liner analysis depends on the accuracy of the model used. In this section, we will discuss the process of creating more precise models of nonlinear elements when increased accuracy is desired. To illustrate the process, let us use the diode as an example of a nonlinear element. Thus far, we used the simple, ideal diode model. It is obvious from the preceding example that the major effect in the model is when the voltage v D across the diode is positive, and above about.6 V. Substantial improvement can be made by adding a.6v source in series with the ideal diode, as shown in Figure 4.33a. The corresponding i v characteristic for the improved piecewise linear model is shown in Figure 4.33b. Let us work a simple example using this piecewise linear model. i D i D v D (a).6 V (b).6 V v D FIGURE 4.33 Improved piecewise linear diode models. i D v D R d.6 V i D.6 V Slope = v D 1 R d (c) (d) 214c

33 example 4.14 another example using piecewise linear modeling Let us rework the example containing a voltage source, resistor, and diode in Figure 4.16 using the piecewise linear model for the diode from Figure 4.33b. The behavior of this model, comprising an ideal diode in series with a voltage source, can also be summarized in two statements: Diode ON (vertical segment): v D =.6 V for i D > Diode OFF (horizontal segment): i D = for v D <.6 V (4.47) Let us determine i D for E = 3 V and E = 5 V, given that R = 5. According to the piecewise linear method, we will focus on one straightline segment at a time, using linear analysis within each segment. Vertical segment When i D and v D are in the vertical segment of their characteristic, the circuit shown in Figure 4.34b results, and we can write i D = E.6 V. (4.48) R Horizontal segment Figure 4.34c shows the corresponding circuit when the diode is operating as an open circuit. In this segment, i D =. (4.49) Combining the results Intuition tells us that the vertical segment applies when E >.6 V (the diode turns on) and the horizontal segment applies otherwise (diode is off). Thus, when E = 3 V, Equation 4.48 applies, and i D = E.6 V R = = 4.8 ma. Comparing to Equation 4.4, notice that the value of i D predicted by this improved model is slightly lower than that predicted by the ideal diode model. The ideal diode model did not account for the.6v drop across the diode, and so overestimated the current. Equation 4.49 applies when E = 5V,so i D =. 214d

34 v R R i D E.6 V v D (a) Complete model v R FIGURE 4.34 Piecewise linear analysis in the vertical and horizontal straightline segments using the diode model containing a voltage source. E R.6 V i D v D (b) Vertical segment v R E R.6 V i D v D (c) Horizontal segment Further improvement in accuracy can be realized by adding a series resistor R d of suitable value to the ideal diode and voltage source, as shown in Figure 4.33c. The specific choice of resistor value depends on the application; one should strive to make the characteristic match over the range of diode current expected in the specific circuit (see Figure 4.35). We will illustrate the use of this model in an example. More examples using these and other more complicated piecewise models will appear throughout the book, and specifically in Chapters 7 and e

35 example 4.15 the diode resistance Choose values for R d for the piecewise linear diode model in Figure 4.33c assuming that the resistance must provide a reasonable match for currents up to.4 A and 1 A. Assume V TH =.25 V and I s = 1 12 A. Figure 4.35 plots the v i characteristics for the diode. The figure shows that the resistance value R d1 =.1 provides a good match for the diode v i characteristics up to 1 A, while the resistance value R d2 =.2 provides a better match in the smaller current range from zero to.4 A. i D (A) Slope = 1, R d1 =.1 Ω Slope = 5, R d2 =.2 Ω FIGURE 4.35 Choosing a value of the resistance in the piecewise linear diode model v D (V) 214f

36 example 4.16 a more complicated piecewise linear model Let us further rework the previous example using the piecewise linear model for the diode from Figure 4.33c. The behavior of this model, comprising an ideal diode in series with a voltage source and a resistor, can be summarized in two statements: Diode ON (vertical segment): v D =.6 V i D R d for i D >. Diode OFF (horizontal segment): i D = for v D <.6 V. (4.5) Again, let us determine i D for E = 3 V and E = 5 V, given that R = 5 and R d = 1. Vertical segment When i D and v D are in the vertical segment of their characteristic, the circuit shown in Figure 4.36b results, and we can write i D = E.6 V R R d. (4.51) Horizontal segment Figure 4.24c shows the corresponding circuit when the diode is operating as an open circuit. In this segment, i D =. (4.52) Combining the results For E = 3 V, Equation 4.51 applies, and so i D = E.6 V R R d Equation 4.52 applies when E = 5V,so = 3.6 V = 4.7 ma. 5 1 i D =. As illustrated using the diode, increasingly better fits to an actual nonlinear device characteristic can be obtained by introducing more and more ideal elements. For example, for the diode, increasingly better fits to the actual diode characteristic can be obtained by introducing more and more ideal diodes, batteries, and resistors. But again a price is paid; increased accuracy of the model brings increased complexity. The proper compromise between simplicity and accuracy is not always obvious. Start with the simplest model, then add complexity to see if the solution changes in major ways. 214g

37 v R R i D E.6 V v D (a) Complete model R d v R E R.6 V R d i D v D FIGURE 4.36 Piecewise linear analysis in the vertical and horizontal straightline segments using the diode model containing a voltage source and a resistor. (b) Vertical segment v R E R.6 V i D v D R d (c) Horizontal segment 214h

38 example 4.21 diode regulator To further illustrate the use of incremental analysis, we examine the diode circuit shown in Figure 4.45, another crude form of voltage regulator that is slightly better than our previous regulator. As before, we assume that the supposedly DC source supplying the circuit in reality has 5 volts of DC with 5 millivolts of AC superimposed. The regulator is designed to reduce this unwanted AC component relative to the DC. To understand how the circuit operates, first draw the DC subcircuit to determine I D and V O, the operating point variables of the circuit. We will use the piecewise linear analysis method (based on the piecewise linear model of the diode shown in Figure 4.33c) to determine the operating point variables. Accordingly, Figure 4.45b shows the DC subcircuit in which each diode has been replaced with its piecewise linear model comprising an ideal diode, a.6v voltage source and a resistor of value R d.by inspection From Figure 4.45b, 5V 1.8V I D =. (4.84) R 3R d For R = 1 and R d = 1, a reasonable value for diode currents in the 1 to 1mA range, I D = 3.2 = 3.1 ma. (4.85) 13 Next, draw the incremental subcircuit, as shown in Figure 4.45c. Here we will use the accurate v i relation for the diode from Equation 4.1 to compute the value of R Total source 5 mv AC 5 V DC v O R FIGURE 4.45 Diode regulator. (a) R 5 V DC 1.8 V 3 R d V O 5 mv AC 3 r d v o (c) Incremental AC subcircuit (b) DC subcircuit 228a

39 the incremental diode resistance r d. This incremental resistance can be derived using Equation 4.75, in which f is the diode v i relation. We have also seen that the application of Equation 4.75 for the diode v i relation results in Equation 4.74, which directly yields the value of r d as 25 mv r d = 8.1. (4.86) 3.1 ma Now, from Figure 4.45c, we can write an expression for the small signal AC output 3r v o = 5 d 3r d R = = 1.19 mv AC. (4.87) (From Equation 4.66, with v o equal to 1.19 mv we expect an error of about 2% in the neglect of higherorder terms in the incremental analysis.) The total DC output voltage of the regular can be found from the DC subcircuit, Figure 4.45b, The fractional ripple at the input, V O = 1.8 3I D R d (4.88) = = 1.89 V. (4.89) fractional ripple = = 1 2 (4.9) 5 and at the output, fractional ripple = 1 3 (4.91) 1.89 so the ripple has been reduced relative to the DC by a factor of b

40 example 4.22 small signal analysis using a piecewise linear diode model In the diode regulator example, we used the piecewise linear model for the diode when conducting the DC operating point analysis, but reverted to the accurate diode equation when computing the small signal resistance. This example will illustrate that small signal analysis of nonlinear devices can also be carried out by using their piecewise linear models for both the DC operating point analysis and in computing the small signal device resistance. Of course, the accuracy of the results will depend on the fidelity of the piecewise linear model used for the nonlinear device. The example will be based on the simple dioderesistor circuit shown in Figure Let us suppose we are interested in the small signal values of the output voltage and the diode current for a 5mV incremental input. As promised, throughout this example, we will use the piecewise linear model for the diode illustrated in Figures 4.33a and 4.33b. We start by drawing the DC subcircuit to determine the operating point variables I D, V O as shown in Figure 4.46b. By inspection, we can write I D = 5.6. R For R = 1, I D = 4.4 ma and V O =.6 V. R 5 mv i D 5 V v O R FIGURE 4.46 A simple dioderesistor circuit. (a) Total circuit R I D 5 mv r d = i d v O 5 V.6 V V O (c) Incremental subcircuit (b) DC subcircuit 228c

41 Next, we draw the incremental subcircuit for the operating point given by I D = 4.4 ma and V O =.6 V. Since we chose to use the piecewise linear model for the diode throughout our analysis, we must derive r d based on this model. Since I D >, notice that the diode is operating in the vertical segment of the piecewise linear v i curve shown in Figure 4.33b. Since the reciprocal of the slope of this curve segment is zero, r d is also zero. In other words, the ideal diode looks like a short circuit for incremental changes in the current. Figure 4.46c shows the corresponding incremental subcircuit. From Figure 4.46c, it is easy to see that the incremental change in the output voltage for the 5mV change in the input voltage is simply v o =. Similarly, the incremental change in the current is given by 5 mv i d = = 5 µa. R 228d

42 example 5.14 simplifying another logic expression (a) Find the minimum sumofproducts representation for the boolean expression in Equation 5.8, namely Output = A B C D ABC D A B C D. (5.3) (b) Further, show that the expression in Equation 5.3 is equivalent to the logic expression in the caption of Table 5.7, namely AB C D. As directed in part (a), we will simplify the expression in Equation 5.3 as follows: Output = A B C D ABC D A B C D = A B C D ABC D A B C D A B C D = (A B C D ABC D) (A B C D A B C D) = A C D(B B) B C D (A A) = A C D 1 B C D 1 = A C D B C D. (5.31) To answer part (b), recall that we have previously shown that AB C D can be simplified to A C D B C D (see Equation 5.29). Since the expressions in Equations 5.29 and 5.31 are identical, it follows that AB C D and A B C D ABC D A B C D are equivalent. 267a

43 example 5.16 yet another implementation using nors Let us derive an implementation based on twoinput NOR gates for the function AB C D. Assume that both the true and complement version of each of the inputs is available: AB C D = A B (C D) (5.35) = A B C D C D (5.36) = ((A B) ((C D) C D)). (5.37) Implementing each of the expressions within parentheses using twoinput NOR gates, we get the circuit shown in Figure Notice that the algebraic simplification process was quite cumbersome. We can actually perform the same transformation directly on a gatelevel circuit with greater ease. Figure 5.25 shows how the original circuit for AB C D from one of the implementations in Figure 5.18 can be transformed into a twoinput NOR implementation. The transformations exploit the fact that two inverters (or circles) in series cancel each other. C D A B FIGURE 5.24 NOR implementation of AB C D. A B C D A B C D A B A B FIGURE 5.25 NOR transformations for AB C D. C D C D 267b

44 6.11 ACTIVE PULLUPS Large valued resistors are difficult to fabricate in VLSI technology. For example, R is usually on the order of a few tens of ohms for polysilicon, few hundreds of ohms for diffusion, and few hundredths of an ohm for metal. Fabricating a 1k resistor using polysilicon would require an area hundreds of times larger than that of a minimum sized transistor. Fortunately, MOSFETs themselves make good highvalued resistors for the same area, the resistance R ON of a minimum sized MOSFET is significantly higher than that of a resistance made out of other materials, such as polysilicon. Figure 6.55 shows an inverter constructed out of MOSFETs with M pu serving as an active pullup. The pullup MOSFET has its drain tied to the power supply connection, and thus the drain has a voltage V S applied with respect to ground. To keep the pullup MOSFET permanently in its ON state, its gate is connected to a second voltage V A, where V A is at least one threshold voltage higher that the supply voltage. In other words, V A > V S V T. V S V A M pu W L pu v OUT v IN M pd W L pd FIGURE 6.55 Logic gate with active pullup. In the circuit, V A > V S V T, so that the pullup MOSFET is always in its ON state. V S V S R ONpu R ONpu v OUT v OUT v IN = High R ONpd v IN = Low 321a

45 Let the W/L ratios of the pullup and the pulldown MOSFETs be (W/L) pu and (W/L) pd, respectively. Let the corresponding ONstate resistances (according to the SR model) be R ONpu and R ONpd. We also know that R ON L W where the constant of proportionality is R n. 25 Let us now choose the respective (W/L) ratios so that the inverter satisfies the relationship derived in Equation 6.6, and repeated below for convenience: V S R ON R ON R L < V T This relationship between the output low voltage of the inverter and the threshold voltage of a MOSFET is necessary for the inverter to be able to drive the MOSFET in another inverter into its OFF state. In the preceding equation, R L is the resistance of the pullup device, and R ON is the resistance of the pulldown device. With both an active pullup and an active pulldown, V T > V S 1 1 R L R ON > V S 1 1 (L/W) pu (L/W) pd (6.12) (6.13) where we have substituted the L/W ratios in place of the resistance values. 25. As mentioned earlier, the MOSFET displays resistive behavior between its drain and its source only when the drain voltage is much smaller than the gate voltage (specifically, v DS v GS V T ). Furthermore, the resistance R n, and therefore R ON, depends on the value of the applied gate voltage. We will see more appropriate models for MOSFETs in other regions of operation in later chapters. But for now, let us go ahead and use the SR model with a single value for R n to analyze the active pullup. 321b

46 For our typical parameters: V S = 5 V and V T = 1 V. Therefore, we get (L/W) pu (L/W) pd < 1 (6.14) ( ) L 5 < 1 W ( ) L pu (6.15) W ( ) L pd 4 < W ( ) L W pu pd. (6.16) In other words, we can choose the size of the pullup so its (L/W) ratio is four times that of the pulldown. 321c

47 example 6.9 sizing pullup devices For a 5V supply voltage, suppose our static discipline prescribes a V OL =.5 V. How do we size the pullup MOSFET in Figure 6.56 relative to the pulldown MOSFET to meet the valid output low threshold? When the pulldown device is on, we know that the output voltage is given by V A V S R ONpu L W pu v OUT R ONpd v OUT = V S. R ONpd R ONpu v IN R ONpd L W pd To satisfy the static discipline, we must have V OL > v OUT when the input is high. Recall that the onstate resistance is proportional to the ratio of the device gate length L and its width W. Thus we have, FIGURE 6.56 An inverter with an active pullup. V OL > v OUT (6.17) > V S R ONpd R ONpd R ONpu (6.18) > V S ( L/W ) pd ( L/W ) > ( ) L/W pd ( L/W ) pu pu ( L/W ) pd (6.19). (6.2) For V OL =.5 V, it is easy to see that if we choose (L/W) pu > 9 we will satisfy the static (L/W) pd discipline. In other words, if both devices are of the same width W, the pullup device must be sized so its length is nine times that of the pulldown device. 321d

48 example 6.1 combinational logic using mosfet switches Let us now rework some of our previous examples using allmosfet designs and the SR model. Assume that we need to design our gates such that they satisfy a static discipline with the low output voltage threshold V OL = V T V, where V T is given to be 1 V. Let us design allmosfet circuits and let us attempt to make them as small as possible. Assume that the area of the circuit is proportional to the area of the gates (W L) of the individual MOSFETs. Let us also compute the power dissipated by the circuits. Assume that R n for the MOSFETs is 1 k. Let us first consider the expression: AB C D. Figure 6.57 shows a compound gate comprising only MOSFETs that implements this expression. This gate design replaces the load resistor in Figure 6.23 with an active pullup. Our task is to determine the sizes of both the pulldown and the pullup MOSFETs so this gate satisfies the static discipline for V OL = 1 V. Note that the gate must satisfy the static discipline for any combination of inputs. As we have seen before, the key issue in designing a NMOS logic gate is to choose the relative values of the pullup and the pulldown resistances so that even the highest value for the gate s output low voltage satisfies the V OL constraint. Since we are asked to design the circuit that occupies the least area, and there are more pulldown transistors than pullups, let us start by choosing minimumsized transistors ((L/W ) pd = 1) for the pulldown circuit. Therefore the on resistance of an individual pulldown MOSFET is ( ) L R ONpd = R n = R n. W pd The highest value for the output low voltage occurs when the pulldown circuit has its highest resistance. Notice that the pulldown circuit has its largest onstate resistance for an output low when A and B are on, and C and D are off. This largest pulldown resistance is given by the sum of the onstate resistances of the MOSFETs with the A V S FIGURE 6.57 Transistorlevel implementation of AB C D using an active pullup. In the circuit, V A > V S V T, so that the active pullup is in its ON state at all times. A B V A C W L pu D OUT W L pd 321e

49 and B inputs. That is, R pdmax = 2R ONpd = 2R n. To satisfy the static discipline, the output voltage of the gate for a logical must be less than V OL for any combination of inputs that can result in a logical at the gate s output. In other words, the highest value for the low output voltage of the gate must be less than V OL, which is given to be V T. Since the output voltage of the gate is given by R ONpd V S, R ONpu R ONpd We can write the following constraint so that the gate satisfies the static discipline for V OL = V T : R ONpd V T > V S R ONpu R ONpd > V S 2R n R ONpu 2R n 2R n > V S ( ) L R n 2R n W pu 2 > V S ( ). L 2 W pu For V S = 5 V and V T = 1 V, the previous constraint simplifies to ( ) L > 8. W pu In other words, the L/W ratio of the pullup must be chosen to be greater than 8. Thus the resistance of the pullup is 8R n. Let us now compute the power dissipated by the circuit. The maximum amount of power is dissipated when the resistance of the pulldown circuit is a minimum. This happens when A = 1, B = 1, C = 1, and D = 1. Recalling that the resistances of each of the pulldowns is R n and that of the pullup is 8R n, V 2 S P max = 8R n 2R n R n R n = W. 321f