VLSI Arithmetic Lecture 10: Multipliers

Transcription

1 VLSI Arithmetic Lecture 10: Multipliers Prof. Vojin G. Oklobdzija University of California

2 A Method for Generation of Fast Parallel Multipliers by Vojin G. Oklobdzija David Villeger Simon S. Liu Electrical and Computer Engineering University of California Davis

3 Fast Parallel Multipliers Objective Improved Speed of Parallel Multiplier via: Improvements in Partial-Product Bit Reduction Techniques Optimization of the Final Adder for the Uneven Signal Arrival Profile from the Multiplier Tree 46

4 Multiplication Algorithm: P = XY = X n 1 i= 0 y i r i = n 1 i= 0 X y i r i p ) (0 = 0 initially ( j 1) 1 j p = ( p + r + n r Xy j ) for j=0,...,n-1 p(n)=xy after n steps 47

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6 49

7 Parallel Multipliers Step 0 Step 1 Step 2 Step 3 Step 4 50

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12 55

13 Minimum Number of Stages (Dada s Rule) 56

14 Their Schemes

15 Use of 4:2 Compressors A. Weinberger 1981 M. Santoro

16 4:2 Compressor 59

17 Critical Signal Path in a 4:2 Compressor Tree 60

18 Re-designed 4:2 Compressor with 3 XOR Delay (Nagamatsu, Toshiba) Cin I1 I2 I3 I4 S 1 0 C C out 61

19 Critical Path in a 4:2 Compressor 62

20 Signal Arrival Profile for RWT (3:2) and MWT (4:2) 63

21 Using 9:2 Compressors (P. Song, G. De Michelli 1991) 64

22 Compressor Tree Implemented with 9:2 Compressors 65

23 9:2 Compressor Structure 66

24 Delay (XOR Gates) Critical Path: (Equivalent XOR Gate Delays) Title 4:2 Compressor (Redesigned) 9to2 Compressor (Redesigned) 3,2 Counter Multiplier Width (bits) 67

25 Delay Expressed as No. of XOR Gate Delays 68

26 Use of Higher-Order Compressors D. Villeger, V.G. Oklobdzija

27 Design of a 13:2 Compressor from a 9:2 Compressor 70

28 Delay Profile of a 24:2 Compressor Tree 71

29 Compressor Family Characteristics 72

30 Using Carry-Propagate Adders (G. Bewick 1993) (D. Villeger & V. G. Oklobdzija 1993) 73

31 Column Compression Tree Consisting of 4-bit Adders 74

32 Bit Reduction Using 4-bit Adders (24X24) 75

33 Idea!!!!!

34 A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach TDM (Oklobdzija, Villeger, Liu, 1994) 77

35 Partial Product Martix Divided into Vertical Compressor Slices Vertical Slices Carry Propagate Adder Horizontal Propagation Carry and Sum Connection to the Final Adder 78

36 3-Dimensional View of Partial Product Reduction Vertical Compressor Slice - VCS FA FA FA FA FA Time Example of a 12 X 12 Multiplication (Partial Product for X*Y = B54 * B1B) Final Adder 79

37 Signal Delays in a Full Adder (3,2) Counter A B Cin Fast Input Sum Fast Output Carry 80

38 Signal Delays in a Full Adder (3,2) Counter A B Cin Fast Input Sum Fast Output Carry 81

39 Three-Dimensional optimization Method: TDM (Oklobdzija, Villeger, Liu, 1996) 82

40 Method

41 a b cin a b cin c s c s Worst Case TDM Arrangement 84

42 Two cases of signals passing through the next level a b cin a b cin c s c s a b cin a b cin c s c s Best Balanced Case Average Case 85

43 Example of Delay Optimization Example of a Optimized Interconnection Example of a not Optimized Interconnection bit (n) position bit (n-1) position bit (n) position bit (n-1) position a b cin a b cin a b cin a b cin 0 xor c s 2 xor c s 0 xor c s 2 xor c s 1 xor a b cin a b cin a b cin 1 xor a b cin c s c s c s c s 3 xor 3 xor 3 xor 4 xor 86

44 The 9th Vertical Compressor Slice of a Multiplier A B A B Cin A B Cin A B Cin C S C S C S C S A B Cin C S A B Cin C S A B Cin C S 11 May Multiplier Design

45 Computer Tools

46 M ethod for Optimal Interconnection Signals w ith Different Delay Levels Sig n als w ith short delays Signals with intermediate delays Signals with long delays a b cin a b cin a b cin a b cin c s c s c s c s Add slow input delay Add fast input delay Bypass Signals, No Delay Added Level i Level i+1 Signals with short delays Signals w ith Different Delay Levels Signals with intermediate delays Signals with long delays 89

47 Design of Parallel Multipliers Algorithm for Automatic Generation of Partial Product Array. Initialize: Form 2N-1 lists Li ( i = 0, 2N-2 ) each consisting of p i elements where: p i = i+1 for i N-1 and p i = 2N-1-i for i N An element of a list L i ( j = 0,...,p i-1 ) is a pair: <n j, D j >i where: n j : is a unique node identifying name D j : is a delay associated with that node representing a delay of a signal arriving to the node nj with respect to some reference point. For i = 0,1 and 2N-2: connect nodes from the corresponding lists L i directly to the CPA. 90

48 Delays Delay(S) = MAX {Delay(A) + D A-S, Delay(B) + D B-S, Delay(C in ) + D Cin-S } Delay(C) = MAX {Delay(A) + D A-C, Delay(B) + D B-C, Delay(C in ) + D Cin-C } In our case the delays in a FA are : FA A S = FA B S = 2 XOR delays FA Cin S = FA A C = FA B C = FA Cin C = 1 XOR delay. In a HA: HA A S = HA B S = 1 XOR delay while HA A C = HA B C = 0.5 XOR delay. 91

49 For i=2 to i=2n-3 {Partial Product Array Generation} Begin For if length of Li is even Then Begin If sort the elements of Li in ascending order by the values of delay δ jconnect an HA to the first 2 elements of Li starting with the slowest input Ds =max {δ A +δ A-S, δ B +δ B-S } Dc =max {δ A +δ A-C, δ B +δ B-C } remove 2 elements from L i insert the pair <Ds,NetName> into L i insert the pair <Dc,NetName> into L i+1 decrement the length of L i increment the length of L i+1 End If; 92

50 while length of Li > 3 Begin While sort the elements of Li in ascending order by the values of delay δj connect an FA to the first 3 elements of Li starting with the slowest input of the FA: Ds =max {δc A +δc A-S, δc B +δc B-S, δc Ci +δc Ci-S } Dc = max {δc A +δc A-C, δc B +δc B-C, δc Ci +δc Ci-C } remove 3 elements from Li insert the pair <Ds,NetName> into Li insert the pair <Dc,NetName> into Li+1 subtract 2 from the length of Li increment the length of Li+1 End While; sort the elements of Li connect an FA to the last 3 nodes of Li connect the S and C to the bit i and i+1 of the CPA End For; End Method;

51 Competing Approaches

52 Comparison between TDM and other representative schemes, in XOR levels. Multiplier Wallace Tree [7] 4:2 Tree [11] Fadavi - TDM Word-length Ardekani [16]

53 Critical Path Delay [CMOS: Leff=1 µ, T=25 o C, V cc=5v] N = 24-bits 4:2 Design 9:2 Design Fadavi-Ardekani TDM Design Delay [ns]

54 Delay (XOR Levels) Equivalent XOR Delays ,2 4:2 9:2 Fadavi-Ardekani TDM Multiplier Width 11 May Multiplier Design

55 Algorithm for Implementation of Fast Parallel Multipliers [1] V. G. Oklobdzija, D. Villeger, and S. S. Liu, A Method For Speed Optimized Partial Product Reduction And Generation Of Fast Parallel Multipliers Using An Algorithmic Approach, IEEE Transactions on Computers, Vol 45, No.3, March, [2] V. G. Oklobdzija and D. Villeger, Improving Multiplier Design By Using Improved Column Compression Tree And Optimized Final Adder In CMOS Technology, IEEE Transactions on VLSI Systems, Vol.3, No.2, June, 1995, 25 pages. [3] V. G. Oklobdzija and D. Villeger, Multiplier Design Utilizing Improved Column Compression Tree And Optimized Final Adder In CMOS Technology, Proceedings of the 1993 International Symposium on VLSI Technology, Systems and Applications, pp , [4] P. Stelling, C. Martel, V. G. Oklobdzija, R. Ravi, Optimal Circuits for Parallel Multipliers, IEEE Transaction on Computers, Vol. 47, No.3, pp , March,

56 Organization of Hitachi's DPL multiplier 99

57 Hitachi's 4:2 compressor structure 100

58 DPL multiplexer circuit 101

59 Addition Under Non-equal Signal Arrival Profile Assumption P. Stelling, V. G. Oklobdzija, "Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier", special issue on VLSI Arithmetic, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol.14, No.3, December

60 Signal Arrival Profile form the Parallel Multiplier Partial-Product Recuction Tree 103

61 Oklobdzija, Villeger, IEEE Transactions on VLSI Systems, June,

62 Oklobdzija and Villeger, IEEE Transactions on VLSI Systems, June,

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71 Performing Multiply-Add Operation in the Multiply Time P. Stelling, V. G. Oklobdzija, " Achieving Multiply-Accumulate Operation in the Multiply Time", Thirteenth International Symposium on Computer Arithmetic, Pacific Grove, California, July 5-9,

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73 Final Adder: Implementation 116

74 Final Adder: Implementation 117

75 Final Adder: Implementation 118

76 Final Adder: Implementation 119

77 RECOMENDATIONS

78 Fast Parallel Multipliers Different Counter and Compressor Families were compared. The best way is to build a compressor of the maximal size (i.e. the entire size of the multiplier) The Essence of the optimal tree is optimal wiring and NOT the use of counter/compressor family The use of Carry-Propagate Adders is advantageous for larger size multipliers in the first stage and for particular technology Tuning of the Final Adder into the signal arrival profile is more important than the speed of the Final Adder. 121

79 THE END 122

80 Hollywood