2-channel analog multiplexer/demultiplexer. The 74LVC2G53 can handle both analog and digital signals.

Size: px
Start display at page:

Download "2-channel analog multiplexer/demultiplexer. The 74LVC2G53 can handle both analog and digital signals."

Transcription

1 Rev. 0 0 January 006 Product data sheet. General description. Features The is a high-performance, low-power, low-voltage, i-gate CMO device that provides superior performance to most advanced CMO compatible TTL families. The provides one analog multiplexer/demultiplexer with a digital select input (), two independent inputs/outputs ( and B), a common input/output () and an active LOW enable input (). When pin is HIGH, the is turned off. The can handle both analog and digital signals. Wide supply voltage range from.65 V to 5.5 V Very low ON resistance: 7.5 Ω (typical) at =.7 V 6.5 Ω (typical) at = 3.3 V 6 Ω (typical) at =5V High noise immunity D protection: HBM JD-4-C exceeds 000 V MM JD-5- exceeds 00 V CDM JD-C0-C exceeds 000 V CMO low-power consumption Latch-up performance meets requirements of JD 78 Class I Direct interface with TTL levels Control inputs accepts voltages up to 5 V Multiple package options pecified from 40 C to +85 C and from 40 C to +5 C

2 3. Quick reference data 4. Ordering information Table : Quick reference data = 0 V; t r =t f.5 ns; minimum and maximum values at T amb = 40 C to +85 C; typical values at T amb =5 C. ymbol Parameter Conditions Min Typ Max Unit t on turn-on time to or Bn C L = 50 pf; R L = 500 Ω = 3.3 V ns = 5.0 V ns to or Bn C L = 50 pf; R L = 500 Ω = 3.3 V ns = 5.0 V ns t off turn-off time to or Bn C L = 50 pf; R L = 500 Ω = 3.3 V ns = 5.0 V ns to or Bn C L = 50 pf; R L = 500 Ω = 3.3 V ns = 5.0 V ns C i input capacitance pf C (OFF) OFF-state capacitance pf C (ON) ON-state capacitance pf 5. Marking Table : Ordering information Type number Package Temperature range Name Description Version DC 40 C to +5 C VOP8 plastic very thin shrink small outline package; 8 leads; body width.3 mm OT765- GT 40 C to +5 C XON8 plastic extremely thin small outline package; no leads; 8 terminals; body mm OT833- Table 3: Marking Type number DC GT Marking code V53 V53 _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January 006 of 3

3 6. Functional diagram 6 B aad386 Fig. Logic symbol B 00aad387 Fig. Logic diagram 7. Pinning information 7. Pinning B B aad389 00aad388 Transparent top view Fig 3. Pin configuration VOP8 Fig 4. Pin configuration XON8 _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

4 7. Pin description Table 4: Pin description ymbol Pin Description common output or input enable input (active LOW) 3 ground (0 V) 4 ground (0 V) 5 select input B 6 independent B input or output 7 independent input or output 8 supply voltage 8. Functional description 8. Function table Table 5: Function table [] Input Channel on L L to or to H L B to or to B X H Z ( off) [] H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = high-impedance OFF-state. _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

5 9. Limiting values Table 6: Limiting values In accordance with the bsolute Maximum Rating ystem (IC 6034). Voltages are referenced to (ground = 0 V). ymbol Parameter Conditions Min Max Unit supply voltage V V I input voltage [] V I IK input clamping V I < 0.5 V or V I > m current I K clamping current V I < 0.5 V or V I > ±50 m V W voltage enable and disable mode V I W current V W = 0.5 V to ( V) - ±50 m I CC quiescent supply - 00 m current I ground current - 00 m T stg storage temperature C P tot total power dissipation T amb = 40 C to +5 C [] mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [] For VOP8 package: above 0 C the value of P tot derates linearly with 8 mw/k. For XON8 package: above 45 C the value of P tot derates linearly with.4 mw/k. 0. Recommended operating conditions Table 7: Recommended operating conditions ymbol Parameter Conditions Min Typ Max Unit supply voltage V V I input voltage V V W voltage enable and disable [] 0 - V mode T amb ambient temperature C t/ V input transition rise and =.65 V to.7 V [] 0-0 ns/v fall rate =.7 V to 5.5 V [] 0-0 ns/v [] To avoid drawing current out of terminal when current flows in terminal Bn, the voltage drop across the bidirectional must not exceed 0.4 V. If the current flows into terminal, no current will flow out of terminal Bn. In this case, there is no limit for the voltage drop across the. [] pplies to control signal levels. _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

6 . tatic characteristics Table 8: tatic characteristics t recommended operating conditions; voltages are referenced to (ground 0 V). ymbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C [] HIGH-state input voltage =.65 V to.95 V V =.3 V to.7 V V = 3 V to 3.6 V V = 4.5 V to 5.5 V V LOW-state input voltage =.65 V to.95 V V =.3 V to.7 V V = 3 V to 3.6 V V = 4.5 V to 5.5 V V I LI input leakage current on pin and pin ; - ±0. ± µ V I = 5.5 V or ; = 5.5 V I (OFF) OFF-state leakage current per channel; V W = and V O = or V W = and V O = ; = 5.5 V; see Figure 5 - ±0. ±5 µ I (ON) ON-state leakage current per channel; V W = or ; = 5.5 V; see Figure 6 I CC quiescent supply current V I = or ; V W = or ; I O =0; = 5.5 V I CC additional quiescent supply current per input pin; V I = 0.6 V; V W = or ; I O = 0 ; = 5.5 V - ±0. ±5 µ µ µ C i input capacitance pf C (OFF) OFF-state capacitance pf C (ON) ON-state capacitance pf T amb = 40 C to +5 C HIGH-state input voltage =.65 V to.95 V V =.3 V to.7 V V = 3 V to 3.6 V V = 4.5 V to 5.5 V V LOW-state input voltage =.65 V to.95 V V =.3 V to.7 V V = 3 V to 3.6 V V = 4.5 V to 5.5 V V I LI input leakage current on pin and pin ; - - ±0 µ V I = 5.5 V or ; = 5.5 V I (OFF) OFF-state leakage current per channel; V W = and V O = or V W = and V O = ; = 5.5 V; see Figure ±0 µ _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

7 Table 8: tatic characteristics continued t recommended operating conditions; voltages are referenced to (ground 0 V). ymbol Parameter Conditions Min Typ Max Unit I (ON) ON-state leakage current per channel; V W = or ; = 5.5 V; see Figure 6 I CC quiescent supply current V I = or ; V W = or ; I O =0; = 5.5 V I CC additional quiescent supply current [] Typical values are measured at T amb =5 C. per input pin; V I = 0.6 V; V W = or ; I O = 0 ; = 5.5 V - - ±0 µ µ µ or I W B I W VW VO 00aad390 Fig 5. V W = or ; V O = or. Test circuit for measuring OFF-state current or I W B VW 00aad39 Fig 6. V W = or. Test circuit for measuring ON-state current _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

8 Table 9: Resistance R on t recommended operating conditions; voltages are referenced to (ground = 0 V); see test circuit Figure 7. ymbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C [] R ON(rail) ON resistance (rail) V W = I W = 4 m; =.65 V to.95 V Ω I W = 8 m; =.3 V to.7 V Ω I W = m; =.7 V Ω I W = 4 m; = 3 V to 3.6 V Ω I W = 3 m; = 4.5 V to 5.5 V Ω V W = I W = 4 m; =.65 V to.95 V - 30 Ω I W = 8 m; =.3 V to.7 V Ω I W = m; =.7 V Ω I W = 4 m; = 3 V to 3.6 V Ω I W = 3 m; = 4.5 V to 5.5 V Ω R ON(peak) ON resistance (peak) V W = to I W = 4 m; =.65 V to.95 V Ω I W = 8 m; =.3 V to.7 V Ω I W = m; =.7 V Ω I W = 4 m; = 3 V to 3.6 V Ω I W = 3 m; = 4.5 V to 5.5 V Ω R ON(flat) ON resistance (flatness) V W = to ; see Figure 9 I W = 4 m; =.65 V to.95 V Ω I W = 8 m; =.3 V to.7 V Ω I W = m; =.7 V Ω I W = 4 m; =3Vto3.6V Ω I W = 3 m; = 4.5 V to 5.5 V Ω T amb = 40 C to +5 C R ON(rail) ON resistance (rail) V W = I W = 4 m; =.65 V to.95 V Ω I W = 8 m; =.3 V to.7 V Ω I W = m; =.7 V - - Ω I W = 4 m; = 3 V to 3.6 V Ω I W = 3 m; = 4.5 V to 5.5 V Ω V W = I W = 4 m; =.65 V to.95 V Ω I W = 8 m; =.3 V to.7 V Ω I W = m; =.7 V Ω I W = 4 m; = 3 V to 3.6 V Ω I W = 3 m; = 4.5 V to 5.5 V Ω _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

9 Table 9: Resistance R on continued t recommended operating conditions; voltages are referenced to (ground = 0 V); see test circuit Figure 7. ymbol Parameter Conditions Min Typ Max Unit R ON(peak) ON resistance (peak) V W = to I W = 4 m; =.65 V to.95 V Ω I W = 8 m; =.3 V to.7 V Ω I W = m; =.7 V Ω I W = 4 m; = 3 V to 3.6 V Ω I W = 3 m; = 4.5 V to 5.5 V Ω [] Typical values are measured at T amb =5 C and nominal. VW or B VW IW 00aad39 Fig 7. R ON = V W / I W Test circuit for measuring ON resistance _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

10 40 00aad406 R ON (Ω) () () (3) (4) (5) V W (V) () =.8 V () =.5 V (3) =.7 V (4) = 3.3 V (5) = 5.0 V (6) T amb =5 C Fig 8. Typical ON resistance as a function of input voltage _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

11 80 00aad aad407 R ON (Ω) R ON (Ω) 60 () () 40 8 (3) (4) 0 () () (3) (4) V W (V) V W (V) () T amb = 5 C () T amb = 5 C () T amb =85 C () T amb =85 C (3) T amb =5 C (3) T amb =5 C (4) T amb = 40 C (4) T amb = 40 C a. =.8 V b. =.5 V 6 00aad aad409 R ON (Ω) R ON (Ω) () 8 () (3) 8 () () 4 (4) 4 (3) (4) V W (V) V W (V) () T amb = 5 C () T amb = 5 C () T amb =85 C () T amb =85 C (3) T amb =5 C (3) T amb =5 C (4) T amb = 40 C (4) T amb = 40 C c. =.7 V d. = 3.3 V Fig 9. witch ON resistance as a function of voltage _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January 006 of 3

12 . Dynamic characteristics Table 0: Dynamic characteristics t recommended operating conditions; voltages are referenced to (ground = 0 V); test circuit Figure. ymbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C [] t PHL HIGH-to-LOW propagation delay see Figure 0 to Bn or Bn to =.65 V to.95 V - - ns =.3 V to.7 V - -. ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns t PLH LOW-to-HIGH propagation delay see Figure 0 to Bn or Bn to =.65 V to.95 V - - ns =.3 V to.7 V - -. ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns t on turn-on time see Figure to or Bn =.65 V to.95 V ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns to or Bn =.65 V to.95 V ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns t off turn-off time see Figure to or Bn =.65 V to.95 V ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns to or Bn =.65 V to.95 V ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January 006 of 3

13 Table 0: Dynamic characteristics continued t recommended operating conditions; voltages are referenced to (ground = 0 V); test circuit Figure. ymbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +5 C t PHL HIGH-to-LOW propagation delay see Figure 0 to Bn or Bn to =.65 V to.95 V ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns t PLH LOW-to-HIGH propagation delay see Figure 0 to Bn or Bn to =.65 V to.95 V ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns t on turn-on time see Figure to or Bn =.65 V to.95 V ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns to or Bn =.65 V to.95 V.9-9. ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns t off turn-off time see Figure to or Bn =.65 V to.95 V. -.5 ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns to or Bn =.65 V to.95 V ns =.3 V to.7 V ns =.7 V ns = 3 V to 3.6 V ns = 4.5 V to 5.5 V ns [] Typical values are measured at T amb =5 C and nominal. _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

14 3. Waveforms Bn or input V I V M V M t PLH t PHL or Bn output V OH V OL V M V M 00aac36 Measurement points are given in Table. Logic levels: V OL and V OH are typical output voltage drop that occur with the output load. Fig 0. Input (Bn or ) to output ( or Bn) propagation delays V I, input V M t off t on, Bn, Bn output LOW to OFF OFF to LOW output HIGH to OFF OFF to HIGH V OL V OH t off V X V Y t on V M V M enabled disabled enabled 00aad393 Measurement points are given in Table. Logic levels: V OL and V OH are typical output voltage drop that occur with the output load. Fig. Turn-on and turn-off times Table : Measurement points upply voltage Input Output V M V M V X V Y.65 V to.7 V V OL V V OH 0.5 V.7 V to 5.5 V V OL V V OH 0.3 V _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

15 V XT PUL GNRTOR V I DUT V O RL RT CL RL mna66 Test data is given in Table. Definitions test circuit: R T = termination resistance (should be equal to output impedance Z o of the pulse generator). C L = load capacitance (including jig and probe capacitance). R L = load resistance. V XT = external voltage for measuring ing times. Fig. Load circuitry for ing times Table : Test data upply voltage Input Load V XT V I t r, t f C L R L t PLH, t PHL t on, t off HIGH to OFF OFF to HIGH LOW to OFF OFF to LOW.65 V to.95 V.0 ns 30 pf kω open.3 V to.7 V.0 ns 30 pf 500 Ω open.7 V.5 ns 50 pf 500 Ω open 3 V to 3.6 V.5 ns 50 pf 500 Ω open 4.5 V to 5.5 V.5 ns 50 pf 500 Ω open 4. dditional dynamic characteristics Table 3: dditional dynamic characteristics t recommended operating conditions; typical values measured at T amb =5 C. ymbol Parameter Conditions Min Typ Max Unit THD total harmonic distortion f i = 600 Hz to 0 khz; R L = 600 Ω; C L =50pF; V i = 0.5 V (p-p); see Figure 3 =.65 V % =.3 V % = 3.0 V % = 4.5 V % f (-3dB) 3 db frequency response R L =50Ω; C L = 5 pf; [] see Figure 4 =.65 V MHz =.3 V MHz = 3.0 V MHz = 4.5 V MHz _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

16 Table 3: dditional dynamic characteristics continued t recommended operating conditions; typical values measured at T amb =5 C. ymbol Parameter Conditions Min Typ Max Unit α OFF(ft) V ct(sw-sw) OFF-state feed-through attenuation crosstalk between es Q inj charge injection C L = 0. nf; V gen =0V; R gen =0Ω; f i = MHz; R L =MΩ; see Figure 7 R L =50Ω; C L = 5 pf; f i = 0 MHz; see Figure 5 =.65 V db =.3 V db = 3.0 V db = 4.5 V db R L =50Ω; C L = 5 pf; f i = 0 MHz; see Figure 6 =.65 V dbv =.3 V dbv = 3.0 V dbv = 4.5 V dbv =.8 V - < pc =.5 V pc = 3.3 V pc = 4.5 V pc = 5.5 V pc [] djust f i voltage to obtain 0 dbm level at output. Increase f i frequency until db meter reads 3 db. [] djust f i voltage to obtain 0 dbm level at input. [3] Definition: Q inj = V O C L. Guaranteed by design. [] [3] or 0. µf B 0.5 RL 0 µf fi 600 Ω CL D 00aad394 Fig 3. Test circuit for measuring total harmonic distortion _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

17 or 0. µf B 0.5 RL fi 50 Ω CL db 00aad395 Fig 4. Test circuit for measuring the frequency response when is in ON-state 0.5 RL 0.5 RL or 0. µf B fi 50 Ω CL db 00aad396 Fig 5. Test circuit for measuring feed-through attenuation when is in OFF-state 0.5 RL 0.5 RL test condition 0log0(V B /V I ) or 0. µf B 0log0(V /V I ) fi 50 Ω CL db 00aad397 Fig 6. Test circuit for measuring crosstalk between es _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

18 B Rgen logic input () V O RL CL Vgen 00aad398 logic () off input on off V O V O 00aac478 V O = output voltage variation R gen = generator resistance V gen = generator voltage Fig 7. Test circuit for measuring charge injection _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

19 5. Package outline VOP8: plastic very thin shrink small outline package; 8 leads; body width.3 mm OT765- D X c y H v M Z 8 5 Q pin index ( 3 ) L p θ 4 detail X L e b p w M mm scale DIMNION (mm are the original dimensions) UNIT max. mm b p c D () () e H L L p Q v w y Z () θ Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included.. Plastic or metal protrusions of 0.5 mm maximum per side are not included OUTLIN VRION RFRNC IC JDC JIT UROPN PROJCTION IU DT OT765- MO Fig 8. Package outline OT765- (VOP8) _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

20 XON8: plastic extremely thin small outline package; no leads; 8 terminals; body x.95 x 0.5 mm OT833- b 3 4 L L 4 () e e e e 8 () D terminal index area 0 mm DIMNION (mm are the original dimensions) scale UNIT () max max b D e e L L mm Notes. Including plating thickness.. Can be visible in some manufacturing processes. OUTLIN VRION RFRNC IC JDC JIT UROPN PROJCTION IU DT OT MO Fig 9. Package outline OT833- (XON8) _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January of 3

21 6. bbreviations Table 4: cronym CMO TTL HBM D MM CDM DUT bbreviations Description Complementary Metal Oxide emiconductor Transistor Transistor Logic Human Body Model lectrotatic Discharge Machine Model Charged Device Model Device Under Test 7. Revision history Table 5: Revision history Document ID Release date Data sheet status Change notice Doc. number upersedes _ Product data sheet _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January 006 of 3

22 8. Data sheet status Level Data sheet status [] Product status [] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips emiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. upplementary data will be published at a later date. Philips emiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips emiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [] Please consult the most recently issued data sheet before initiating or completing a design. [] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 9. Definitions hort-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating ystem (IC 6034). tress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. xposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips emiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 0. Disclaimers customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips emiconductors for any damages resulting from such application. Right to make changes Philips emiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips emiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.. Trademarks Notice ll referenced brands, product names, service names and trademarks are the property of their respective owners. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips emiconductors. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ _ Koninklijke Philips lectronics N.V ll rights reserved. Product data sheet Rev. 0 0 January 006 of 3

23 3. Contents General description Features Quick reference data Ordering information Marking Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions tatic characteristics Dynamic characteristics Waveforms dditional dynamic characteristics Package outline bbreviations Revision history Data sheet status Definitions Disclaimers Trademarks Contact information Koninklijke Philips lectronics N.V. 006 ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 0 January 006 Document number: _ Published in The Netherlands

8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).

8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground). Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and

More information

74HC1G125; 74HCT1G125

74HC1G125; 74HCT1G125 Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state

More information

The 74HC21 provide the 4-input AND function.

The 74HC21 provide the 4-input AND function. Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).

More information

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting 3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible

More information

Hex inverting Schmitt trigger with 5 V tolerant input

Hex inverting Schmitt trigger with 5 V tolerant input Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible

More information

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses. Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance

More information

2-input EXCLUSIVE-OR gate

2-input EXCLUSIVE-OR gate Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output

More information

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1. Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance

More information

14-stage binary ripple counter

14-stage binary ripple counter Rev. 01 29 November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020.

More information

8-bit binary counter with output register; 3-state

8-bit binary counter with output register; 3-state Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It

More information

2-channel analog multiplexer/demultiplexer

2-channel analog multiplexer/demultiplexer Rev. 6 January 08 Product data sheet General description Features and benefits The is a low-power, low-voltage, high-speed, i-gate CMO device. The provides one analog multiplexer/demultiplexer with a digital

More information

The 74LVC1G11 provides a single 3-input AND gate.

The 74LVC1G11 provides a single 3-input AND gate. Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input

More information

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance

More information

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device. 74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function

More information

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver. 16-bit dual supply translating transciever; 3-state Rev. 02 1 June 2004 Product data sheet 1. General description 2. Features The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior

More information

74HC244; 74HCT244. Octal buffer/line driver; 3-state

74HC244; 74HCT244. Octal buffer/line driver; 3-state Rev. 03 22 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

More information

The 74LVC1G02 provides the single 2-input NOR function.

The 74LVC1G02 provides the single 2-input NOR function. Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use

More information

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs. Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

More information

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They

More information

8-bit serial-in/parallel-out shift register

8-bit serial-in/parallel-out shift register Rev. 03 4 February 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164.

More information

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This

More information

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86. Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.

More information

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02. Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0

More information

INTEGRATED CIRCUITS. PCK2002P 533 MHz PCI-X clock buffer. Product data Supersedes data of 2001 May Dec 13. Philips Semiconductors

INTEGRATED CIRCUITS. PCK2002P 533 MHz PCI-X clock buffer. Product data Supersedes data of 2001 May Dec 13. Philips Semiconductors INTEGRATED CIRCUITS Supersedes data of 2001 May 09 2002 Dec 13 Philips Semiconductors FEATURES General purpose and PCI-X 1:4 clock buffer 8-pin TSSOP package See PCK2001 for 48-pin 1:18 buffer part See

More information

8-channel analog multiplexer/demultiplexer with injection-current effect control

8-channel analog multiplexer/demultiplexer with injection-current effect control 8-channel analog multiplexer/demultiplexer with injection-current effect control Rev. 01 9 March 2007 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is

More information

74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop.

74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop. Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.

More information

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 24 January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

More information

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified

More information

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output

More information

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers. Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0

More information

74AHC1G00; 74AHCT1G00

74AHC1G00; 74AHCT1G00 74HC1G00; 74HCT1G00 Rev. 06 30 May 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G00 and 74HCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input

More information

74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state

74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state Rev. 03 20 January 2006 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with

More information

The 74LV32 provides a quad 2-input OR function.

The 74LV32 provides a quad 2-input OR function. Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.

More information

DATA SHEET. 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS

DATA SHEET. 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET 16-bit D-type transparent latch with 5 V Supersedes data of 2002 Oct 02 2003 Dec 08 FEATURES 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage

More information

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC393; 74HCT393. Dual 4-bit binary ripple counter Rev. 03 6 September 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky

More information

2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1. Rev. 1 17 November 25 Product data sheet 1. Product profile 1.1 General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features

More information

74AHC1G66; 74AHCT1G66

74AHC1G66; 74AHCT1G66 Rev. 04 18 December 2008 Product data sheet 1. General description 2. Features 3. Ordering information 74AHC1G66 and 74AHCT1G66 are high-speed Si-gate CMOS devices. They are single-pole single-throw analog

More information

2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1. Rev. 3 28 April 26 Product data sheet. Product profile. General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology..2 Features Logic level

More information

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer

More information

PMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1.

PMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1. Rev. 2 24 March 25 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features

More information

Octal bus transceiver; 3-state

Octal bus transceiver; 3-state Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive

More information

74AHC2G126; 74AHCT2G126

74AHC2G126; 74AHCT2G126 Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line

More information

NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD) plastic package.

NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD) plastic package. Rev. 02 14 July 2005 Product data sheet 1. Product profile 1.1 General description NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD)

More information

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

74AHC14; 74AHCT14. Hex inverting Schmitt trigger Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

More information

8-channel analog multiplexer/demultiplexer

8-channel analog multiplexer/demultiplexer Rev. 04 10 ugust 2009 Product data sheet 1. General description 2. Features The is an with three digital select inputs (S0 to S2), an active-low enable input (), eight independent inputs/outputs (Y0 to

More information

PMV65XP. 1. Product profile. 2. Pinning information. P-channel TrenchMOS extremely low level FET. 1.1 General description. 1.

PMV65XP. 1. Product profile. 2. Pinning information. P-channel TrenchMOS extremely low level FET. 1.1 General description. 1. Rev. 1 28 September 24 Product data sheet 1. Product profile 1.1 General description P-channel enhancement mode field effect transistor in a plastic package using TrenchMOS technology. 1.2 Features Low

More information

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function. Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They

More information

2-channel analog multiplexer/demultiplexer

2-channel analog multiplexer/demultiplexer Rev. 3 6 eptember 00 Product data sheet. General description The provides one analog multiplexer/demultiplexer with one digital select input (), two independent inputs/outputs (, Y) and a common input/output

More information

N-channel TrenchMOS logic level FET

N-channel TrenchMOS logic level FET M3D315 Rev. 3 23 January 24 Product data 1. Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. 2. Features Low on-state resistance Fast switching

More information

2-channel analog multiplexer/demultiplexer

2-channel analog multiplexer/demultiplexer Rev. 5 6 December 0 Product data sheet. General description The provides one analog multiplexer/demultiplexer with one digital select input (), two independent inputs/outputs (, Y) and a common input/output

More information

74AHC1G14; 74AHCT1G14

74AHC1G14; 74AHCT1G14 Rev. 6 18 May 29 Product data sheet 1. General description 2. Features 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt

More information

DATA SHEET. PH2369 NPN switching transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr Oct 11.

DATA SHEET. PH2369 NPN switching transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr Oct 11. DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D186 Supersedes data of 1999 Apr 27 2004 Oct 11 FEATURES Low current (max. 200 ma) Low voltage (max. 15 V). APPLICATIONS High-speed switching. PINNING

More information

DISCRETE SEMICONDUCTORS DATA SHEET. PMBT3906 PNP switching transistor. Product specification Supersedes data of 1999 Apr 27.

DISCRETE SEMICONDUCTORS DATA SHEET. PMBT3906 PNP switching transistor. Product specification Supersedes data of 1999 Apr 27. DISCRETE SEMICONDUCTORS DATA SHEET Supersedes data of 1999 Apr 27 2004 Jan 21 FEATURES Collector current capability I C = 200 ma Collector-emitter voltage V CEO = 40 V. APPLICATIONS General amplification

More information

INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23

INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23 INTEGRTED CIRCUITS DT SHEET Supersedes data of 993 Sep 0 2003 Jul 23 FETURES Complies with JEDEC standard no. 8- ESD protection: HBM EI/JESD22-4- exceeds 2000 V MM EI/JESD22-5- exceeds 200 V. Specified

More information

74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state

74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state Rev. 06 6 March 2006 Product data sheet. General description 2. Features 3. Quick reference data The is a high-performance BiCMOS product designed for V CC operation at 3.3 V. This device combines low

More information

DATA SHEET. 74LVC16374A; 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS

DATA SHEET. 74LVC16374A; 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Supersedes data of 1998 Mar 17 2003 Dec 12 FEATURES 5 V tolerant inputs/outputs for interfacing

More information

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state Rev. 04 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They

More information

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device. Rev. 03 12 November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state

More information

DISCRETE SEMICONDUCTORS DATA SHEET M3D071. BAT74 Schottky barrier double diode. Product specification Supersedes data of 1996 Mar 19.

DISCRETE SEMICONDUCTORS DATA SHEET M3D071. BAT74 Schottky barrier double diode. Product specification Supersedes data of 1996 Mar 19. DISCRETE SEMICONDUCTORS DATA SHEET M3D07 Supersedes data of 996 Mar 9 200 Sep 05 FEATURES Low forward voltage Guard ring protected Small plastic SMD package. APPLICATIONS Ultra high-speed switching Voltage

More information

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28 INTEGRATED CIRCUITS -to-8 line decoder/demultiplexer; inverting 998 Apr 8 FEATURES Wide supply voltage range of. to. V In accordance with JEDEC standard no. 8-A Inputs accept voltages up to. V CMOS lower

More information

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook. INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels

More information

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function. Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible

More information

PMV40UN. 1. Product profile. 2. Pinning information. TrenchMOS ultra low level FET. 1.1 Description. 1.2 Features. 1.

PMV40UN. 1. Product profile. 2. Pinning information. TrenchMOS ultra low level FET. 1.1 Description. 1.2 Features. 1. M3D88 Rev. 1 5 August 23 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. Product availability: in SOT23.

More information

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads; Rev. 06 4 June 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (P) inputs, set (SD)

More information

SI Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.

SI Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1. M3D35 Rev. 2 7 February 24 Product data. Product profile. Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology..2 Features Low gate charge Low

More information

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device. Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state

More information

BF545A; BF545B; BF545C

BF545A; BF545B; BF545C Rev. 3 5 August 24 Product data sheet. Product profile. General description N-channel symmetrical silicon junction field-effect transistors in a SOT23 package. CAUTION This device is sensitive to electrostatic

More information

74HC164; 74HCT bit serial-in, parallel-out shift register

74HC164; 74HCT bit serial-in, parallel-out shift register Rev. 03 4 pril 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They

More information

PMV56XN. 1. Product profile. 2. Pinning information. µtrenchmos extremely low level FET. 1.1 Description. 1.2 Features. 1.

PMV56XN. 1. Product profile. 2. Pinning information. µtrenchmos extremely low level FET. 1.1 Description. 1.2 Features. 1. M3D88 Rev. 2 24 June 24 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. 1.2 Features TrenchMOS technology

More information

µtrenchmos standard level FET Low on-state resistance in a small surface mount package. DC-to-DC primary side switching.

µtrenchmos standard level FET Low on-state resistance in a small surface mount package. DC-to-DC primary side switching. M3D88 Rev. 2 19 February 23 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. Product availability: in

More information

PMN40LN. 1. Description. 2. Features. 3. Applications. 4. Pinning information. TrenchMOS logic level FET

PMN40LN. 1. Description. 2. Features. 3. Applications. 4. Pinning information. TrenchMOS logic level FET M3D32 Rev. 1 13 November 22 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS technology. Product availability: in SOT457 (TSOP6). 2.

More information

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook. INTEGRATED CIRCUITS Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels

More information

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation: Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance

More information

74LV General description. 2. Features. 8-bit addressable latch

74LV General description. 2. Features. 8-bit addressable latch Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed

More information

PHT6N06T. 1. Product profile. 2. Pinning information. TrenchMOS standard level FET. 1.1 Description. 1.2 Features. 1.

PHT6N06T. 1. Product profile. 2. Pinning information. TrenchMOS standard level FET. 1.1 Description. 1.2 Features. 1. M3D87 Rev. 2 3 February 23 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. Product availability: in SOT223.

More information

3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state

3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state with 30 Ω termination resistors; 3-state Rev. 03 17 January 2005 Product data sheet 1. General description 2. Features The is a high performance BiCMOS product designed for V CC operation at 3.3 V. The

More information

DATA SHEET. BC368 NPN medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Dec 01.

DATA SHEET. BC368 NPN medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Dec 01. DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D86 Supersedes data of 2003 Dec 0 2004 Nov 05 FEATURES High current. APPLICATIONS Linear voltage regulators Low side switch Supply line switch for negative

More information

DATA SHEET. BC856; BC857; BC858 PNP general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Apr 09

DATA SHEET. BC856; BC857; BC858 PNP general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Apr 09 DISCRETE SEMICONDUCTORS DATA SHEET Supersedes data of 23 Apr 9 24 Jan 16 FEATURES Low current (max. 1 ma) Low voltage (max. 65 V). APPLICATIONS General purpose switching and amplification. PINNING PIN

More information

PSMN002-25P; PSMN002-25B

PSMN002-25P; PSMN002-25B PSMN2-25P; PSMN2-25B Rev. 1 22 October 21 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS 1 technology. Product availability: PSMN2-25P

More information

DATA SHEET. BC846; BC847; BC848 NPN general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2002 Feb 04

DATA SHEET. BC846; BC847; BC848 NPN general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2002 Feb 04 DISCRETE SEMICONDUCTORS DATA SHEET Supersedes data of 22 Feb 4 24 Feb 6 FEATURES Low current (max. 1 ma) Low voltage (max. 65 V). APPLICATIONS General purpose switching and amplification. PINNING PIN 1

More information

N-channel µtrenchmos ultra low level FET. Top view MBK090 SOT416 (SC-75)

N-channel µtrenchmos ultra low level FET. Top view MBK090 SOT416 (SC-75) M3D73 Rev. 3 March 24 Product data. Product profile. Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology..2 Features Surface mounted package Low

More information

DATA SHEET. BSN304 N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 17

DATA SHEET. BSN304 N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 17 DISCRETE SEMICONDUCTORS DATA SHEET age M3D6 Supersedes data of 997 Jun 7 2 Dec FEATURES PINNING - TO-92 variant Direct interface to C-MOS, TTL, etc. High-speed switching No secondary breakdown. APPLICATIONS

More information

TrenchMOS technology Very fast switching Logic level compatible Subminiature surface mount package.

TrenchMOS technology Very fast switching Logic level compatible Subminiature surface mount package. M3D88 Rev. 2 2 November 21 Product data 1. Description in a plastic package using TrenchMOS 1 technology. Product availability: in SOT23. 2. Features TrenchMOS technology Very fast switching Logic level

More information

INTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26.

INTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26. INTEGRTED CIRCUITS DT SHEET Quad 2-input NND gate Supersedes data of 1997 ug 26 2003 Jun 30 Quad 2-input NND gate FETURES Complies with JEDEC standard no. 8-1 ESD protection: HBM EI/JESD22-114- exceeds

More information

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook INTEGRATED CIRCUITS 1998 Jun 23 IC24 Data Handbook FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground

More information

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20 DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D19 Supersedes data of 1997 Jun 2 22 May 22 FEATURES Direct interface to C-MOS, TTL, etc. High-speed switching No secondary breakdown. APPLICATIONS Line

More information

DATA SHEET. BC369 PNP medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Nov 20.

DATA SHEET. BC369 PNP medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Nov 20. DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D186 Supersedes data of 23 Nov 2 24 Nov 5 FEATURES High current Two current gain selections. APPLICATIONS Linear voltage regulators High side switches

More information

DATA SHEET. BC856; BC857; BC858 PNP general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr 12

DATA SHEET. BC856; BC857; BC858 PNP general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr 12 DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D88 Supersedes data of 1999 Apr 12 22 Feb 4 FEATURES Low current (max. 1 ma) Low voltage (max. 65 V). APPLICATIONS General purpose switching and amplification.

More information

DATA SHEET. BSN254; BSN254A N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS

DATA SHEET. BSN254; BSN254A N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D186 Supersedes data of 1997 Jun 23 22 Feb 19 FEATURES Direct interface to C-MOS, TTL, etc. High-speed switching No secondary breakdown Low R DSon. APPLICATIONS

More information

PHD110NQ03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.

PHD110NQ03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1. M3D3 Rev. 1 16 June 24 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. 1.2 Features Logic level threshold

More information

NX3L1G3157-Q100. Low-ohmic single-pole double-throw analog switch

NX3L1G3157-Q100. Low-ohmic single-pole double-throw analog switch Rev. 1 3 May 013 Product data sheet 1. General description The is a low-ohmic single-pole double-throw analog suitable for use as an analog or digital :1 multiplexer/demultiplexer. It has a digital select

More information

Dual 2-to-4 line decoder/demultiplexer

Dual 2-to-4 line decoder/demultiplexer 74LV9 Rev. 04 December 007 Product data sheet. General description. Features. Ordering information The 74LV9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC9 and 74HCT9.

More information

PSMN004-60P/60B. PSMN004-60P in SOT78 (TO-220AB) PSMN004-60B in SOT404 (D 2 -PAK).

PSMN004-60P/60B. PSMN004-60P in SOT78 (TO-220AB) PSMN004-60B in SOT404 (D 2 -PAK). Rev. 1 26 April 22 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS technology. Product availability: PSMN4-6P in SOT78 (TO-22AB) PSMN4-6B

More information

IRFR Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field effect transistor

IRFR Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field effect transistor M3D3 Rev. 4 August Product data. Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. Product availability: in SOT48 (D-PAK).. Features Fast switching

More information

Octal D-type transparent latch; 3-state

Octal D-type transparent latch; 3-state Rev. 02 18 October 2007 Product data sheet 1. General description 2. Features The is an octal -type transparent latch featuring separate -type inputs for each latch and 3-state true outputs for bus-oriented

More information

TrenchMOS ultra low level FET

TrenchMOS ultra low level FET M3D32 Rev. 1 27 September 22 Product data 1. Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. Product availability: in SOT457 (TSOP6). 2.

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device. Rev. 3 8 May 29 Product data sheet 1. General description 2. Features 3. pplications 4. Ordering information The is a high-speed Si-gate CMOS device. The provides three inverting buffers with Schmitt trigger

More information

DATA SHEET. BC846W; BC847W; BC848W NPN general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr 23

DATA SHEET. BC846W; BC847W; BC848W NPN general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr 23 DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D12 Supersedes data of 1999 Apr 23 22 Feb 4 FEATURES Low current (max. 1 ma) Low voltage (max. 65 V). APPLICATIONS General purpose switching and amplification.

More information