64Mb Synchronous DRAM Specification

Transcription

1 Specification P2V64S2DTP P2V64S3DTP P2V64S4DTP Deutron Electronics Corp. 8F, 68, SEC. 3, NANKING E. RD., TAIPEI 4, TAIWAN, R. O. C. TEL : FA : http: //

2 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) ORDERING INFORMATION Frequency Speed(ns) Order Part Number Type Standard Low Power Pb-Free Low Power and Pb-Free Package 66MHz 6 P2V64S2/3/4 DTP -6-6L -G6 -G6L 4mil TSOP-2 43MHz 7 P2V64S2/3/4 DTP -7-7L -G7 -G7L 4mil TSOP-2 33MHz 7.5 P2V64S2/3/4 DTP L -G75 -G75L 4mil TSOP-2 25MHz 8 P2V64S2/3/4 DTP -8-8L -G8 -G8L 4mil TSOP-2 Type Designation Code P2 V 64 S 3 D TP - G 6 L Special Function L : Low Power, Blank : Standard Access Item -6 : 6 ns (66MHz/3-3-3) -7 : 7 ns (43MHz/3-3-3) -75 : 7.5ns (MHz/2-2-2 or 33MHz/3-3-3) -8 : 8 ns (MHz/2-2-2 or 25MHz/3-3-3) Package Type Process Generation Function Organization Synchronous DRAM Density TP : TSOP(II) ; G : Pb - Free D : 5th generation : Random Column 2 : x4, 3: x8, 4: x6 64 :64Mbit Interface V : LVTTL MIRA DRAM Sep.23

3 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) P2V64S2DTP (4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) PRELIMINAR Some of contents are described for general products and are subject to change without notice. DESCRIPTION P2V64S2DTP is organized as 4-bank x 4,94,34-word x 4-bit Synchronous DRAM with LVTTL interface and P2V64S3DTP is organized as 4-bank x 2,97,52-word x 8-bit and P2V64S4DTP is organized as 4-bank x,48,576-word x 6-bit. All inputs and outputs are referenced to the rising edge of. P2V64S2DTP,P2V64S3DTP and P2V64S4DTP achieve very high speed data rates up to 66MHz, and are suitable for main memories or graphic memories in computer systems. FEATURES t tras tac trc ITEM Clock Cycle Time (Min.) Active to Precharge Period (Min.) Row to Column Delay (Min.) Access Time from (Max.) Ref /Active Period (Min.) CL=2 CL=3 CL=2 CL= ns 42ns 8ns - 5ns 6ns P2V64S2/3/4DTP L - 7ns 45ns 2ns - 5.4ns 63ns ns ns 7.5ns 7.5ns 45ns 45ns 2ns 2ns 6ns 6ns 5.4ns 5.4ns 67.5ns 67.5ns -8 ns 8ns 48ns 2ns 6ns 6ns 7ns Icc Icc6 Operation Current (Single Bank) Self Refresh Current (Max.) (Max.) V64S2D V64S3D V64S4D 85mA 85mA 85mA ma 85mA 85mA 85mA ma 85mA 85mA 85mA ma 85mA 85mA 85mA.5mA 85mA 85mA 85mA ma - Single 3.3V ±.3V power supply - Max. Clock frequency : -6:66MHz<3-3-3>/-7:43MHz<3-3-3>/-75:33MHz<3-3-3>/-8:MHz<2-2-2> - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA,BA(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- /2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- ML and MU (P2V64S4DTP) - Random column access - Auto precharge / All bank precharge controlled by A - Auto and self refresh refresh cycles /64ms - LVTTL Interface - Package P2V64S2DTP/3DTP/4DTP 4-mil, 54-pin Thin Small Outline (TSOP II) with.8mm lead pitch Sep.23 Page-

4 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) PIN CONFIGURATION (TOP VIEW) P2V64S2DTP P2V64S3DTP P2V64S4DTP PIN CONFIGURATION (TOP VIEW) Vdd VddQ VssQ VddQ VssQ Vdd /WE /CAS /RAS /CS BA(A3) BA(A2) A(AP) A A A2 A3 Vdd Vdd VddQ VssQ 2 VddQ 3 VssQ Vdd /WE /CAS /RAS /CS BA(A3) BA(A2) A(AP) A A A2 A3 Vdd Vdd VddQ 2 VssQ 3 4 VddQ 5 6 VssQ 7 Vdd ML /WE /CAS /RAS /CS BA(A3) BA(A2) A(AP) A A A2 A3 Vdd mil 54pin TSOP(II) Vss 5 VssQ 4 3 VddQ 2 VssQ 9 VddQ 8 Vss MU A A9 A8 A7 A6 A5 A4 Vss Vss 7 VssQ 6 VddQ 5 VssQ 4 VddQ Vss M A A9 A8 A7 A6 A5 A4 Vss Vss VssQ 3 VddQ VssQ 2 VddQ Vss M A A9 A8 A7 A6 A5 A4 Vss /CS /RAS /CAS /WE -5 : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O M : Output Disable / Write Mask A- : Address Input BA, Vdd : Bank Address : Power Supply VddQ : Power Supply for Output Vss : Ground VssQ : Ground for Output Sep.23 Page-2

5 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) BLOCK DIAGRAM -7 I/O Buffer Memory Array 496 x52 x8 Cell Array Bank # Memory Array 496 x52 x8 Memory Array 496 x52 x8 Memory Array 496 x52 x8 Cell Array Cell Array Cell Array Bank # Bank #2 Bank #3 Mode Register Control Circuitry Address Buffer Control Signal Buffer Clock Buffer A- BA, /CS /RAS /CAS /WE M Note:This figure shows the P2V64S3DTP The P2V64S2DTP configuration is 496x24x4 of cell array and -3 The P2V64S4DTP configuration is 469x256x6 of cell array and -5 Type Designation Code P2 V 64 S 3 D T -8-6 : 6 ns (66MHz/3-3-3) Access Item -7 : 7 ns (43MHz/3-3-3) -75 : 7.5ns (MHz/2-2-2 or 33MHz/3-3-3) -75L : 7.5ns (MHz/2-2-2 or 33MHz/3-3-3) -8 : 8 ns (MHz/2-2-2 or 25MHz/3-3-3) Package Type TP : TSOP(II) Process Generation D : 5th generation Function : Random Column Organization 2 : x4, 3: x8, 4: x6 Synchronous DRAM Density 64 : 64Mbit Interface V :LVTTL MIRA DRAM Sep.23 Page-3

6 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) PIN FUTION Input Master Clock: All other inputs are referenced to the rising edge of Input Clock Enable: controls internal clock.when is low, internal clock for the following cycle is ceased. is also used to select auto / self-refresh. After self-refresh mode is started, becomes asynchronous input. Self-refresh is maintained as long as is low. /CS Input Chip Select: When /CS is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. A- Input A- specify the Row / Column Address in conjunction with BA,. The Row Address is specified by A-. The Column Address is specified by A-9(x4)/A-8(x8)/A-7(x6). A is also used to indicate precharge option. When A is high at a read / write command, an auto precharge is performed. When A is high at a precharge command, all banks are precharged. BA, -3(x4), -7(x8), -5(x6) M(x4,x8), MU/L(x6) Input Input / Output Input Bank Address: BA, specifies one of four banks to which a command is applied. BA, must be set with ACT, PRE,, WRITE commands. Data In and Data out are referenced to the rising edge of. Din Mask / Output Disable: When M(U/L) is high in burst write, Din for the current cycle is masked. When M(U/L) is high in burst read, Dout is disabled at the next but one cycle. Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only. Sep.23 Page-4

7 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) BASIC FUTIONS The P2V64S2, 3 and 4DTP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at rising edge. In addition to 3 signals, /CS, and A are used as chip select, refresh opt ion, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. /CS /RAS Chip Select : L=select, H=deselect /CAS /WE define basic command A Refresh refresh command Precharge precharge or read/write command Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read () [/RAS =H, /CAS =L, /WE =H] command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A =H at this command, the bank is deactivated after the burst read (auto-precharge, A). Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A =H at this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE = =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. Sep.23 Page-5

8 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) COMMAND TRUTH TABLE COMMAND MNEMONIC n- n /CS /RAS /CAS /WE BA, A A A-9 Deselect DESEL H H No Operation NOP H L H H H Row Address Entry & Bank Active Single Bank Precharge ACT H L L H H V V V V PRE H L L H L V L Precharge All Banks Column Address Entry &Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge PREA H L L H L H WRITE H L H L L V V L V WRITE A H L H L L V V H V H L H L H V V L V A H L H L H V V H V Auto-Refresh REFA H H L L L H Self-Refresh Entry REFS H L L L L H Self-Refresh Exit REFS L H H L H L H H H Burst Terminate TBST H L H H L Mode Register Set MRS H L L L L L L L V* H=High Level, L=Low Level, V=Valid, =Don't Care, n= cycle number NOTE:. A7-A9 =, A-A6 =Mode Address Sep.23 Page-6

9 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) FUTION TRUTH TABLE Current State /CS /RAS /CAS /WE Address Action IDLE H DESEL NOP L H H H NOP NOP L H H L TBST ILLEGAL*2 L H L BA, CA, A / WRITE ILLEGAL*2 L L H H BA, RA ACT Bank Active, Latch RA L L H L BA, A PRE / PREA NOP*4 L L L H REFA Auto-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 ROW ACTIVE H DESEL NOP L H H H NOP NOP L H H L TBST NOP L H L H BA, CA, A L H L L BA, CA, A / A WRITE / WRITEA Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA Precharge / Precharge All L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Sep.23 Page-7

10 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) FUTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Action H DESEL NOP (Continue Burst to END) L H H H NOP NOP (Continue Burst to END) L H H L TBST Terminate Burst L H L H BA, CA, A L H L L BA, CA, A /A WRITE / WRITEA Terminate Burst, Latch CA,Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA Terminate Burst, Precharge L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE H DESEL NOP (Continue Burst to END) L H H H NOP NOP (Continue Burst to END) L H H L TBST Terminate Burst, Latch CA,Begin L H L H BA, CA, A L H L L BA, CA, A / A WRITE / WRITEA Terminate Burst, Latch CA,Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA Terminate Burst, Precharge L L L H REFA ILLEGAL Op-Code, L L L L MRS ILLEGAL Mode-Add Sep.23 Page-8

11 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) FUTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Action with AUTO PRECHARGE H DESEL L H H H NOP NOP (Continue Burst to END) NOP (Continue Burst to END) L H H L TBST ILLEGAL L H L H BA, CA, A / A L H L L BA, CA, A WRITE / WRITEA L L H H BA, RA ACT ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA ILLEGAL*2 L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE with AUTO PRECHARGE H DESEL NOP (Continue Burst to END) L H H H NOP NOP (Continue Burst to END) L H H L TBST ILLEGAL L H L H BA, CA, A L H L L BA, CA, A / A WRITE / WRITEA ILLEGAL ILLEGAL L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA ILLEGAL*2 L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Sep.23 Page-9

12 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) FUTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Action PRE - CHARGING H DESEL NOP (Idle after trp) L H H H NOP NOP (Idle after trp) L H H L TBST ILLEGAL*2 L H L BA, CA, A / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A PRE / PREA NOP*4 (Idle after trp) L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING H DESEL NOP (Row Active after ) L H H H NOP NOP (Row Active after ) L H H L TBST ILLEGAL*2 L H L BA, CA, A / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A PRE / PREA ILLEGAL*2 L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Sep.23 Page-

13 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) FUTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Action WRITE RECOVERING H DESEL NOP L H H H NOP NOP L H H L TBST ILLEGAL*2 L H L BA, CA, A / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A PRE / PREA ILLEGAL*2 L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL REFRESHING H DESEL NOP (Idle after trc) L H H H NOP NOP (Idle after trc) L H H L TBST ILLEGAL L H L BA, CA, A / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A PRE / PREA ILLEGAL L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Sep.23 Page-

14 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) FUTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Action MODE REGISTER SETTING H DESEL NOP (Idle after trsc) L H H H NOP NOP (Idle after trsc) L H H L TBST ILLEGAL L H L BA, CA, A / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A PRE / PREA ILLEGAL L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Sep.23 Page-2

15 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) FUTION TRUTH TABLE for Current State SELF- REFRESH* n- n /CS /RAS /CAS /WE Add Action H INVALID L H H Exit Self-Refresh (Idle after trc) L H L H H H Exit Self-Refresh (Idle after trc) L H L H H L ILLEGAL L H L H L ILLEGAL L H L L ILLEGAL L L NOP (Maintain Self-Refresh) POWER DOWN H INVALID L H Exit Power Down to Idle L L NOP (Maintain Power Down) ALL BANKS IDLE*2 H H Refer to Function Truth Table H L L L L H Enter Self-Refresh H L H Enter Power Down H L L H H H Enter Power Down H L L H H L ILLEGAL H L L H L ILLEGAL H L L L ILLEGAL L Refer to Current State =Power Down AN STATE other than listed above H H Refer to Function Truth Table H L Begin Susspend at Next Cycle*3 L H Exit Susspend at Next Cycle*3 L L Maintain Suspend ABBREVIATIONS: H=High Level, L=Low Level, =Don't Care NOTES:. Low to High transition will re-enable and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. Sep.23 Page-3

16 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) SIMPLIFIED STATE DIAGRAM SELF REFRESH REFS REFS MODE REGISTER SET MRS IDLE REFA AUTO REFRESH L SUSPEND L ACT H POWER DOWN H TERM WRITE ROW ACTIVE TERM WRITE SUSPEND L H WRITE WRITEA WRITE A L H SUSPEND WRITEA A WRITEA A WRITEA SUSPEND L H WRITEA PRE PRE PRE A L H A SUSPEND POWER APPLIED POWER ON PRE PRE CHARGE Automatic Sequence Sequence Sep.23 Page-4

17 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) POWER ON SEQUEE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.. Apply power and start clock. Attempt to maintain high, M high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 2µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After trsc from a MRS command, the SDRAM is ready for new command. /CS /RAS /CAS /WE BA, A-A V BA BA A A A9 A8 A7 A6 A5 A4 A3 A2 A A WM LTMODE BT BL CL Write Mode /CAS LATE R R Burst Write Single Write BURST LENGTH BL BT= BT= R R LATE MODE 2 3 R R R R BURST TPE R R FP SEQUENTIAL INTERLEAVED R R R R: Reserved for Future Use FP: Full Page Sep.23 Page-5

18 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Address Read Write Q Q Q2 Q3 D D D2 D3 CL= 3 BL= 4 /CAS Latency Burst Length Burst Length Burst Type Initial Address BL Column Addressing A2 A A Sequential Interleaved Sep.23 Page-6

19 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) OPERATIONAL DESCRIPTION BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA,). A row is indicated by the row addresses A-. The minimum activation interval between one bank and the other bank is trrd. Maximum 2 ACT commands are allowed within trc, although the number of banks which are active concurrently is not limited. PRECHARGE The PRE command deactivates the bank indicated by BA,. When multiple banks are active, the precharge all command (PREA, PRE + A=H) is available to deactivate them at the same time. After trp from the precharge, an ACT command to the same bank can be issued. After from the bank activation, a command can be issued. st output data is available after the /CAS Latency from the, followed by (BL -) consecutive data when the Burst Length is BL. The start address is specified by A-A9(x4), A-8(8), A-7 (6), and the address sequence of burst data is defined by the Burst Type. A command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. When A is high at a command, the auto-precharge (A) is performed. Any command (, WRITE, PRE, TBST, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after A. (Need to keep tras min.) The next ACT command can be issued after (BL + trp) from the previous A. Bank Activation and Precharge All (BL=4, CL=3) 2 ACT command / trcmin trcmin ACT ACT PRE ACT trrd tras trp A-9 a b b A a b b A a b b BA, Qa Qa Qa2 Qa3 Precharge all Sep.23 Page-7

20 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Multi Bank Interleaving (BL=4, CL=3) A-9 ACT a ACT b PRE A a b A a b BA, /CAS latency with Auto-Precharge (BL=4, CL=3) Qa Qa Qa2 Qa3 Qb Qb Qb2 Burst Length BL + trp A-9 ACT a BL trp ACT a A a a A a a BA, Qa Qa Qa2 Qa3 Auto-Precharge Timing (BL=4) Internal precharge start ACT CL=3 BL Qa Qa Qa2 Qa3 CL=2 Qa Qa Qa2 Qa3 Internal Precharge Start Timing Sep.23 Page-8

21 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) WRITE After from the bank activation, a WRITE command can be issued. st input data is set at the same cycle as the WRITE. Following (BL -) data are written into the RAM, when the Burst Length is BL. The start address is specified by A-A9(x4), A-8(8), A-7(6) and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (twr) is required. When A is high at a WRITE command, the autoprecharge (WRITEA) is performed. Any command (, WRITE, PRE, TBST, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at twr after the last input data cycle. (Need to keep tras min.) The next ACT command can be issued after trp from the internal precharge timing. WRITE with Auto-Precharge (BL=4) A-9 ACT a Write ACT b Write PRE PRE A a a b A a b a BA, Da Da Da2 Da3 Db Db Db2 Db3 Multi Bank Interleaving WRITE (BL=4) A-9 ACT a Write trp ACT a A a a A a a BA, Da Da Da2 Da3 twr Internal precharge starts Sep.23 Page-9

22 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed to interval is minimum.. Read Interrupted by Read (BL=4, CL=3) A-9 i j k l A A BA, Qai Qaj Qaj Qbk Qbk Qbk2 Qal Qal Qal2 Qal3 [ Read Interrupted by Write ] Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the should be controlled adequately by using the M to prevent the bus contention. The output is disabled automatically cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3) Write A-9 i j A A BA, M Q Qai D Daj Daj Daj2 Daj3 M control Write control Sep.23 Page-2

23 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank. to PRE interval is minimum. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. Read Interrupted by Precharge (BL=4) PRE Q Q Q2 PRE CL=3 Q Q PRE Q PRE Q Q Q2 PRE CL=2 Q Q PRE Q Sep.23 Page-2

24 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) [Read Interrupted by Burst Terminate] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. to TBST interval is minimum. A TBST command to output disable latency is equivalent to the /CAS Latency. Read Interrupted by Terminate (BL=4) TBST Q Q Q2 TBST CL=3 Q Q TBST Q TBST Q Q Q2 TBST CL=2 Q Q TBST Q Sep.23 Page-22

25 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum. Write Interrupted by Write (CL=3,BL=4) Write Write Write Write A-9 i j k l A A BA, Dai Daj Daj Dbk Dbk Dbk2 Dal Dal Dal2 Dal3 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to interval is minimum. The input data on at the interrupting cycle is "don't care". Write Interrupted by Read (CL=3,BL=4) Write Write A-9 i j k l A A BA, M Dai Qaj Qaj Dbk Dbk Qal Sep.23 Page-23

26 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank.write recovery time(twr) is required from the last data to PRE command. During write recovery, data inputs must be masked by M. Write Interrupted by Precharge (BL=4) ACT Write PRE ACT trp A-9, a a a A BA- M twr Da Da [Write Interrupted by Burst Terminate] Burst terminate command can terminate burst write operation.in this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum. Write Interrupted by Terminate (BL=4) ACT Write TBST Write A-9, a a b A BA- Da Da Db Db Db2 Db3 Sep.23 Page-24

27 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) [Write with Auto-Precharge Interrupted by Write or Read to another Bank] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after trp. Auto-precharge interruption by a command to the same bank is inhibited. Write Interrupted by WRITE to another bank (BL=4) Write Write ACT BL trp A-9, a b a twr A a BA- Da Da Db Db Db2 Db3 auto-precharge interrupted activate Write Interrupted by to another bank (CL=2,BL=4) Write Read ACT BL trp A-9, a b a twr A a BA- Da Da Qb Qb Qb2 Qb3 auto-precharge interrupted activate Sep.23 Page-25

28 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) [Read with Auto-Precharge Interrupted by Read to another Bank] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after trp. Auto-precharge interruption by a command to the same bank is inhibited. Read Interrupted by Read to another bank (CL=2,BL=4) Read Read ACT BL trp A-9, a b a A a BA- Qa Qa Qb Qb Qb2 Qb3 auto-precharge interrupted activate [Full Page Burst] Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal. [Single Write] When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-). Sep.23 Page-26

29 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= / CAS= L, /WE= /= H) command. The refresh address is generated internally. 496 REFA cycles within 64ms refresh 64M bit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum trc. Any command must not be supplied to the device before trc from the REFA command. Auto-Refresh /CS /RAS NOP or DESELECT /CAS /WE minimum trfc A- BA, Auto Refresh on All Banks Auto Refresh on All Banks Sep.23 Page-27

30 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, = L). Once the selfrefresh is initiated, it is maintained as long as is kept low. During the self-refresh mode, is asynchronous and the only enabled input,all other inputs including are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable inputs, asserting DESEL or NOP command and then asserting =H. After trc from the st egde following =H, all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh /CS Stable NOP /RAS /CAS /WE A- new command BA, Self Refresh Entry Self Refresh Exit minimum trfc for recovery Sep.23 Page-28

31 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) SUSPEND controls the internal at the following cycle. Figure below shows how works. By negating, the next internal is suspended. The purpose of suspend is power down, output suspend or input suspend. is a synchronous input except during the self-refresh mode. suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. ext. tih tis tih tis int. Power Down by Standby Power Down PRE NOP NOP NOP Active Power Down ACT NOP NOP NOP Suspend by (CL=2) Write Read D D D2 D3 Q Q Q2 Q3 Sep.23 Page-29

32 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) M CONTROL M is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, M(U,L) masks input data word by word. M(U,L) to write mask latency is. During reads, M(U,L) forces output to Hi-Z word by word. M(U,L) to output Hi-Z latency is 2. M Function(CL=3) Write M D D2 D3 Q Q Q3 masked by M(U,L)=H disabled by M(U,L)=H Sep.23 Page-3

33 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) ABSOLUTE MAIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vdd Supply Voltage with respect to Vss V VddQ Supply Voltage for Output with respect to VssQ V VI Input Voltage with respect to Vss V VO Output Voltage with respect to VssQ V IO Output Current 5 ma Pd Power Dissipation Ta = 25 C Topr Operating Temperature - 7 Tstg Storage Temperature mw C C RECOMMENDED OPERATING CONDITIONS (Ta= - 7 C,unless otherwise noted) Symbol Parameter Limits Min. Typ. Max. Unit Vdd Supply Voltage V Vss Supply Voltage V VddQ Supply Voltage for output V VssQ Supply Voltage for output V VIH* High-Level Input Voltage all inputs 2. VddQ +.3 V VIL*2 Low-level Input Voltage all inputs V NOTES:. VIH(max)=5.5V for pulse width less than ns. 2. VIL(min)=-.V for pulse width less than ns. CAPACITAE (Ta= -7 C,Vdd=VddQ=3.3±.3V,Vss=VssQ=V,unless otherwise noted) Symbol Parameter Test Condition Limits (max.) Limits (min.) -6,-7-75/-75L/-8 Unit CI(A) Input Capacitance, address MHz pf CI(C) Input Capacitance, contorl pin.4v bias pf CI(K) Input Capacitance, pin 2mV swing Vcc=3.3V pf CI/O Input Capacitance, I/O pin pf Sep.23 Page-3

34 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) AVERAGE SUPPL CURRENT from Vdd (Ta= - 7 C, Vdd=VddQ=3.3±.3V,Vss=VssQ=V, unless otherwise noted) ITEM Symbol Organization -6 Limits (max.) L -8 Unit Operating current Icc trc=min, t=min BL=,IOL=mA x4/x8/x ma Precharge Standby current in Non-Power down mode Precharge Standby current in Power down mode =VILmax Icc2N x4/x8/x6 ma t=5ns =VIHmin Icc2NS x4/x8/x ma =VILmax(fixed) Icc2P =VIHmin t=5ns(note) x4/x8/x6 =VIHmin Icc2PS x4/x8/x6 ma t=vilmax(fixed) ma Active Standby current Icc3N Icc3NS =/CS=VIHmin t=5ns(note) =VIHmin t=vilmax(fixed) x4/x8/x6 x4/x8/x ma Burst current Icc4 All Bank Active t = min BL=4, CL=3, IOL=mA x4/x8/x ma Auto-refresh current Icc5 trc=min, t=min x4/x8/x ma Self-refresh current Icc6 <.2V x4/x8/x6.5 ma NOTE:. Icc(max) is specified at the output open condition. 2. Input signals are changed one time during 3ns. AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta= - 7 C, Vdd=VddQ=3.3±.3V,Vss=VssQ=V, unless otherwise noted) Symbol Parameter Test Conditions Min. Limits Max. unit VOH (DC) High-Level Output Voltage (DC) IOH=-2mA 2.4 V VOL (DC) Low-level Output Voltage (DC) IOL= 2mA.4 V IOZ Off-state Output Current Q floating VO= -- VddQ -5 5 µa II Input Current VIH = -- VddQ +.3V -5 5 µa Sep.23 Page-32

35 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) AC TIMING REQUIREMENTS (Ta= - 7 C, Vdd=VddQ=3.3±.3V,Vss=VssQ=V, unless otherwise noted) Input Pulse Levels:.8V-2.V Input Timing Measurement Level:.4V Symbol Parameter t cycle time CL=2 Limits L -8 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. - - Unit ns CL= ns tch High pulse width n tcl Low pulse width ns tt Transition time of tis Input Setup time (all inputs) tih Input Hold time (all inputs) n trc Row Cycle time trfc Refresh Cycle Time Row to Column Delay tras Row Active time trp Row Precharge time twr Write Recovery time trrd Act to Act Delay time trsc Mode Register Set Cycle time tref Refresh Interval time ns ns K 45 K ns 75 8 ns 2 2 ns K 45 K 48 K ns 2 2 ns 5 2 ns 5 2 ns 5 2 ns ms s s.4v.4v Any AC timing is referenced to the input signal passing through.4v. Sep.23 Page-33

36 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) SWITCHING CHARACTERISTICS (Ta= - 7 C, Vdd=VddQ=3.3±.3V,Vss=VssQ=V, unless otherwise noted) Limits Symbol Parameter Min. -6 Max. -7 Min. Max. -75 Min. Max. -75L Min. Max. Min. -8 Max. Unit Note tac Access time from CL=2 CL= ns ns toh Output Hold time from CL=2 CL= ns ns * tolz Delay time, output lowimpedance from ns tohz Delay time, output highimpedance from ns NOTE:. If clock rising time is longer than ns,(tr/2-.5ns) should be added to the parameter. Output Load Condition V OUT.4V 5pF.4V Output Timing Measurement Reference Point.4V tolz.4v tac toh tohz Sep.23 Page-34

37 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Burst Write (single trc /CS tras trp /RAS /CAS twr twr /WE M A-8 A A9, BA, D D D D D D D D ACT# WRITE# PRE# ACT # WRITE# PRE# Italic parameter indicates minimum case Sep.23 Page-3 5

38 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Burst Write (multi /CS /RAS trrd tras trc trc trp /CAS twr twr /WE M A-8 A A9, BA, D D D D D D D D D D D D ACT# WRITE# PRE# ACT# WRITE# PRE# ACT# WRITEA# (Auto-Precharge) ACT# Italic parameter indicates minimum case Sep.23 Page-36

39 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Burst Read (single CL= /CS trc tras trp tras /RAS /CAS /WE M A-8 A A9, BA, Q Q Q Q Q Q Q Q ACT# # PRE# ACT# # PRE# Italic parameter indicates minimum case Sep.23 Page-37

40 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Burst Read (multiple CL= /CS trc trc trrd tras /RAS /CAS /WE M A-8 A A9, BA, Q Q Q Q Q Q Q Q Q Q Q Q ACT# A# ACT# A# ACT# # PRE# ACT# Italic parameter indicates minimum case Sep.23 Page-38

41 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Write Interrupted by /CS /RAS /CAS /WE trrd twr M A-8 A A9, BA, D D D D D D D D D D D D ACT# WRITE# WRITE# WRITEA# WRITE# PRE# ACT# interrupt same bank interrupt other bank interrupt other bank ACT# Italic parameter indicates minimum case Sep.23 Page-39

42 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Read Interrupted by /CS /RAS trrd /CAS /WE M A-8 A A9, BA, Q Q Q Q Q Q Q Q Q Q Q Q ACT# # # A# # ACT# interrupt other bank interrupt same bank interrupt other bank ACT# Italic parameter indicates minimum case Sep.23 Page-4

43 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Write Interrupted by Read, Read Interrupted by /CS trrd /RAS /CAS twr /WE M A-8 A A9, BA, D D Q Q D D D D ACT# WRITE# # WRITE# PRE# ACT# Italic parameter indicates minimum case Sep.23 Page-4

44 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Write/Read Terminated by trc /CS trp tras trp /RAS /CAS twr /WE M A-8 A A9, BA, D D Q Q ACT# WRITE# PRE# ACT# # PRE# Te rminate Te rminate ACT# Italic parameter indicates minimum case Sep.23 Page-42

45 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Write/Read Terminated by Burst /CS /RAS /CAS /WE twr M A-8 A A9, BA, D D Q Q D D D D ACT# WRITE# TERM # TERM WRITE# PRE# Italic parameter indicates minimum case Sep.23 Page-43

46 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Single Write Burst /CS /RAS /CAS /WE M A-8 A A9, BA, D Q Q Q Q ACT# WRITE# # Italic parameter indicates minimum case Sep.23 Page-44

47 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Power-Up Sequesce and Intialize 2µs /CS trp trfc trfc trsc /RAS /CAS /WE M A-8 MA A A9, BA, NOP Power On PRE ALL REFA REFA REFA MRS ACT# Minimum 8 REFA cycles Italic parameter indicates minimum case Sep.23 Page-45

48 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Auto Refresh trfc /CS trp /RAS /CAS /WE M A-8 A A9, BA, D D D D PRE ALL REFA ACT# WRITE# All banks must be idle before REFA is issued. Italic parameter indicates minimum case Sep.23 Page-46

49 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Self Refresh /CS /RAS trp trfc /CAS /WE M A-8, A A9, BA, PRE ALL Self Refres h Entry Self Refres h Exit ACT# All banks must be idle before REFS is issued. Italic parameter indicates minimum case Sep.23 Page-47

50 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) /CS /RAS /CAS /WE M A-8 A A9, BA, D D D D Q Q Q Q ACT# WRITE# internal # suspended internal suspended Italic parameter indicates minimum case Sep.23 Page-48

51 P2V64S2DTP ( 4-BANK x 4,94,34-WORD x 4-BIT) P2V64S3DTP (4-BANK x 2,97,52-WORD x 8-BIT) P2V64S4DTP (4-BANK x,48,576-word x 6-BIT) Power Down /CS /RAS /CAS /WE Standby Power Down Active Power Down M A-8 A A9, BA, PRE ALL ACT# Sep.23 Page-49