Modeling and Design of High-Efficiency Power Amplifiers Fed by Limited Power Sources

Size: px

Start display at page:

Download "Modeling and Design of High-Efficiency Power Amplifiers Fed by Limited Power Sources"

Wendy Lang
5 years ago
Views:

1 Modeling and Design of High-Efficiency Power Amplifiers Fed by Limited Power Sources Arturo Fajardo Jaimes 1,2, Fernando Rangel de Sousa 1 1- Radiofrequency Department of Electrical and Electronics Engineering UFSC Florianopolis, Brazil 2- Department of Electronics Engineering Pontifical Xavierian University (PUJ) Bogota, Colombia

2 Agenda Introduction Proposed PA Modeling Design Methodology Study Case Conclusions Acknowledgment References 2

3 WBANs means? Networks which can be wearable, implanted or around the human body [1]. WBAN1 N1b H1 N1a N2b N1c N1d N2a H2 WBAN2 N3b N3a WBAN3 N3c H3 1 S. Movassaghi, M. Abolhasan, J. Lipman, et al., Wireless body area networks: A survey, IEEE Communications Surveys & Tutorials, vol. 16, no. 3, pp ,

4 WBANs means? Networks which can be wearable, implanted or around the human body [1]. IoT N1b WBAN1 H1 N1a N2b N1c N1d N2a H2 WBAN2 N3b N3a WBAN3 H3 N3c Networking at human body level (WBANs + IoT) is expected to cause a dramatic shift in HcS [1]. 1 S. Movassaghi, M. Abolhasan, J. Lipman, et al., Wireless body area networks: A survey, IEEE Communications Surveys & Tutorials, vol. 16, no. 3, pp ,

5 WPTn concept for implanted device autonomy WPT node (WPTn) is an autonomous wearable WBAN node used as energy and communication solution for a passive implanted ID tag that sense biomedical data. NODE WBAN IMPLANTED DEVICE SKIN FAT MUSCLE WBAN NETWORK N1b N1a H1 N1c N1d 5

6 Self-sustaining WPT system power chain The maximum available power (P avs) of the Implanted power supply is limited by BOTH power chain efficiency and P avs of the Power EPS [2]. Rs Implanted Power Supply WPTn DC Implanted Device V DC Power EPS WPT interface (e.g. Inductive link or Antenna) DC LOAD 2 A. Fajardo and F. Rangel de Sousa, Ideal energy power source model and its implications on battery modeling, in Proc. 22th IBERCHIP Workshop, Florianopolis, Brasil. 2016, pp

7 Self-sustaining WPT system Design Traditional design approach: The system interactions are reduced to V or I specifications. The subsystems are optimized individually. Non - Traditional design example: Regulator-less PA: A non regulated voltage between the EPS and the power amplifier (PA) was explored in [3]. Rs V DC EPS DC M L 1 L 2 Inductive Link DC Load For Self-sustaining WPT system traditional design approach is inadequate, because maximum η does not necessarily means maximum P out. 3 J. C. Rudell, V. Bhagavatula, and W. C. Wesson, Future integrated sensor radios for long-haul communication, IEEE Commun. Mag., vol. 52, no. 4, pp ,

8 Modeling of the energy-flow process using the PA impedance ports At input power ports: R DC and R AC. A fraction of the power dissipated by PA are transfered to R L = R IL. Rs V DC EPS RDC PA RAC LIL RIL V AC L 1 DC/ Impedance Converter, 8

9 Modeling of the energy-flow process using the PA impedance ports At input power ports: R DC and R AC. A fraction of the power dissipated by PA are transfered to R L = R IL. Rs The load power depends only on the external elements connected to the PA. V DC EPS RDC PA RAC LIL RIL V AC L 1 DC/ Impedance Converter, 9

10 Modeling of the energy-flow process using the PA impedance ports At input power ports: R DC and R AC. A fraction of the power dissipated by PA are transfered to R L = R IL. The load power depends only on the external elements connected to the PA. The output power port could be modeled by a AC circuit power source. Rs V DC V DC EPS V AC RDC PA RAC LIL RIL L 1 DC/ Impedance Converter, V AC RDC P PA RAC RL 10

11 Circuit power source I s (t) i(t) v(t) A circuit power source imposes the power on its load [4]. P s (t) i(t) v(t) V s (t) i(t) v(t) 4 R. W. Erickson and D. Maksimovic, Fundamentals of power electronics. New York: Springer,

12 PA efficiency predicted by the Model I V DC V AC RDC P PA RAC I RL V P = Im2 2 R L = Vm 2 Im Vm = 2R L 2 P DC = I 2 DC R DC = V DC 2 = I DC V DC R DC Output power and efficiency: P = PAE P DC + P AC P = η D P PA P = η (P DC + P AC ) I = I m sin (ω 0 t) V = V m sin (ω 0 t) When P AC is negligible compared to P DC : η PAE η D P = R ( ) 2 L Im. P DC 2R DC I DC 12

13 PA efficiency predicted by the Model DC Rbias L I bias AC CBypass IPA RPA C0 L0 PA CBypass DC power= Bias circuit (or the driver circuit) + PA power stage. Therefore, η can be rewritten as: DC Rbias I bias AC CBypass Class-A PA RPA IPA C0 GND PA L0 GND η = 1 R L R DC 2 2 R PA ( Im I PA ) 2 = f (G R ) G R is the PA impedance factor defined as G R = R DC /R L, and f (x) is a function dependent on the PA topology. Class-D PA 13

14 Class-D Modeling Example I Considering ideal components, D=50% in the AC-port, high loaded quality factor, the MOSFET (N and P type) as an ideal switch an R on. V m I m = (R L + R = 4V DC on) π (R L + R on) I PA = i PA (t) T0 2I m/π R PA = V DC = π2 I PA 8 (R L + R on) R on R bias = f 0 α a b DC Rbias IPA I bias AC C Bypass Moving average RPA PA C 0 L 0 GND where, α represents the capacitance excess due to the driver implementation. The technology parameters (i.e., a = C G W and b = R onw ) were proposed in [5]. x(t) T0 = ω 0 2π t 0 + 2π ω 0 t 0 x(t)dt 5 B. R. W. Stratakos Anthony J. and S. R. Sanders, High-efficiency low-voltage dc-dc conversion for portable applications., in Proc. Int. Workshop on Low-Power Design, Napa, CA. 1994, pp

15 Class-D Modeling Example II DC AC Rbias I bias IPA RPA PA C 0 L 0 C Bypass GND η = 1 ( ( )) (1 + m (G R )) 1 + k m(g R ) where the function m(x) is given by: m (x) = 1 2 ( ) (A + B) x 1 ± 1 + (2A 2B) x + (A + B) 2 x 2 This efficiency is maximum when: (k + 1) k + k G opt = (A + B) (k + 1) k + A (k + 1) its maximum value is: (1) A = f 0 α a b ; B = 8 π 2 ; k = A B ; G R = R DC R L. k 2 + k η max = ( k + ) ( k 2 + k k ).(2) k 2 + k 15

16 Proposed Design Methodology I For maximizing the power delivered to the load, the methodology maximize BOTH the power supplied by the harvester and the PA efficiency. The methodology uses PA modeling based on its ports and impedance matching concepts. The DC-IM implementation could be an DC/DC converter, and the AC-IM implementation could be a L or π network. Power EPS DC-IM 1 : M 1 : p AC-IM DC/ converter DC AC In PA AC Out 1 : n AC-IM 16

17 Proposed Design Methodology II Step Step Description Equation 1 Find the P avs of the power EPS and its related variables: optimum load impedance (R pavs), load voltage (V pavs) and current (I pavs). e.g. for a thermoelectric generator, the internal series resistor of the EPS (R s) is constant, therefore: R pavs = R s, V pavs = V DC 2 and I pavs = V DC. 2R s 17

18 Proposed Design Methodology II Step Step Description Equation Find the P avs of the power EPS and its related variables: optimum load 1 impedance (R pavs), load voltage (V pavs) and current (I pavs). Fix the voltage in the PA DC-port as the 2 highest for a particular implementation restriction (e.g. V max CMOS process.) e.g. for a thermoelectric generator, the internal series resistor of the EPS (R s) is constant, therefore: R pavs = R s, V pavs = V DC 2 and I pavs = V DC. 2R s V DC opt = V max 18

19 Proposed Design Methodology II Step Step Description Equation Find the P avs of the power EPS and its related variables: optimum load 1 impedance (R pavs), load voltage (V pavs) and current (I pavs). Fix the voltage in the PA DC-port as the 2 highest for a particular implementation restriction (e.g. V max CMOS process.) 3 Find the DC current that extracts the Pavs of the EPS. e.g. for a thermoelectric generator, the internal series resistor of the EPS (R s) is constant, therefore: R pavs = R s, V pavs = V DC 2 and I pavs = V DC. 2R s V DC opt = V max I DC opt = Pavs V max 19

20 Proposed Design Methodology II Step Step Description Equation Find the P avs of the power EPS and its related variables: optimum load 1 impedance (R pavs), load voltage (V pavs) and current (I pavs). Fix the voltage in the PA DC-port as the 2 highest for a particular implementation restriction (e.g. V max CMOS process.) 3 Find the DC current that extracts the Pavs of the EPS. Find the impedance of the PA DC-port 4 that maximizes the power extracted from the harvester. e.g. for a thermoelectric generator, the internal series resistor of the EPS (R s) is constant, therefore: R pavs = R s, V pavs = V DC 2 and I pavs = V DC. 2R s V DC opt = V max I DC opt = Pavs V max R DCopt = V DC I DC = V 2 max P avs 20

21 Proposed Design Methodology II Step Step Description Equation Find the P avs of the power EPS and its related variables: optimum load 1 impedance (R pavs), load voltage (V pavs) and current (I pavs). Fix the voltage in the PA DC-port as the 2 highest for a particular implementation restriction (e.g. V max CMOS process.) 3 Find the DC current that extracts the Pavs of the EPS. Find the impedance of the PA DC-port 4 that maximizes the power extracted from the harvester. Find the optimum load value for maximizing PA 5 efficiency. e.g. for a thermoelectric generator, the internal series resistor of the EPS (R s) is constant, therefore: R pavs = R s, V pavs = V DC 2 and I pavs = V DC. 2R s V DC opt = V max I DC opt = Pavs V max R DCopt = V DC I DC = V 2 max P avs R Lopt = G Ropt R DCopt 21

22 Proposed Design Methodology II Step Step Description Equation Find the P avs of the power EPS and its related variables: optimum load 1 impedance (R pavs), load voltage (V pavs) and current (I pavs). Fix the voltage in the PA DC-port as the 2 highest for a particular implementation restriction (e.g. V max CMOS process.) 3 Find the DC current that extracts the Pavs of the EPS. Find the impedance of the PA DC-port 4 that maximizes the power extracted from the harvester. Find the optimum load value for maximizing PA efficiency. 5 Find the specifications of the DC and 6 AC impedance matching networks (DC- IM and AC-IM). e.g. for a thermoelectric generator, the internal series resistor of the EPS (R s) is constant, therefore: R pavs = R s, V pavs = V DC 2 and I pavs = V DC. 2R s V DC opt = V max I DC opt = Pavs V max R DCopt = V DC I DC = V 2 max P avs R Lopt = G Ropt R DCopt R DC opt M = = R pavs V 2 max P avs R pavs 22

23 Proposed Design Methodology II Step Step Description Equation Find the P avs of the power EPS and its related variables: optimum load 1 impedance (R pavs), load voltage (V pavs) and current (I pavs). Fix the voltage in the PA DC-port as the 2 highest for a particular implementation restriction (e.g. V max CMOS process.) 3 Find the DC current that extracts the Pavs of the EPS. Find the impedance of the PA DC-port 4 that maximizes the power extracted from the harvester. Find the optimum load value for maximizing PA efficiency. 5 Find the specifications of the DC and 6 AC impedance matching networks (DC- IM and AC-IM). e.g. for a thermoelectric generator, the internal series resistor of the EPS (R s) is constant, therefore: R pavs = R s, V pavs = V DC 2 and I pavs = V DC. 2R s V DC opt = V max I DC opt = Pavs V max R DCopt = V DC I DC = V 2 max P avs R Lopt = G Ropt R DCopt R DC opt M = = R pavs n = = R L R L opt V 2 max P avs R pavs P avs R L G R opt V 2 max 23

24 Class A Study Case - PA Modeling I IPA DC Rbias L I bias AC C Bypass RPA C 0 L 0 PA C Bypass GND { 0.5 GR G R < 1 ; I m = I PA η = 1 2G R G R 1; V m = V. C Where, G R = R DC R L. G Ropt = 1 its maximum value is: η max = 50% This efficiency is maximum when: 24

25 Class A Study Case - PA Modeling II As a proof of concept a class A PA was designed, simulated and implemented. I PA f 0 R L 1mA 100 khz 1kΩ DC Rbias IPA RPA PA The simulation setup uses the harmonic balance simulation technique in the Advanced Design System (ADS R ) software. V AC and R PA sweeps were implemented. L I bias AC CBypass C0 L0 CBypass GND PA simulation results R PA Limit P DC P DC P L P L η η (Ω) type vac φt w/o LC w L w/o L w L w/o L w L (mw) (mw) (mw) (mw) (%) (%) 0.5 Vm=V C Vm=V C Im=I PA Im=I PA The R PA sweep was implemented by a fixed current (I PA =1mA) and a V DC sweep. The circuit was simulated with and without the output LC tank filter (Only C 0 ). 25

26 Class A Study Case - PA Modeling III In the experimental setup the I PA was fixed to 1 ma and the R PA was set with the V DC. In this setup, V AC was incremented until the PA operates at the limit of the class-a operation (I m = I PA or V m =V C ). PA experimental results R PA Limit v ac φt LC tank P DC P L η (Ω) type (mw) (mw) (%) 0.50 V m=v C w/o V m=v C w/o I m=i PA w/o I m=i PA w/o

27 Class A Study Case - PA Modeling IV The predicted efficiency by the proposed PA model and the results (simulated and experimental) are plotted in the Figure GR 27

28 Class A Study Case - Proposed Methodology (PA + Power EPS) In order to verify experimentally the proposed methodology without the practical limitations of the commercial harvesters and the impedance matching networks, we choose a scenario with the following specifications: a emulated power EPS with P avs = 1mW and R pavs = 1kΩ, a resistive load of R L = 1kΩ, and f 0 = 100 khz. Metodology Results V DCopt I DCopt R DCopt R Lopt M n 1V 1mA 1kΩ 1kΩ 1 1 Experimental results R DC P EPS P DC P η EPS η DC/ 1.001kΩ 2.004mW µw 500.4µW 50% 50 % 28

29 Conclusions A design methodology for a generic PA fed by a power EPS was proposed. 29

30 Conclusions A design methodology for a generic PA fed by a power EPS was proposed. As a proof of concept a class-a PA was designed, implemented and tested. 30

31 Conclusions A design methodology for a generic PA fed by a power EPS was proposed. As a proof of concept a class-a PA was designed, implemented and tested. The results reflect that the designed PA extracts the maximum available power of the source with its maximum efficiency. 31

32 Conclusions A design methodology for a generic PA fed by a power EPS was proposed. As a proof of concept a class-a PA was designed, implemented and tested. The results reflect that the designed PA extracts the maximum available power of the source with its maximum efficiency. For maximizing the power on the load in a system powered by Power EPSs, the traditional approach based only the system efficiency is inadequate. Furthermore, the designing of EPSs, Energy converters (i.e. PAs) and circuits that could take advantage of the use of power specifications instead of predefined voltage or current condition is a open challenge. Implanted Power Supply WPTn Implanted Device Rs DC V DC Power EPS WPT interface (e.g. Inductive link or Antenna) DC LOAD 32

33 Acknowledgment The first author would like to thank COLCIENCIAS and the Pontificia Universidad Javeriana for the financial support. Also, the authors would like to thank the CNPq and the INCT/NAMITEC for their partial financial support and all the students of the Radio Frequency integrated circuits Group (G-UFSC) for the important discussions. 33

34 References [1] S. Movassaghi, M. Abolhasan, J. Lipman, D. Smith, and A. Jamalipour, Wireless body area networks: A survey, IEEE Communications Surveys & Tutorials, vol. 16, no. 3, pp , [2] A. Fajardo and F. Rangel de Sousa, Ideal energy power source model and its implications on battery modeling, in Proc. 22th IBERCHIP Workshop, Florianopolis, Brasil. 2016, pp [3] J. C. Rudell, V. Bhagavatula, and W. C. Wesson, Future integrated sensor radios for long-haul communication, IEEE Commun. Mag., vol. 52, no. 4, pp , [4] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics. New York: Springer, [5] B. R. W. Stratakos Anthony J. and S. R. Sanders, High-efficiency low-voltage dc-dc conversion for portable applications., in Proc. Int. Workshop on Low-Power Design, Napa, CA. 1994, pp

35 Obrigado Site:

Revisiting the Power-Efficiency Trade-Off on a DC Voltage Source

Revisiting the Power-Efficiency Trade-Off on a DC Voltage Source Arturo Fajardo Jaimes 1,2, Fernando Rangel de Sousa 1 1- Radiofrequency Department of Electrical and Electronics Engineering UFSC Florianpolis,