Digital Logic Design. Midterm #2

Transcription

1 EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm - igital Logic esign Miterm #2 Problems Points Total 5 Was the exam fair? yes no

2 EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm - 2 Problem 5 points Given is the logic circuit moel of a state machine shown in Figure.. y +y (+y ) FF C y Z y + y (+ ) C FF2 (a) Y = (+y ) Y 2 = y (+ ) Z = y Figure. state machine with two flip-flops in its internal state memory block. (a)logic moel of the circuit. erive excitation functions of the internal state memory flip-flops an the output function z. Problem Statement Using the given logical moel of Figure., emonstrate an ability to:. etermine the expressions of logic functions at the outputs of all logic gates in the combinational block of the logical moel; 2. apply the knowlege of Boolean algebra to simplification of logic functions; 3. recite the characteristic function of a -type flip-flop, an compose expressions of the next state functions of the internal memory block; 4. erive the content of the State Transition Table from the Next State Functions, 5. raw the State Transition Graph base on a prepare State Transition Table. Hint # For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces the shown results.

3 EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm - 3 Problem Solution n explicit emonstration of unerstaning the following solution steps is expecte.. Next to the outputs of logic gates in the circuit of Figure.(a), inicate the expressions of logic gates output functions. Write in the space reserve for Figure. the expressions of the excitation functions of internal memory flip-flops an the expression of the output function Z..2 In the space reserve for equation (-) fill in the expression of the -type flip-flop s characteristic function. + = (-).3 In the space reserve for equations (-2) an (-3), fill in the simplifie expressions of the next state functions of the internal state memory (flip-flops). Y = = (+y ) Y 2 = 2 = y (+ ) Z = y (-2) (-3) (-4).4.5 In the space reserve for Figure.2(a), fill in the contents of the State transition table of the sequential circuit moel of Figure.. In the space reserve for Figure.2, prepare the rawing of the State transition graph (state iagram) of the sequential logic circuit of Figure.. y / / / / /,/ / / / / / /,/ Y Y 2 /z (a) / Figure.2 Results of the analysis. (a)state transition table of the SM from Figure.(a). State transition graph (State iagram) of the SM from Figure.(a).

4 EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm - 4 Problem 2 4 points Given is a logic function F 2 in the ecimal sum of minterms representation (2-). F 2 (,B,C,) = Σ(, 2, 4, 5, 8, 9,, 2, 4) (2-) 2 Problem Statement For the logic function (2-), emonstrate an ability to:. esign a combinational circuit which uses an 8: multiplexer moule to implement the function (2-), 2. apply the esign metho which is base on preparation of either one of the following two tables: - MUX Implementation Table, or - Truth Table of the function to be implemente. Hint # For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces the shown results. Problem Solution n explicit emonstration of unerstaning the following solution steps is expecte. 2. epening on the selecte esign metho, fill in the missing ata in either the MUX Implementation Table of Figure 2.(a), or the Truth Table of Figure 2.2(a). I I I 2 I 3 I 4 I 5 I 6 I (a) MUX 8: s 2 s s F(,B,C,) B C Figure 2. MUX Implementation Table metho. (a)mux implementation table. Implementation of the function (2-) Consistent with the selecte esign metho, show in the space reserve for Figure 2., or

5 f5m2s_il7.fm - 5 The University of Toleo EECS: igital Logic esign r. nthony. Johnson alternatively in the space reserve for Figure 2.2, how the logical constants an, an the literals of the logical variables, B, C, an ought to be applie to the MUX moule s inputs. n lternative Problem Solution (a) Figure 2.2 Truth Table metho. (a)truth table. Implementation of the function (2-) s 2 s s MUX 8: F(,B,C,) B C B C F I k k=(s 2 s s ) 2

6 EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm - 6 Problem 3 6 points Given is the following verbal specification of a state machine (SM): (a) the SM has one input signal S, the SM has one output signal output Z, (c) the SM recognizes the input signal sequence, () every time the input signal sequence has been observe by the SM, the output signal Z is set to Z =, otherwise Z =; (overlapping sequences recognize). (e) the SM is to be implemente using positive ege triggere -type flip-flop(s). S Next state logic I N n / Internal state memory Y y n / I Output logic O y Z Figure 3. General architecture of a Mealy type State Machine. Problem Statement Base on the given specification, emonstrate an ability to:. compose the graphical representation of the State Transition Graph of a state machine that will implement the given verbal specification of the SM, 2. compose a State Transition Table which escribes the same State Machine as alreay escribe by the compose State Transition Graph, 3. combine the information from the State Transition Table a the flip-flop s Excitation Table to prepare the Transition Excitation Table of the specifie SM. 4. apply the Karnaugh Map simplification metho to erive the internal state excitation functions escribe in the Transition Excitation Table of the specifie SM, 5. compose a minimum number of logic gates circuit which implements the State Machine for which the internal state memory is specifie, an for which the flip-flop excitation functions have been erive. Hint # For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces the shown results.

7 EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm - 7 Problem Solution n explicit emonstration of unerstaning the following solution steps is expecte. 3. ssigning to the initial state the binary encoe name "", prepare a graphical representation of the State Transition Graph of the SM which will implement the given verbal specification. Show the prepare State Transition graph in the space reserve for Figure 3.2(a). 3.2 In the space reserve for Figure 3.2 fill in the contents of the State Transition Table that correspons to the prepare state transition graph. 3.3 In the space reserve for Figure 3.2(c) fill in the contents of the Excitation Table of a -type flip-flop. 3.4 In the space reserve for Figure 3.2(), compose the State Transition Excitation Table of the SM by combining the information from the state transition table of the SM an the excitation table of the flip-flop Using the Karnaugh map metho, erive the simplifie expressions of the flip-flop excitation function(s), 2 an the output function Z, an manipulate them into expressions with minimum number of literals. Show the obtaine expressions into the space reserve for Figure 3.2(f). y Y S y / Y Y 2 2 Z? y y? 2 S / / / / / / / / / / / Y Y 2 /Z / (c) / (a) () Sy Sy Sy = S 2 = S Z = Sy (e) -Kmap 2 -Kmap Figure 3.2 esign process of the State Machine. (a)state transition graph of the SM. State transition table of the SM. (c)-type flip-flop excitation table. ()State Transition excitation table of the SM. (e)karnaugh maps of functions, 2 an Z. (f)simplifie expressions of logic functions, 2 an Z. Z-Kmap (f)

8 EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm In the space reserve for Figure 3.3 prepare the minimum number of logic gates logical circuit moel which implements the State Machine whose specification is given at the beginning of this problem. S FF y Z = Sy S FF2 Figure 3.3 Logical circuit moel of the State Machine that implements the sequence recognizer for sequence.