Electronics I. Midterm 2

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1 The University of Toledo Section s5m2s_elct7.fm - S:3400 lectronics I r. nthony. Johnson lectronics I Midterm 2 Problems Points Total 5 Was the exam fair? yes no

2 The University of Toledo s5m2s_elct7.fm - 2 S:3400 lectronics I r. nthony. Johnson Problem 4 points Given is the oolean function of equation (-). Z = + (+) (-) Problem Statement For the oolean function of quation (-), demonstrate an ability to:. design a transistor level circuit model of a static MOS gate which implements the function (-) using the minimum number of transistors; 2. apply the design procedure in which one first synthesizes the n-block circuit, and then derives the p-block circuit as a dual circuit with respect to the n-block circuit. Problem Solution Hint # For full credit, give answers to all questions, prepare all required circuit diagrams, write all equations for which the space is reserved, and show all algebraic and numerical expressions whose evaluation produces shown numerical results. n explicit demonstration of understanding the following solution steps is expected.. erive a minimum number of literals expression of the function Z and show it in the space reserved for equation (-2). Z = + (+) = + (+) (-2).2 Identify in the oolean expression (-2) all subexpressions which involve sums/products of exclusively literals of variables,,,, and. Show the identified subexpressions above the grey/red line in Figure. leaving between them adequate space for showing below the line the circuits specified in the next Step.3. +Ε Figure. Subcircuits of the n-block which implement the Ns or ORs of literals in (-)..3 onstruct the n-block subcircuits which correspond to sums or products of literals shown above the grey line in Figure.. Show the graphical representations of the constructed subcircuits below the grey line, and underneath the corresponding subexpression which they implement.

3 The University of Toledo s5m2s_elct7.fm - 3 S:3400 lectronics I r. nthony. Johnson.4 Identify in the oolean expression (-2) all those subexpressions in which the subexpressions shown in Figure. are involved in sums or products with other subexpressions of Figure., or with some literals of variables,,,, and. Show the identified subexpressions above the grey/red line in Figure.2 leaving between them adequate space for showing below the line the circuits specified in the Steps.5 and.6. (+) + (+) Figure.2 Subcircuits/circuit of the n-block which implement Ns or ORs of literals and higher order subexpressions in (-)..5 onstruct the n-block subcircuits which correspond to the subexpressions shown above the grey line in Figure.2. Show the graphical representations of the constructed subcircuits below the subexpressions which they implement..6 ontinue identifying all higher order subexpressions/expression in which lower-order subexpressions shown in Figures. and.2 are involved in sums or products with other lowerorder subexpressions, or with some literals, until finally the expression (-2) is reached. Show the identified higher-order expressions above the grey line in Figure.2, leaving between them adequate space for showing below the line the graphical representations of the circuits which implement the corresponding expressions shown above the line..7 onstruct the p-block circuits as the dual to the already constructed n-block circuit. Show in Figure.3 the graphical representations of the circuit of whole static MOS gate which implements the oolean function (-). V Z = + (+) Figure.3 ompleted Static MOS implementation of the oolean function Z = + (+) V SS

4 The University of Toledo s5m2s_elct7.fm - 4 S:3400 lectronics I r. nthony. Johnson Problem 2 5 points Figure 2. shows the electric circuit models of the reference inverter, and a static MOS implementation of a oolean Function Y, which are both the modules in the same VLSI integrated circuit. +V +V Y /2 (a) Figure 2. Static MOS gate and Reference inverter circuits. (a)reference Inverter. (b)static MOS gate. (b) 2 2 Problem Statement For the given static MOS gate of Figure 2.(b), demonstrate an ability to: (a) determine the expression of the oolean function Y implemented by the gate, (b) design the aspect ratios of transistors in the circuit of the given gate so that the rise and fall times of the gate are equal to the rise and fall times of the reference inverter of Figure 2.(a). Hint # For full credit, give answers to all questions, prepare all required circuit diagrams, write all equations for which the space is reserved, and show all algebraic and numerical expressions whose evaluation produces shown numerical results. Problem Solution n explicit demonstration of understanding the following solution steps is expected. 2. Prepare the expression of the oolean function Y implemented by the circuit in Figure 2.(a), and show the prepared expression in the space reserved for equation (2-). Y = ( +) (2-) 2.2 Using as the reference the transistor sizes of the reference inverter circuit of Figure 2.(a), design the aspect ratios of transistors in the p-block of the gate in Figure 2.(b) so that the gate s rise time is equal to the rise time of the reference inverter. Hint #2 Indicate the numerical values of the calculated aspect ratios next to the graphical symbols of corresponding transistors in Figure 2.(b). 2.3 Using as the reference the transistor sizes of the reference inverter circuit of Figure 2.(a), design the aspect ratios of transistors in the n-block of the gate in Figure 2.(b) so that the gate s fall time is equal to the fall time of the reference inverter.

5 The University of Toledo s5m2s_elct7.fm - 5 S:3400 lectronics I r. nthony. Johnson Problem 3 6 points Figure 3. shows a sketch of the layout of a MOS inverter circuit. The inverter circuit has been 3λ 2λ 2λ 2λ 3λ 5λ 3λ 5λ 2λ 5λ 3λ λ 2λ 4λ 4λ 4λ n + -diffusion p + -diffusion polysilicon n-well Figure 3. partial sketch of a MOS inverter layout (metal layer not shown). manufactured using an n-well process with the following parameter values: a) whole I - electron/hole mobility µ n = m 2 /Vs - µ p = 0.03 m 2 /Vs - threshold voltage V TN = 0.25 V - V TP = -0.3 V - body doping N b = 0 20 donor. atoms/m 3 - p-well doping N w = accpt. atoms/m 3 - n-diffusion doping N d = donor atoms/m 3 - p-diffusion doping N d = acceptor atoms/m 3 - thinox thickness t ox =0.07 µm - junction depth X j = 0.8 µm - lateral diffusion L = µm - V = 5V - minimum feature size λ= 0.6µm - dielectric constant of vacuumε o = F/m - dielectric constant of Si ε Si =.7 ε o - dielectric constant of SiO 2 ε ox =3.97 ε o b) pull-down transistor c) pull-up transistor - channel length L n = 2λ - channel length L P = 2λ - channel width W n = 4λ - channel width W P = 6λ.

6 The University of Toledo s5m2s_elct7.fm - 6 S:3400 lectronics I r. nthony. Johnson Problem Statement ased on the layout sketch of MOS inverter shown in Figure 3., demonstrate an ability to calculate: - chip-wide "Thinox" (gate to channel) capacitance per unit area, - gate to drain overlap capacitances of both transistors, - gate to channel capacitances of both transistors, - total parasitic capacitance at the inverter's input. Hint # For full credit, give answers to all questions, prepare all required circuit diagrams, write all equations for which the space is reserved, and show all symbolic and numerical expressions whose evaluation produces shown numerical results. Problem Solution n explicit demonstration of understanding the following solution steps is expected. 3. alculate the hip-wide "Thinox" (gate to channel) capacitance per unit area. Show your work in the space reserved for equation (3-). ox = ε ox t ox = = = ~ 500 µf/m 2 (3-) 3.2 alculate the pull-down transistor s gate to drain overlap capacitance. Show your work in the space reserved for equation (3-2) gdn = W n L ox = = 0.6 ff 3.3 alculate the gate-to-channel capacitance of the n-channel transistor. Show your work in the space reserved for equation (3-3). gn = W n. L n. ox = =.44fF 3.4 alculate the pull-up transistor s gate to drain overlap capacitance. Show your work in the space reserved for equation (3-4). gdp = W p L ox = = 0.9 ff 3.5 alculate the gate-to-channel capacitances of the p-channel transistor. Show your work in the space reserved for equation (3-5). gp = W p. L p. ox = = 2.6 ff 3.6 alculate the total parasitic capacitance at the inverter's input. Show your work in the space reserved for equation (3-6). TI = gn + gp = ( ). 0-5 = 3.6 ff (3-2) (3-3) (3-4) (3-5) (3-6)