Quantum Cellular Automata Final Project Report. Apoorv Khurasia Pulkit Gambhir

Transcription

1 Quantum Cellular Automata Final Project Report Apoorv Khurasia Pulkit Gambhir May 22, 2006

2 Abstract Our project involved the study of next generation paradigms of computation. In particular, our area of interest was nano-scale computing and the various materials or techniques we may use to achieve the same. We began with the study of Carbon Nano-tubes and then moved on to the study of Quantum Cellular Automata, which became our primary focus in the project. This report is written with a twofold purpose, firstly to summarize what all major work has been done in the area of Quantum Cellular Automata to date and secondly to document our efforts in extending this given knowledge.

3 Contents 1 Introduction 5 2 Basics of a QCA Quantum Wells, Boxes and Dots From Dots to Cells Cell Polarization and Binary Encodings Transmitting Information Line Saturation From Wires to Logic Making crossing coplanar Rotated Cells and Inverter chains Coplanar Wire Crossing Logical Operations on the Encoded Information Negation Higher Arity functions: Majority function Exclusive OR Dealing with Numerals Conclusion Clocked Quantum Cellular Automata Molecular Quantum Cellular Automata Single molecule response Cell to cell response Effects of external field Inducing information flow More on clocking Regular Designs based on Quantum Cellular Automata Designing a QCA FPGA Basic Logic Block Inter-connect Design Some untackled issues Designing a QCA RAM

4 5.2.1 Top Level Design QCA Implementation Combining RAMs and FPGAs Basic synchronous elements : Latches and Flip-Flops Building a D-latch Traditional Design QCA Implementation Building a D-flipflop Traditional Design QCA Implementation Concluding Remarks Extending synchronous designs : Building a counter Binary Counter A different approach Analysis Further Work Bibliography 57 2

5 List of Figures 2.1 Wave functions for the one dimensional Quantum Well problem for a proton. (width of the well is 3.65fm) Wave functions for the one dimensional Quantum Well problem for a proton. (width of the well is 3.65fm) Symmetric state of a proton in a box of height 25MeV and side 3.65fm Anti-symmetric state of the quantum dot in figure A Quantum Cell for QCA The two ground states for the system (labelled P = ±1) in the absence of an external Electric Field The cell-cell response function with t = 0.3meV A Line of interacting Quantum Cells Response of a line of cells The response of a line of cells for a different value of tunneling energy parameter. The driver cell is at 1 st location The variation of P sat with tunneling energy parameter A Quantum Cell rotated by 45. It is similar in all other respects to the one shown in fig Representing logical states in rotated cells An inverter chain and the variations in the cell polarization with distance(no. of cells) from driver Wire converters Coplanar wire crossing in QCA The results of simulation on the circuit of Fig The implementation of an inverter gate in QCADesginer The simulation results on the inverter shown in Fig The implementation of a majority gate in QCADesginer The simulation results on the majority gate shown in Fig The layout of a XOR gate The implementation of a XOR gate in QCA The implementation of a full adder in QCA Unoptimized and optimized full adder

6 4.1 1, 4-diallyl butane radical cation , 4-diallyl butane radical cation in various states of polarization Single molecule response : the setup Single molecule response The bistable ground state of the molecular QCA cell Cell-cell response Electric field applied to a single molecule Arrangement used for clocking of Quantum Cellular Automata The 4-phase clocking signal Resulting electric field produced at QCA surface on application of the clocking signal shown in figure Spatio-temporal evolution of states in a clocked regime pass transistor used in traditional FPGA s First-cut design x2 and 3x3 connect block Memory cell with a loop bit wide RAM with 4 addressable words QCA cell layout of RAM module Truth table for a gated D-latch Traditional design of a D-latch Latched wire Simulations of the latched wire D-latch circuit diagram QCA layout of D-Latch Simulation results of the D-Latch Negative edge triggered D-flip flop design Negative edge triggered D-flip flop design Negative edge triggered QCA based D-flip flop Simulation results of D-flip flop Binary counter or bit flipper Bit flipper QCA circuit A different way to think of synchronous circuits NI + OI and OI.NI CS. OI.NI and CS.( NI + OI) CS.( NI + OI) + CS. OI.NI Next state state connected back to current state, completing the loop of fig Simulation results of circuit shown in fig

7 Chapter 1 Introduction This report is a result of a one semester long study and experimentation (through simulations) by the authors at the Indian Institute of Technology, Delhi under the supervision of Dr. Kolin Paul. This report aims at introducing to the reader a new paradigm for computation - one that is of Quantum Cellular Automata (inter-changeably referred to as QCA from now on). This field is a wonderful and exciting blend of Computer Science and Physics. There is a constant demand for developing faster (and hence often smaller) digital computing components today. Over the past few years the computing hardware industry and chip manufacturers in particular have tried to achieve these small scale hardware devices by almost a brute force scaling down of the involved components. Thus one saw the development of such things as TFTs (Thin Film Transistors) and a whole range of Thin Film Design innovations aimed only at one thing - to scale down the existing components and save space. In this process both success and failure were achieved. The success was an achievement of feature sizes of 60nm, and the development of commercial hardware such micro-controllers and processors built using such tiny devices. The failure was that the power leakage as device sizes shrunk down, started to grow exponentially. About 5 years ago, switching power leakage was so small that researchers almost neglected the issue completely but today with the tiny chips we have, power dissipation is a major headache. At feature sizes mentioned above, power loss due to switching alone is reaching values of up to 50%. However, the story does not end here, there are bigger evils to be tackled. Even if we were able to come up with schemes to ebb this loss of power, it would not suffice. The reason being the fact that as device dimensions scale down, the variation between two transistors produced by the same process becomes serious enough to hamper the scalability and hence the usability of the device. Perhaps even more threatening is the fact that Quantum Effects are beginning to show up now. Going any further below this scale 5

8 would require researchers to develop knowledge about high power losses and building up and controlling very large Electric Fields capable of damaging the device. To add to this, quantum effects mean a very high probability of electrons tunneling through the wires and other devices thus creating more troubles for the already troubled scientists. The time is therefore apt, to look else where for newer ways of doing things, in short to look beyond silicon. In Quantum Cellular Automata we explore one such paradigm which has shown quite some potential over the past decade. This report starts by firstly delving into some quantum mechanics and in particular talking about quantum dots. We then introduce the concept of a Quantum Cellular Automata and the various interesting properties it displays. We then move on to the design of basic building blocks of digital circuit design using Quantum Cellular Automata wherein we explore some things such as quantum wires, inverters and majority gates. After looking at some of these basic designs, we go on to explore the concept of clocking with reference to Quantum Cellular Automata and the build up of very basic synchronous machinery in terms of a shift register. We then discuss a couple of large regular designs such as ROMs and FPGAs that may potentially be built using these automata. Finally, we describe our own efforts toward extending the work in synchronous circuits using QCA s where in we discuss some synchronous modules we had success in creating and also discuss some difficulties experienced in the same. 6

9 Chapter 2 Basics of a QCA QCAs or Quantum Dot Cellular Automata were introduced by Lent et al in the early 90s. They consist of an array of several Quantum Dots in close proximity. We shall describe the basics of a Quantum Dot in the following section. 2.1 Quantum Wells, Boxes and Dots One of the first things that one does in a basic Quantum Mechanics course is to solve the Schrödinger equation for a single particle in a single dimensional potential trap with infinite height (also called a Quantum Well). The wave equation for this problem is 2 ψ(x) x 2 + 2µE ψ(x) = 0 (2.1) 2 assuming the well dimension to be a. The boundary conditions for the equation are given by : ψ(x = 0) = 0 (2.2) ψ(x = a) = 0 (2.3) The normalized solutions for this equation are well known 2 ψ n (x) = a sin(nπ x) where n is the principal quantum number. (2.4) a and are plotted in Figure 2.1. If the height of the well is made finite then the particle can tunnel out of this well and can get lost. The Schrödinger equation for this case becomes 2 ψ(x) x 2 + k 2 ψ(x) = 0 for x < a 2 2 ψ(x) x 2 + κ 2 ψ(x) = 0 for x a 2 7 (2.5) (2.6)

10 Figure 2.1: Wave functions for the one dimensional Quantum Well problem for a proton. (width of the well is 3.65fm) while the boundary conditions change to the following lim ψ(x) = 0 x (2.7) ψ(x) = 0 (2.8) lim x with the additional requirements of continuity and differentiability of ψ(x) at x = a 2 and x = a 2. The solutions for this equation are now a little tricky. For the symmetric case (when ψ(x) is a symmetric function of x) they are ψ(x) = A cos(kx) for x < a 2 ψ(x) = B exp( κ x ) for x a 2 tan( ka 2 ) = k κ And for the anti-symmetric case one has ψ(x) = A sin(kx) for x < a 2 (2.9) (2.10) (2.11) (2.12) 8

11 ψ(x) = B exp( κ x ) for x a 2 (2.13) cot( ka 2 ) = κ (2.14) k These wave functions are plotted in Figure 2.2. Equations like (2.11) and (2.14) determine the allowed solutions for the well and hold only when E < V 0. When E > V 0 all states are allowed and we say that the particle is free. Figure 2.2: Wave functions for the one dimensional Quantum Well problem for a proton. (width of the well is 3.65fm) Now consider a particle in a square well. In this case the Schrödinger equation is two dimensional and its solutions can obtained by the separation of variables method. Ψ(x, y) = ψ(x)ψ(y) (2.15) We already know the values of ψ(x) and ψ(y) from Equations (2.9), (2.10), (2.12) and (2.13) we just need to substitute them in Equation (2.15) to get the wave function for the two dimensional case. Figures 2.3 and 2.4 show the wave functions of the particle in a square trap. A Quantum Dot is a three dimensional extension of the mentioned wells. The reader should note that the type of the dot may be spherical for which the solutions are in terms of the Legendre polynomials, or a cube for which 9

12 Figure 2.3: Symmetric state of a proton in a box of height 25MeV and side 3.65f m we have, as above, sinusoidal solutions. Whatever be the case, the important property of a quantum dot is that motion within it is restricted in all the three spatial dimensions. A particle in such a dot cannot move freely. But since the potential at the boundaries is still finite there is a finite probability that the particle tunnels outside and is lost from the dot. For our purposes we need a quantum dot which can trap an electron. There are many ways to implement an electron Quantum Dot. Implementations with semiconductors are most common and they are mainly used in Quantum Dot Lasers, which in themselves are a very active area of research today. Implementations with organic molecules have also been reported and are particularly useful for reasons discuused in chapter 4. Once we have a Quantum Dot ready we can move to the next level of abstraction and forget how it was implemented. This shall be our general philosophy of working wherein we try to understand a structure, build an appropriate model for the structure, then work with the abstraction of the model forgetting about the actual underlying structure. 2.2 From Dots to Cells Moving on, now we shall generate a Quantum Cell from such Quantum Dots which we have seen in the previous section. Such a cell consists of 10

13 Figure 2.4: Anti-symmetric state of the quantum dot in figure 2.3 four quantum dots on the corners of a square and one central dot (Fig. 2.5). The cell is occupied by two electrons. The electrons are free to tunnel from one dot to another but they cannot tunnel through the cell along the paths shown in the figure. We generally associate tunneling parameters t and t for tunneling between boundary dots and between boundary and center respectively. A good choice of these values is generally associated with t = t /10 = 0.3eV. It is also pertinent to point out there is nothing holy about the given construction of the quantum cell. It will become clear in the ensuing sections that the only reason for choosing this particular design is to have a configuration with a bistable ground state. If a design made with different numbers of dots or with different geometries may also achieve the same, we can equivalently build our model around that structure. 2.3 Cell Polarization and Binary Encodings Since there are five positions available and only two electrons to occupy them, there are 5 C 2 configurations available for a single cell, classically speaking. Quantum mechanics however ensures that there is in fact a continuum of possibilities with the electronic wave functions being delocalized over the quantum dots. It is helpful to define a quantity P called polarization and associate it with a cell. P = (ρ 1 + ρ 3 ) (ρ 2 + ρ 4 ) ρ 0 + ρ 1 + ρ 2 + ρ 3 + ρ 4 (2.16) 11

14 Figure 2.5: A Quantum Cell for QCA where ρ i = 1 if the i th dot is occupied and 0 otherwise. If the cell is isolated, which means that there are no fields present in its vicinity, then the observable value of P is 0. This is because any state A which has a polarization P A also has a counter state A with polarization P A. Now since both these states are symmetric (the only thing that can break their symmetry is an electric field) they occur with equal probability p and hence their superposed state has an expected value of polarization pp A + p( P A ) = 0. Now since all states which have a non-zero polarization have their counterpart, the net polarization in case of isolated cells is zero. When the cell temperature is low ( 0 K)the tunneling probabilities decrease and Coulombic term in the cell hamiltonian become dominant and hence the probability that the system occurs with the electrons in the antipodal sites (Fig.2.3) increases. This essentially means that at sufficiently low temperatures where perturbation due to thermal effects is negligible, if we can tune tunneling parameters correctly, we can have a bistable ground state; which consists of the electrons at the opposites of the diagnol. This happens because under such conditions, electrostatic repulsion is the only important quantity. These two states are equi-probable when the cell is in isolation (they are symmetric as the dot is isolated and there is no Electric Field in its proximity) and one has a polarization 1 and the other has a polarization 1. We can label them as binary zero and one respectively. Thus we have shown the way in which binary information can be stored in such a Quantum Dot Cell. Notice that the analysis assumes a very low temperature which is not a possibility for practical computability. However this is not a very serious drawback as it is fairly easy to increase our working temperature without losing the bistable ground state. This can be done by the appropriate tuning of the tunneling parameters from one dot to the other within the cell, which in turn is a highly implementation dependent matter. Also another assumption that we make hence forth is that although it is possible to have intra-cell tunneling, the probability of inter-cell tunneling is low enough to 12

15 Figure 2.6: The two ground states for the system (labelled P = ±1) in the absence of an external Electric Field. be completely ignored. 2.4 Transmitting Information Once information is available to us we must be able to transmit it as well. Consider two Quantum Cells A and B adjacent to each other. Now suppose we have somehow fixed the polarization of A to P and lets call this configuration S (we will see later how this can be done). What will happen to cell B? Now this seems to be a case of broken symmetry and our intuition tells us that the most probable state for B is S now. That is indeed the case provided we control tunneling. Lent et al have shown that the cell-cell response function is abrupt and non-linear. The cell-cell response function for two cells is defined as variation in the polarization of one with respect to the other s. In this case it would be P A as a function of P B see Figure 2.7 below. Figure 2.7: The cell-cell response function with t = 0.3meV We can indeed see that the response function is highly non-linear. The type of function ensures that even a slight amount of polarization in the driver cell (which is A here) can fix the state of its adjacent cells. It is a highly error-correcting type of response function which immediately restores the polarization to fixed rails of ±1. Now we know that our dot can transmit the information stored in it without any passage of current through it. This is the most fundamental difference between a QCA circuit and normal electronics circuit. In the latter information travels through passage of current while in the former it is through the Electric Field created by the cell s 13

16 polarization. We can now expect to keep a driver cell in an array and it will drive the whole array for us. Figure 2.8 shows schematically a line of two-electron quantum cells. The distance between the cells is three times the near-neighbor distance between dots in a single cell. We are interested in the question that if the polarization of the leftmost cell is fixed to say P = +1, then is the saturation sufficient enough to lock the whole array into the same polarization state. If this occurs then we have a wire available to us which is capable of transmitting information from one place to another. Figure 2.8: A Line of interacting Quantum Cells Line Saturation Figure 2.9 shows the polarization as a function of cell number for a line of ten cells. The polarization of cell 1 is set to values P = 0.9, 0.8, 0.6, 0.2 and 0.02, and the ground state of the electrons in the remaining nine cells is calculated. The cell considered has t = 0.3meV and t = t 10. Note that in figure 2.9 for the shown values of t and t the polarization reaches very quickly up to 1.0 from cell 2 itself. This re-iterates the error correcting nature of the wire. Figure 2.9: Response of a line of cells. If the tunneling energies, t and t, are increased then the two-particle ground state wave function in each cell becomes less and less localized in the antipodal sites and eventually we loose the information we were supposed to transmit. Figure 2.10 shows the variations in the polarization of the line of cells for different values of t and t. Notice that in both cases the polarization 14

17 saturates to a certain value P sat, quite far away from the driver cell. The last cell always has a slightly lower (in case of positive driver polarization) polarization as it has only one near neighbor. The quantity P sat actually depends on the physical parameters in the cell and on the distance between the cells. For still larger values of t and t one can completely loose the information of the driver cell (P sat = 0). Figure 2.10: The response of a line of cells for a different value of tunneling energy parameter. The driver cell is at 1 st location. Figure 2.11: The variation of P sat with tunneling energy parameter. Thus we have seen that information can indeed be transmitted using Quantum Dot Cells provided we choose our cells in a smart way and control the tunneling. All the above discussion is a lot simplified case since we have assumed that entropy effects are absent. That is indeed the case when the temperature of the cells is 0K. At non-zero temperatures we may see the presence of other excited states too. But as mentioned earlier, by 15

18 appropriate setting of tunneling parameters, we can increase our working temperature as well. 16

19 Chapter 3 From Wires to Logic In the previous chapter we discussed how one can encode and transmit information using Quantum Dots arranged in a Quantum Cell. It would be highly desirable to be able to process the information using QCA based circuits rather than decoding this information and using the traditional semiconductor based circuits to process it. The latter approach, of course defeats the purpose of introducing this paradigm in the first place itself. In the current chapter we shall first deal with the primary logical operations (inversion, conjunction and disjunction) on the encoded information. Then we shall build some circuits to perform the basic arithmetic operations of addition, subtraction and multiplication. The only way to test these circuits, before realizing them on the materials, is through simulation. The simulator, most widely used, is the QCADesigner. It is an Open Source Software freely available from Our own circuit designing and simulation has been done using this tool. 3.1 Making crossing coplanar Today s complicated electronic circuits involve a huge amount of wiring. Even the less complicated PCB s these days may involve over ten layers of wiring. This is a major problem, not because it is impossible to manufacture but because it is expensive to do so. A single layered board will be a lot cheaper than a multi-layered board and one of the optimizations in PCB design is to design circuits with minimum layers, typically done using algorithms from the area of planar graph drawing. Moreover, great care must be taken to ensure these overlapping wires do not short as that can lead to uncertain behavior and possible circuit damage. An important issue, as iterated and re-iterated several times in this report is that in the QCA paradigm we are not dealing with currents, instead we are dealing with electrostatic charges. So it is indeed possible to do things which have no equivalent in traditional designs. One such possibility is the coplanar 17

20 crossing of wires which we shall demonstrate in this section. This idea is simple yet very powerful as it potentially means making circuit layouts less complicated and easier to manufacture Rotated Cells and Inverter chains In the previous chapter we discussed a Quantum Dot Cell of a particular type and we used it to form a wire in which cells copy the state of their adjacent cells so as to make the state of the whole line of cells collapse to the ground state. There is a yet another way to place these cells. Consider the design of the Figure 3.1. It is the same cell as of Figure 2.5 but now it has been rotated by 45. Figure 3.2 shows the binary encoding representation for these kinds of cells. Figure 3.1: A Quantum Cell rotated by 45. It is similar in all other respects to the one shown in fig 2.5. Figure 3.2: Representing logical states in rotated cells Now consider two such cells adjacent to each other say A and B. Now let us fix the state of A to some polarization P = ±1.0 and let us label the state of A by S. We shall denote the negation of S by S. Intuitively one shall expect that the state of B shall become S. That is indeed the case. So if we build a line of such cells then the polarization shall alter for every alternate cell. We shall refer to such a line as an inverter line. Figure 3.3 shows such a line of Quantum Dot Cells and the variations in its polarization with respect to the cell distance (measured in terms of the number of cells from the driver cell). Provided we know this length we can safely predict the output signal we obtain at the other end for any input on the driver cell. An inverter chain is another useful way of relaying information from one point to the other. Moreover, just like the binary wire it too is errorcorrecting in nature. But, in order to use it in conjunction with our normal 18

21 Figure 3.3: An inverter chain and the variations in the cell polarization with distance(no. of cells) from driver binary wire, we require a way to convert information going down a normal wire into an inverter chain and then convert back. This may be achieved by to + converters and + to converters respectively. These converters are shown in figure 3.4 as the red and blue highlighted sections respectively. Figure 3.4: Wire converters In general we may observe that if we tap input and output on same side of the rotated line, then leaving an even number of rotated cells between input and output results in the same output as input whereas an odd number of rotated cells result in inverted output. Ina complementary manner, if we tap input and output on opposite sides of the rotated line, an even number of cells give inverted output and an odd number yield normal output Coplanar Wire Crossing In this section we shall use the inverter line developed in section to implement coplanar wire crossings. The basic idea is quite simple in principle. If we cross a line of rotated cells with one made up of normal cells as in 19

22 Figure 3.5: Coplanar wire crossing in QCA figure 3.5 then there would be no cross talk between the wires. The reason is is not too hard to understand intuitively. Consider the electric field pattern of the rotated cells (see Fig. 3.1). It shall either point along the z direction (in case of P = 1.0) or along the x direction (if P = 1.0). In either of the cases this field does not break the symmetry of the normal cells. So if we can convert a line from +-to- then essentially we have a solution. The simulation results for this coplanar wires setup can be seen in figure 3.6. It must be noted that although we said that tunneling probability between cells is negligible, the fact that coplanar crossing work implies that the effect of one cell can be felt not only by its nearest neighbor but also by the cell next to its neighbor. And the effect felt at the neighbor s neighbor is strong enough to drive the polarization state through that cell as well. 3.2 Logical Operations on the Encoded Information In this section we will talk about circuits to perform the basic logical operations of negation, conjunction and disjunction on the encoded binary information. We shall begin with the simplest of logic operations, negation. 20

23 Figure 3.6: The results of simulation on the circuit of Fig Negation Negation is fairly simple to achieve as the discussion on wire crossing has probably also indicated. There are multiple ways to do it in the QCA paradigm we present a particularly intelligent and intuitive one. This implementation is shown in Figure 3.7 and the simulation results are shown in Figure 3.8. Lets understand the circuit. The signal comes in from Figure 3.7: The implementation of an inverter gate in QCADesginer. the left, splits into two parallel wires, and is inverted at the point of convergence. The design is geometrically symmetric, so inversion of a 1 or a 0 occurs with the same reliability. We have mentioned earlier that there is no meaning to talk about coming in of a signal, as there are no currents here only static charges. But if we have fixed the polarization of one of the cells then the symmetry of the cells adjacent to this cell is broken. The only degree of freedom (in a Classical sense) is the one associated with the driver cell. This is what we mean by coming in of a signal. This design of the inverter may be (intuitively) tested out on paper using simple ruling out of states. The idea is to look for a state of the system in which the energy of 21

24 Figure 3.8: The simulation results on the inverter shown in Fig. 3.7 the configuration is minimum, that is one in which electrostatic repulsion between electrons is also minimized Higher Arity functions: Majority function Figure 3.9: The implementation of a majority gate in QCADesginer. We have successfully made an inverter in the previous subsection. Now we shall focus on conjunction and disjunction. But before we move on to those functions we should implement a seemingly auxiliary function which is more easily achievable in this paradigm than the conjunction and disjunction operators. This is the Majority Voting Function defined as M(A, B, C) = AB + BC + CA (3.1) The Majority gate, as the reader might be aware of, is a programmable logical function. If one of the input is bound to some fixed value then the output is a conjunction or disjunction of the remaining two inputs. If suppose A, B and C are the inputs to M then if C is considered to be the program input then M(A, B, C) = AB when C = 0 (3.2) M(A, B, C) = AB + B = A + B when C = 1 (3.3) 22

25 Figure 3.10: The simulation results on the majority gate shown in Fig. 3.9 This gate is surprisingly simple to implement using QCAs. It is implemented in Figure 3.9 and the simulation results are shown in Figure The implementations of the conjunction and the disjunction functions follow trivially. All one has to do it to bind one of the inputs to a P = 1.0 or P = 1.0 depending upon the case of interest. A very important point to be noticed here, is that the majority function is a generalized version of the AND and OR gates. It is a three function which when implemented can be be combined with other gates to achieve fairly non-trivial circuits particularly easily. One of the challenges for designing QCA circuits is to forget about AND gates and OR gates and use MAJORITY gates. Although, we can take a regular circuit and blindly replace AND s and OR s with hard wired MAJORITY gates, this will very often give sub-optimal designs. In short, there is a need to come up with algorithmic methods to reduce complicated boolean expressions to optimized implementations using MAJORITY gates. (Note that Majority + Inverters form a complete logical set equally powerful as AND-OR-INVERT) Exclusive OR Figure 3.11: The layout of a XOR gate. Now that we have seen the implementations and the uses of a majority gate as a generator gate for the logical operations of conjunction and 23

26 Figure 3.12: The implementation of a XOR gate in QCA. disjunction. Now we must concentrate on some more complex functions. Consider an Exclusive OR gate. From basic knowledge of Digital circuits we have an implementation of XOR in terms of the AND and OR gates. We will translate it to the QCA design now (without trying to optimize on majority gates). The implementation is shown in Figure Dealing with Numerals Figure 3.13: The implementation of a full adder in QCA. Handling boolean information and being able to process it is not quite the only thing our computing paradigm should be capable of. Indeed it should be able to handle other complex operations like addition, subtraction (comparison) etc. Once we have made a XOR gate we should not have any problem building a full adder using it. The implementation is shown in Fig

27 In order to appreciate the comment about optimization of logic circuits for using majority gates mentioned in a previous section, it is perhaps interesting to point out that it took over six years for an optimized version of an adder to come up; after the original paper on QCA s had presented an implementation based on blind translation of AND s and OR s to hardwired MAJORITY gates. Clearly even optimizing trivial circuitry like this one is a non-trivial task. The two designs are shown in figure 3.14; while one needs 5 M-gates and 3-NOT gates the other just 3-M gates and 2-NOT gates. Figure 3.14: Unoptimized and optimized full adder 3.4 Conclusion Some of the implementations presented henceforth may appear quite complicated in terms of the number of cells required. But the actual work of implementation is not very cryptic once we have with us the modular knowledge in terms of building basic gates, doing wire crossing etc. which we have tried to gain in this chapter. Also as we develop more and more simple modules such as multiplexers, decoders etc., later on we can use them as ready made blocks in more complicated and involved circuits. The real untackled problem that remains however is the one dealing with optimized circuitry for MAJORITY gates. If Quantum Cellular Automata are indeed the computing paradigm of the near future, this problem will only gain more and more in importance. 25

28 Chapter 4 Clocked Quantum Cellular Automata In this chapter we discuss the concept of a clock as relevant to Quantum Cellular Automata. Although this concept of clocking is quite different from the one we use in traditional circuits, the underlying philosophy of the clock remains unchanged, it being a mechanism to synchronize flow of data in a system. Before we get into the details of clocking, we discuss the concept of molecular a QCA which we will use later to build our clocking model. 4.1 Molecular Quantum Cellular Automata A molecular Quantum Cellular Automata is one which is implemented at the molecular level. This requires a molecule in which charge is localized on specific sites and can tunnel between those sites. The molecules used in general have one or more redox centers and one or more bridging ligands connecting these centers. The redox centers play the role of the quantum dots in this case and the bridging ligands act as the tunneling barriers. One such molecule is 1, 4-diallyl butane radical cation which is shown in figure 4.1. It consists of two allyl groups connected by a butyl bridge. There is a single unpaired electron that can tunnel through the barrier and provide various configurations just as is required in a QCA cell. Under the absence of an external field, the electron is delocalized over the molecule occupying both the redox centers, but an external charge or field can break this degeneracy as can be seen in figure 4.2, wherein (b) is the normal state of the molecule and (a) as well as (c) result when degeneracy is broken Single molecule response A single molecule response refers to the state of polarization (measured as dipole moment of the molecule) when an external charge is moved alongside 26

29 Figure 4.1: 1, 4-diallyl butane radical cation Figure 4.2: 1, 4-diallyl butane radical cation in various states of polarization the molecule (the nature of the external charge is also measured as an external dipole moment). A schematic illustration depicting this can be seen in figure 4.3. We wish to plot the response of our molecule with respect to the state of the driver. We would want this response to be highly non-linear for good switching. It should be clear why we require such a response. If we were to put two of these molecules side by side in parallel, then essentially we d get a system of 4 quantum dots very similar to our originally defined notion of a quantum cell. Then if the single molecule response is highly non-linear and close to a steep sigmoidal or better still a step function, it would mean that just placing the molecules close to each other would break their individual degeneracies. What we would obtain is a system with two bistable ground states in which the electrons occupy opposite corners. This is precisely the kind of system we are trying to build. The response is in fact plotted in figure 4.4, and is highly non-linear and step function like. Theses results have all been obtained by Hartree-Fork based quantum 27

30 Figure 4.3: Single molecule response : the setup Figure 4.4: Single molecule response mechanical simulations, and they can be interpreted to mean that we can indeed build a system with a bistable ground state by placing two single molecules next to each other. The bistable ground states are shown in figure 4.5. To conclude the construction however we will also have to show the inter-cell response function to be equally non-linear and step function like. Once we achieve this we can have a QCA cell which is composed of only two such molecules Cell to cell response To complete our molecular QCA construction we need to show a cell to cell response which will ensure that we can build a binary wire out of it and transmit information through that wire. This is indeed possible as is shown by the cell to cell response which is plotted in figure 4.6. This time the quantity we use to measure the response is the double molecule quadruple moment about the center of the system. We can in fact do one step better using our simulations and show the working of a majority gate based on 28

31 Figure 4.5: The bistable ground state of the molecular QCA cell molecular QCA, although we are not including the relevant simulation data for the same in this report. Figure 4.6: Cell-cell response 4.2 Effects of external field The structure of a molecular Quantum Cellular Automata cell studied in the previous section leaves us with a rather important lesson, it does not matter what the fine structure at the implementation level is, as long as it it satisfies certain conditions such as the existence of a bistable ground state and the ability to drive neighboring cells, each of those structures may be a valid implementation for our abstract QCA model. In this structure once again the type of structure we use is changed slightly so that we can exploit some extra new properties to develop the concept of clocking. The type of molecule we now use has been illustrated in figure 4.7. It is essentially one with three redox centers rather than two but still has only one free electron. If we do not apply a field, the electron wave function will be delocalized over all the three sites. However, the figure shows two interesting cases, when we apply an external field in the appropriate direction. In 29

32 Figure 4.7: Electric field applied to a single molecule one case, the electron is forcefully confined to a single redox site, we label this molecular state as the null state. In the other case, the electron is forced into the other portion of the molecule where there are two redox sites, each of which may be occupied with equal probability. Again we have gotten a position equivalent to our original development of molecular QCA cells, wherein an external charge (dipole moment) will be able to break this symmetry/degeneracy. Without going into the details, it is intuitively obvious that if we were to place two of these molecules in parallel and applied the appropriate field, we would obtain a bistable ground state as we did earlier. In summary the effect of the field on a complete two molecule quantum cell is as follows : Under 0 field, the wave functions of the electrons spread over all 6 redox sites. Underfield pointing vertically upwards (electron attracted downwards), both molecules enter a null state and we declare our cell to be in the null state as well. Underfield pointing vertically downwards (electron attracted upwards), we get two electrons in four redox centers, whose mutual repulsion for each other ensures the presence of a bistable ground state, which we may then treat as our binary zero and binary one. As a QCA cell switches state from null to non- null, it immediately acquires the polarization of its neighboring cell due to electrostatic forces. This is the crucial phenomenon we will use for information flow using clocking techniques. 4.3 Inducing information flow Consider the arrangement shown in figure 4.8. The idea is to embed very tiny metallic wires below the bed of QCA cells. Then by appropriately 30

33 Figure 4.8: Arrangement used for clocking of Quantum Cellular Automata controlling the voltage applied in the wires, we aim to create the requisite field at the surface of the QCA cells in order to cause an information flow through a QCA wire. The conductor shown above the cells is grounded and is placed in order to draw the electric lines of force in the ȳ direction, which is how we require them to be. Figure 4.9: The 4-phase clocking signal If we were to apply a four phase clocking signal (fig. 4.9) on the clocking wires, i.e., send such a trapezoidal voltage wave along each wire, with a phase difference of π/2 between consecutive wires then the electric field produced at the surface of the QCA s will be roughly sinosuidal as shown in figure The thresholds indicate that the cells will keep shifting between the locked and the null states in between separated by the switch states, which is 31

34 basically the indeterminate state in which the wave function of the electron is delocalized all over the molecule. Figure 4.10: Resulting electric field produced at QCA surface on application of the clocking signal shown in figure 4.9 A typical single cycle of the sinosuid will result in a series of state changes of the cell, in the order...,locked,switch,null,switch,locked,...the dotted curves in figure 4.10 indicate the time evolved version of the spatial electric field distribution. This time evolution of the distribution shows that the locked state is traveling to the right with time, i.e., the switch state just next to the locked state transforms into the locked state and reads as well as stores the value of this old locked state, which itself then goes into a switch mode followed by a null mode and then a switch mode again after which the cycle starts to repeat. The new switch state propagates the bit forward in a similar manner. The null mode is very important since it ensures that the next bit of information does not interact with the previous bit. It buffers out or shields the next bit from the previous bit. This shielding occurs because when the old bit s current cell state change from locked to switch, it is vulnerable to change from the next bit, but the next bits is delayed by a quarter clock by introducing a null mode in between ensuring that the bits remain mutually non-interacting and exclusive. It is pertinent to point out that the spatial evolution through states from left to right, is not the same as the temporal evolution of states of a given cell, this fact is more clearly depicted diagrammatically in figure 4.11 where we may see that the sequence of states left to right is different from the sequence top to bottom. The spatio-temporal assymetry in some sense is responsible for the transmission of information down the line a buffered manner. Note that in figure 4.11, switch and release (blue and yellow respectively) refer to what we have so far called the switch state; relax (red) refers to what we 32

35 have so far called the null state and hold (green) refers to what we have so far called the locked state. Figure 4.11: Spatio-temporal evolution of states in a clocked regime 4.4 More on clocking We summarize some conclusions that may be drawn from this chapter : Clocking in QCA is on the face value very different from clocking in regular CMOS based circuits wherein the clock refers to a periodic signal on whose edges events occur. However, the underlying philosophy remains constant, it is a mechanism to provide synchronisation. It may be used to make events occur simultaneously in time. Clocked QCA s, if implementable, will be able to achieve clock speeds we cannot even imagine regular circuits. This is so because in regular circuits, clock speed is limited by the power losses at higher switching rates. In QCA however there is no such restriction, the clock period may be limited by one of two things : 1. Relaxation time to reach ground state 33

36 2. Maximum switching rate on a metallic wire (due to inherent capacitive effects) It is widely believed that the actual bottleneck is the latter of the above mentioned reasons, meaning that we can currently think of circuits working in the T Hz range. The clock in QCAs is the only source of power we really need (apart from the few bits for which we may need to spend some energy to set constant polarization values); this is therefore also a low energy paradigm. (This statement has to be taken with a pinch of salt because we may not in all cases be working at room temperature and will expend power to cool things down) The nature of the QCA clock ensures that consecutive bits are in some sense latched from one clocking zone to the next and are also prevented from interfering with each other. We therefore have a very ready and natural implementation of a shift register available (explained in more detail in the ensuing chapters). A majority of the work in designing QCA clocked circuits will be spent in deciding and laying out the clocking zones. This is necessary to ensure data synchronization and correct working of designs. 34

37 Chapter 5 Regular Designs based on Quantum Cellular Automata In this chapter we explore some regular designs based on Quantum Cellular Automata. By regular designs we refer to digital designs which can be very easily scaled up by repeatedly copying a basic unit. We explore two such regular designs, first that of an FPGA and then that of a RAM. 5.1 Designing a QCA FPGA The design for an FPGA based on QCA presented in this section is based on work done at the University of Notre Dame. The design philosophy is to is to look at the FPGA in two essentially independent portions, the first one is the design of a basic logic block (which decides what sort of functionality is possible in the FPGA) and the second is the design of the inter-connect logic (which decides the what kind of flexibility is possible in the FPGA). Hence we split the discussion of the design into these two components Basic Logic Block We have seen some basic digital blocks that are implementable in the QCA paradigm, these include foremost, the majority gate which in turn may be used to implement AND gates as well as OR gates. We also have inverters available to us. However the one thing lacking so far in our QCA tool box is a memory, so our logic block will also be devoid of any memory element such as a flip flop or a latch. Our design choice now reduces to building a system which is complete (in the sense of being able to implement any logic circuit) and also simple to keep it realistic and given both of these 35

38 constraints we also don t have the luxury of using a memory or a look up table in the design. We explore various choices below : 1. AND-OR-INVERT Building a sea of two-input AND gates and two-input OR-gates seems a simple design but it is not complete since it cannot be used to implement NOT logic. Thus if we want to use AND gates and OR gates we must also use INVERTERS. Although at first glance it seems that this is a good option as it delivers a very natural way to build Sum of Products as well as Product of Sums designs, and even the inter-connect logic seemingly gets simplified. But there is a very big problem with this choice, the inversion has to be provided in every logic block and needs to be optional and thus multiplexed. The problem is in the multiplexer, as that design is non-trivial and takes a very large number of cells. Also conditional multiplexing requires a memory which we do not have. We therefore reject this option. 2. MUX Multiplexers can be used to implement any logic gate, and thus alone form a complete logical system. But their use in our blocks has two disadvantages as already stated above : They require many more more cells than simple logic gates The programming part needs a store or memory which is something we do not have. 3. AND-XOR AND-XOR is also a complete logical system. The advantages of this choice is that it does not need any inverters or any multiplexers, and thus each logic block can be either an AND or a XOR gate. However the problem is the complexity of the XOR gate in the QCA implementation, it requires a non-trivial implementation. In general, having two different kinds of logic blocks would mean it is harder to come up with a ground layout of the FPGA in order to make the inter-connects easier to design. 4. NOR NOR logic alone is complete. The gates are also very simply implemented using QCA cells and provide a very simple and elegant logic block, one with a single NOR gate. However we disregard this option since in NOR logic, the natural way to design circuits is in a Product of Sums manner whereas designs are more often presented in a Sum of Products manner. 5. NAND This option provides the simplicity and elegance of NOR gates along- 36

39 side a natural implementation of Sum of Products design. Hence it is chosen as the logic block design. Our logic block is thus chosen to consist of a single NAND gate Inter-connect Design Traditional FPGA s In traditional FPGA s, inter-connects typically connect everything to everything in a metallic grid, with a 6-pass transistor at every node in the grid which can provide optional switching between any two of the wires at the node. This is depicted diagrammatically in figure 5.1. This design uses an SRAM to program and hold the switches in an appropriate state, which is something we cannot directly emulate on QCA s. Hence we look for alternate designs that can achieve the same goal without involving memory units. Figure 5.1: 6-pass transistor used in traditional FPGA s Emulating the switch One way to directly map the switch design a transistor may provide traditionally, is to use a MUX-DEMUX pairing to connect any wire to any wire. Typically for a 4 wire node we would therefore require 3 or 4 control signals. This design has a couple of major flaws in it : 1. It needs a storage to remember the control signals. 37

40 2. The design may not be as straight forward as the first glance would have us believe. We would need to ensure that a wire cannot self-loop etc. Hence it is not a trivial design. 3. The multiplexers use too many cells and very large area. Non-traditional methods We now present a series of non-traditional methods to do our routing, which are based on the concepts of QCA clocking, do not require memories and can provide very useful inter-connect options. The first-cut design is shown in figure 5.2. It is essentially our wire crossing as discussed in section 3.1.2, and provides us with a single option of interconnect at every node that of crossing over two signals without interference. Figure 5.2: First-cut design The idea is shown in figure 5.3. We essentially lay out the cells as shown in the figure, dividing into various zones (4 in the case of figure I and 9 in figure II). Then by choosing certain blocks to be in the null state of the clock permanently, we can effectively take them out of the circuit and obtain the various inter-connect options that are illustrated at the bottom of the figures. The 2x2 block provides a lot of flexibility but has some problems which are shown in sub-figure I(c). We develop the 3x3 connection block to overcome precisely this problem. This design methodology can be used to obtain a 3x2 block on similar lines which does not have the shorting problems of the 2x2 block and which takes less space than the 3x3 block. 38

41 This extended design can be found in a paper published on QCA FPGA design, which is refrenced in the bibliography. I II Figure 5.3: 2x2 and 3x3 connect block Some untackled issues Given a design we need to modify known algorithms to decide upon which inter-connect zones to activate and which to switch off. Given a design, we also need to modify known algorithms for FPGA s to decide on the ground mapping of the design onto the board. A major issue is to ensure all signals reach the appropriate parts of the circuit at the appropriate time. For example, two inputs to a gate must reach at the same time. This problem is tackled by appropriately clocking the cells and has not been dealt with in the current design. 39

42 5.2 Designing a QCA RAM The design of a QCA RAM is a very exciting prospect because firstly it adds a new element into our available QCA modules collection and substantially opens up new design possibilities. On a more practical note, since we can clock QCA circuits at very high rates (limited primarily by the rate at which we can switch a signal on a metal wire) without worrying at all about power loss, we can have low power memories that work at clock speeds of 100 s of GHz and give an incredible high memory density (1.6Gbit/cm 2 ) as well Top Level Design The basic idea is to design a bit storage mechanism. This is done by circulating a bit in a closed QCA loop which consists of all four clocking zones, this ensures we don t lose information. We then need to build extra circuitry around this loop to allow us to read and write. We also have a select line to decide whether we wish to operate on a memory cell or not. This memory cell is laid out in figure 5.4. We may then put lots of these blocks together Figure 5.4: Memory cell with a loop on a regular array, interfaced with appropriate circuits to get a complete RAM block which is usable as a synchronous memory. Such a design of a 4 bit data, 4 word RAM is shown in figure QCA Implementation We were able to map the design onto the QCA simulator and produced the following QCA cell layout using 295 cells. We did not try to optimize on the number of cells and this number can probably be reduced substantially by a more clever layout. Our cell layout is shown in figure 5.6.The design shown involves 8 clocking zones from input to output. Due to the nature of clocking in QCA s, this means two things : 1. Our RAM cell has a response time of two clock cycles. 40

43 Figure 5.5: 4 bit wide RAM with 4 addressable words 2. There is inherent pipelining of instructions, thus we may give in an instruction of signal every cycle to the cell, the output comes two cycles later. Figure 5.6: QCA cell layout of RAM module To complete the design of the RAM, we need to further add decoders behind each of the RAM cells, this can be done fairly trivially and we are not including those details here. 41

44 5.3 Combining RAMs and FPGAs In the section on FPGA design we continually stressed the absence of a memory in our tool kit and avoided all designs which involved the same. However, now that we have also given a RAM design we must defend our design choice for FPGA s. This is fairly easy to do and the reasons are presented below : The RAM cell design for storing a single bit of information is very tiny if we wish to design a memory of the size of a few GBs. However, for the purpose of our FPGA, the size is far too large. The RAM cell for a single bit consumes nearly 300 cells whereas we can get a majority get in less than 10 cells. The complexity is too high for use in a first cut design. Another important fact is that unlike majority gates which may involve a couple of clocking zones, the RAM cell takes up 8 zones on the path from input to output. This will only complicate the already unsolved problem of clocking the FPGA appropriately. In the following chapters, we strip down the RAM cell to obtain a basic D-latch which is far less complicated and involves only 4 clocking zones and hence only a single clock cycle delay. We shall also develop a D-flipflop. These are perhaps better choices for such a design. 42

45 Chapter 6 Basic synchronous elements : Latches and Flip-Flops Latches and flip flops are the basic building blocks of synchronous circuit design and our aim in this chapter is to evolve the design of both using Quantum Cellular Automata. 6.1 Building a D-latch Traditional Design A gated D-latch is specified by the truth table shown in figure 6.1. In the table E stands for the gating or enabling signal whereas D is the input. The similarity of the latch to the RAM cell in terms of functionality is quite obvious. In traditional CMOS design however, flip flops come first and then one designs RAMs based on arrays of flip flops. The role in the case of Quantum Cellular Automata is reversed, wherein the RAM cell design discussed earlier gives rise to a latch design followed by a flip flop design. Figure 6.1: Truth table for a gated D-latch Traditionally, a D-latch is implemented using cross-coupled NAND gates as shown in figure 6.2. It is similar to the RAM cell in the sense that it 43

46 Figure 6.2: Traditional design of a D-latch involves a closed loop inside the circuit as well. However there is a subtle difference, whereas the CMOS latch works on currents and thus involves propagation of currents in a deterministic manner across the loop; the QCA RAM cell does not. The directionality that current provides in a CMOS circuit is provided in a more subtle manner by proper clocking in QCA s. It was natural to build memory cells in QCA by looping because of the Figure 6.3: Latched wire nature of the clock. As soon as we clocked a wire, we had gotten a bit shift register or a latched line (figure 6.3) wherein every clock quarter cycle the bit was shifted forwards. The simulation results (figure 6.4)on the latched line show how bits are shifted in time at every consecutive clocking zone, which is just like latching the bit forward through a shift register. But this was of little use in so far as storing information is concerned as ultimately the bit was shifted out. The answer to our problem was also in some sense obvious, to loop around the latched wire and close it to store information. We only need extra circuitry to retrieve or change this information QCA Implementation The stripped down version of the RAM cell which acts as a gated D-latch is shown in figure 6.5. The portion of the circuit removed corresponds to the circuitry for the select line; this small change reduces the design complexity tremendously as can be seen in the QCA cell layout diagram shown in figure 6.6. This design involves only 50 cells and only 4 clocking zones; hence input-output delay is only a single clock cycle. The simulation results on 44

47 Figure 6.4: Simulations of the latched wire Figure 6.5: D-latch circuit diagram the circuit can be seen in figure

48 Figure 6.6: QCA layout of D-Latch Figure 6.7: Simulation results of the D-Latch 6.2 Building a D-flipflop In the previous section, we illustrated the design of a Quantum Cellular Automata D-latch. Although this is a value component for synchronous designs, to really harness the power of synchronous design we need to construct a D-flipflop. A flip flop in essence is just an edge detector, but in being an edge detector it embodies in itself the essential nature of a counter, wherein it becomes possible to cascade several flip flops and build n-ary counters. The inspiration for this design comes directly from the way flip flops (edge detectors) are built in traditional CMOS circuits Traditional Design There are two different ways flip flops arise in traditional circuitry. The first one is illustrated in figure 6.8 and is the circuit layout of a negative edge 46

49 triggered D-flip flop. This circuit design can be obtained from techniques of asynchronous design fairly easily, though at first there seems no intuitive way of getting at this circuit. We cannot construct an analogue of this design using Quantum Cellular Automata as we have no analogue of cross coupled NAND gates. The second design methodology is illustrated in figure 6.9 Figure 6.8: Negative edge triggered D-flip flop design 1 Figure 6.9: Negative edge triggered D-flip flop design 2 wherein we use two gated latches in a master and slave arrangement. This is a design we can take and incorporate into the QCA framework since we already have all the required lower level modules built QCA Implementation The QCA circuit layout for the master slave arrangement is shown in figure The layout clearly shows two latches cascaded one after the other. This design uses 133 QCA cell and spans over 8 clocking zones from input to output. The input-output delay of the circuit is therefore 2 clock cycles. Although the translation of the design seems a very mechanical task, it is in fact a very tricky and non-trivial one particularly with respect to deciding the clocking zones. The layout shown in figure 6.10 took several iterations to come to its current working form. 47

50 Figure 6.10: Negative edge triggered QCA based D-flip flop Some simulation results showing the negative edge triggering of the flip flop are shown in figure The simulation results clearly show how the circuit indeed behaves as a negative edge triggered flip flop with a two cycle delay between input and output. Figure 6.11: Simulation results of D-flip flop 6.3 Concluding Remarks In the preceding sections we took a working RAM cell design and gradually modified it to at first obtain a latch and then a negative edge triggered flip flop. This process of translation seemingly enhances our available set of Quantum Cellular Automata modules substantially by including the basic synchronous elements in it. It seems that henceforth it will become possible to translate our large body of knowledge concerning synchronous circuits verbatim into the QCA domain. However, in the ensuing chapter we shall notice that this translation is not that simple and trouble free. 48

51 Chapter 7 Extending synchronous designs : Building a counter This chapter deals with our major attempt to add to the existing knowledge base of QCA circuits. We have already presented a novel design for a D-flip flop in the previous section. Our attempt here will be to put this design to use and build a counter out of it. The motivation is the need to extend the Quantum Cellular Automata paradigm to include the design of Finite State Machines. This may be achieved in one of the following two ways. One is via direct mapping of FSM circuits to QCA circuits. This seemingly achievable as we have the last missing component in terms of the flip flop. The alternative methos is to come up with an entirely new way to encode state and data in FSMs. As with previous designs we first explore the easier option of mapping our known knowledge, show a special case where this approach works and highlight the reasons for its non applicability in general. We also try to explore a different way to design FSMs. In the end, the idea is to motivate novel ways of FSM design which fit more naturally in this framework and are more probable to work than the traditional methods. Figure 7.1: Binary counter or bit flipper 49

52 7.1 Binary Counter The easiest and simplest of all FSMs is the binary counter. It only requires a single bit to encode state and keep flipping the state at every positive (or negative) edge of the input signal. In essence by counting rising (or falling) edges what we achieve is the effect of frequency division by two or counting. The traditional circuit for this is shown using a D flip flop in figure 7.1. The Figure 7.2: Bit flipper QCA circuit circuit as mapped onto a QCA design is shown in figure 7.2. Things are however not as ideal as they might seem. The circuit of figure 7.2 doesn t work the way it should, although it seems a logically correct design. The simulation package we used ( provides two kind of simulation environments, the first is based on a bistable state approximation and the second is based on a coherence vector analysis. The latter is more involved as it requires numerical solutions of several simulataneous differential equations. In our experience with the designer, both environments gave the same results in nearly every case we tested. The cell width used for designs are 18nm and the radius of effect is set to a default value of 65nm, which means that cell can effect not only its nearest neighbors but also the cells next to its neighbors. This is essentially why coplanar wire crossings work. Now, if we take the circuit layout presented in figure 7.2 and simulate it under the condition of radius of effect 35nm, our results change dramatically and the bit flipper begins to work. This is rather interesting because as mentioned in the previous paragraph, under these conditions coplanar wire crossings do not work (note that they are not needed in this design). We will try to discuss the reasons behind this failure and subsequent success with tweaked simulation parameters in section

53 7.2 A different approach Figure 7.3: A different way to think of synchronous circuits The different approach that we take now is to base the design of our FSM on regular sequential circuit design, this being a possibility because in this case it is possible for us to actually take out a signal which has been delayed by exactly one clock cycle, all we need to do is to put the wire through 5 clocking zones. And after all, an FSM can be thought of as a sequential circuit in which the next state is a function of previous state and input (fig. 7.3), if we have access to all of the three signals we can form a circuit. In general, we can treat the clock or gating signal as just another input. Although, as we shall see, the ghosts of the earlier design would not leave us, this new strategy will still provide us with some new insights. Old Input New Input Current State New State Table 7.1: Truth table for the bit flipper Table 7.1 shows the truth table for a bit flipper, which essentially flips state on every positive edge in the input. This truth table results in the following boolean function : NS = CS[OI + NI] + CS. OI.N I (7.1) 51

54 where NS is the next state, CS is the current state, OI is the old input (or the input from 1 cycle earlier) and NI is the next input (or the input of the current cycle). We designed a cirtit in various stages (by gradually building the boolean function term by term) to implement this truth table, checking the correctness of the output at every stage. These stages are shown in figures 7.4, 7.5, 7.6 and 7.7. At every step, if we compare the simulation results to the expected answer we get the expected answers, in particular for the second last step, the simulations are shown in figure 7.8. It is easy to see that the results match with table 7.1. Note that due to the circuit spreading over 8 clocking zones, the output is delayed by two cycles. However, if we now move on to the final step of the design and connect the computed next state to the current state signal to complete our feedback, the simulations become unstable and do not yield the desired results, this is exactly what was happening in the earlier design attempt. It is now all the more pertinent to discuss why our designs are failing. 7.3 Analysis In our introduction to Quantum Cellular Automata we had mentioned a subtle difference in the logic circuits based on QCA and those based on CMOS switching. This difference lied in the fact that whereas CMOS switching was controlled by currents and the directionality characteristics of the same, QCA circuitry works on the interaction of static charges and coulombic potentials. This difference is also the reason for our failures. If we look at the systems developed both in section 7.1 and section 7.2, they have one common characteristic, the presence of a feedback loop. This feedback loop can help us explain why our circuits did not show expected behavior. In the case of current driven circuits, when we have a feedback loop, the current gives the needed directionality. It ensures the fact that we start at the input and end at the output going through a series of voltage changes along the way. However, in this case, there is no current and no directionality. It is a system which we await to settle in a stable ground state. This means that the concept of feeding output back into the input is equivalent to actually feeding the input into the output since there is no question of direction when there is no driver (cell of a forcing and fixed polarization), and our feedback loop has no driver. Hence as soon as we get a closed loop without the sense of a driving signal that drives the next state, it is a system which just settles to some ground state. There is no reason why this ground state should in all cases coincide with the one expected when we start evaluating the loop in a particular direction. This is why the design start to fail when we loop back. 52

55 7.3.1 Further Work We have been able to come up with a design for a latch and a flip flop. However, we failed to extend the design to have a universal paradigm for synchronous circuit design using quantum cells. This is an area which probably requires a new way of thinking about state encoding and finite state automata to come up with a general approach. It probably requires a novel design of the kind presented in the Quantum Cellular Automata clocking section, wherein the underlying principle of synchronization mechanism remained invariant but the the structure on top was radically different. This remains our area of further query into this fascinating subject. Figure 7.4: NI + OI and OI.NI 53

56 Figure 7.5: CS. OI.NI and CS.( NI + OI) 54

57 Figure 7.6: CS.( NI + OI) + CS. OI.NI 55

58 Figure 7.7: Next state state connected back to current state, completing the loop of fig. 7.6 Figure 7.8: Simulation results of circuit shown in fig