Figure 6-1 Layout of Part of a Programmable Logic Cell Array

Size: px

Start display at page:

Download "Figure 6-1 Layout of Part of a Programmable Logic Cell Array"

Julianna Clarke
6 years ago
Views:

1 Figure 6-1 Layout of Part of a Programmable Logic Cell Array Configurable Logic Block I/0 Block Interconnect Area

2 Figure 6-2 Configuration Memory Cell Q WRITE DATA Q CONFIGURATION CONTROL

3 Figure 6-3 Xilinx 3000 Series Logic Cell DATA IN LOGIC VARIABLES A B C D E DI QX F COMBINATORIAL FUNCTION QY G F DIN G M M F DIN G M M 0 MUX 1 0 MUX 1 D Q RD D Q QX F M G QY M X CLB OUTPUTS Y ENABLE CLOCK EC 1 (ENABLE) RD CLOCK K M DIRECT RESET RD 0 (INHIBIT) M (GLOBAL RESET) M

4 Figure 6-4 Combinatorial Logic Options A B C D E QX QX QY QY Any Function of 4 Variables Any Function of 4 Variables F G FG MODE A B C D E QX QX QY QY Any Function of 4 Variables Any Function of 4 Variables M U X F G FGM MODE A B C D E QX QY Any Function of 5 Variables F G F MODE

5 Figure 6-5 Flip-flops with Clock Enable D1 EC CLK 0 1 MUX D Q RD D1 EC CLK D Q CE FF Reset Q + = EC D1 + EC' Q

6 Figure 6-6 Parallel Adder-Subtracter Logic Cell c i b i Su (Ad + Su) Reset A G B Combinational E Logic (QX) F D Q CE RD c i+1 (Carry out) a i (Sum) K (Clock) F = sum = a i + = a i (b i Su) c i G = c i+1 = carry out = a i c i + (a i + c i )(b i Su)

7 Figure 6-7 Signal Paths Within Adder-Subtracter Logic Cell DATA IN c i b i LOGIC VARIABLES Su A B C D E DI QX F COMBINATORIAL FUNCTION G QY F DIN G F DIN G 0 MUX 1 0 MUX 1 D Q RD D Q QX a i F CLB OUTPUTS G c QY i+1 Ad + Su ENABLE CLOCK EC 1 (ENABLE) RD CLOCK K DIRECT RESET RD 0 (INHIBIT) (GLOBAL RESET)

8 Figure 6-8 Xilinx 3000 Series I/O Block PROGRAM-CONTROLLED MEMORY CELLS Vcc OUT INVERT 3-STATE INVERT OUTPUT SELECT SLEW RATE PASSIVE PULL UP 3-STATE (OUTPUT ENABLE) T OUT O D Q FLIP FLOP R OUTPUT BUFFER I/O PAD DIRECT IN REGISTERED IN I Q CK IK Q D FLIP FLOP or LATCH R TTL or CMOS INPUT THRESHOLD (GLOBAL RESET) CK1 PROGRAM CONTROLLED MULTIPLEXER CK2 = PROGRAMMABLE INTERCONNECTION POINT or PIP

9 Figure 6-9 General-purpose Interconnects Figure 6-10 Direct Interconnects Between Adjacent CLBs CLB CLB CLB CLB CLB CLB Switch Matrix Switch Matrix Switch Matrix Switch Matrix CLB CLB CLB CLB CLB CLB Switch Matrix Switch Matrix CLB CLB CLB

10 Figure 6-11 Vertical and Horizontal Long Lines CLB CLB Switch Matrix CLB CLB

11 Figure 6-12 Uses of Tristate Buffers Z = D A A' + D B B' + D C C' D N N' WEAK KEEPER CIRCUIT D A D B D C D N A B C N (a) Muliplexer implementation V cc V cc Z = D A D B D C...D N D A D B D C D N (b) Wired-AND implementation

12 Figure 6-13 Crystal Oscillator D Q XTAL2 (IN) XTAL1 R1 R2 Alternate Clock Buffer C1 Y1 C2

13 6.2 Designing with FPGAs Sophisticated CAD tools are available to assist with the design of systems using programmable gate arrays. One method of designing a digital system with a FPGA uses the following steps: 1. Draw a block diagram of the digital system. Define condition and control signals and construct SM charts or state graphs which describe the required sequence of operations. 2. Write a VHDL description of the system. Simulate and debug the VHDL code, and make any necessary corrections to the design which was developed in step Work out the detailed logic design of the system using gates, flip-flops, registers, counters, adders, etc. 4. Enter a logic diagram of the system into the computer using a schematic capture program. Simulate and debug the logic diagram, and make any necessary corrections to the design of step Run a partitioning program. This program will break the logic diagram into pieces which will fit into the configurable logic blocks. 6. Run an automatic place and route program. This will place the logic blocks in appropriate places in the FPGA and then route the interconnections between the logic blocks. 7. Run a program which will generate the bit pattern necessary to program the FPGA. 8. Download the bit pattern into the internal configuration memory cells in the FPGA and test the operation of the FPGA.

14 Figure 6-14 EPROM Connection for LCA Initialization FPGA Address Data EPROM (contains configuration data)

15 From Page 213 Dice Game Controller Equations (From SM Chart of Figure 5-32) State Assignment: T0: AB = 00, T1: AB = 01, T2: AB = 10, T3: AB = 11 A+ = A'B' Dn_roll D711 + A'B' Dn_roll D A'B Dn_roll Eq + A'B Dn_roll D7 + A Reset' B+ = A'B' Dn_roll D711' + A'B Dn_roll' + A'B Eq' + A B Reset' Win = A B' Lose = A B En_roll = A' Sp = A'B' Dn_roll D711' D2312' Q+ = Q' En_roll Rb + Q Rb Roll = Q Rb Dn_roll = Q Rb'

16 CLK CE D DFF Q RD C CLK CE D DFF Q RD C IPAD SPARESWITCH VCC LOC=P16 IBUF IPAD LOC=P14 LOC=P12 IPAD CQ CQL Q GOSC CLK_IN ACLK CLK CLK GAME_RESET RB LOSE WIN ROLL D7 D711 D2312 SP EQ dice_contoller ROLL RB RB GAME_RESET OPAD LOC=P32 LOC=P33 WIN LOSE OBUF OBUF OPAD IPAD LOC=P11 IBUF comparator EQ A[3:0] B[3:0] Q[3:0] D[3:0] Q[3:0] 4bit_register CLK CHIP_ENABLE CLK D7 D711 D2312 SUM[3:0] test logic A[2:0] B[2:0] SUM[3:0] full_adder3 CLK SUM[3:0] COUNT_1to6 COUNT[2:0] CARRY CLK CHIP_ENABLE CLK COUNT[2:0] COUNT_1to6 CHIP_ENABLE CARRY CLK D2_[2:0] D1_[2:0] LOC=P37 OPAD D2_2 OBUF LOC=P36 OPAD D2_1 OBUF LOC=P41 OPAD D2_0 OBUF LOC=P31 OPAD D1_2 OBUF LOC=P28 OPAD D1_1 OBUF LOC=P29 OPAD D1_0 OBUF Figure 6-15 Dice Game Block Diagram

17 CLK Figure 6-16 Dice Game Controller Module DN_ROLL D711 D2312 EO D7 GAME_RESET VCC DFF D Q A CE C RD DFF D Q B CE C RD (a) Main controller WIN LOSE SP EN_ROLL'

18 Figure 6-16 Dice Game Controller Module ROLL RB EN_ROLL' DFF D ROLL_NEXT Q DN_ROLL VCC CLK CE C RD (b) Dice roll controller

19 Figure 6-17 Modulo-6 Counter DFF D CE Q2 C RD DFF D CE Q Q1 C RD DFF D Q Q0 CHIP_ENABLE CLK MAIN_RESET CE C RD COUNT0 COUNT1 COUNT2 CHIP_ENABLE CARRY COUNT[2:0]

20 Figure 6-18 Layout and Routing for Dice Game for XC3020 PWR DN P9 P8 P7 P6 P5 P4 P3 P2 GND P6 8 P6 7 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 CCL K GAM E_ R P5 9 ESE T CL $ 1 N 6 CL K _ I N AB $ $ 1 N3 1 $ $ 1 N4 3 $ B_ NEX AF AG AH P5 8 P1 3 P5 7 U6 1 BA BB $ $ 1 N1 7 $ $ 1 N2 9 $ A_ NEX $ $ 1 N2 3 BG BH P5 6 $ 1 N 5 U2 1 P1 5 CA CB CC $ 1 N 2 3 Q2 $ 1 N 2 7 $ 1 N 2 4 CH P5 5 $ 1 N 5 1 P5 4 P1 7 DA RB DC DD Q3 $ 2 - $ 1 N 7 $ 1 N 2 6 DH P5 3 VCC VCC P1 9 U2 5 U5 5 EA $ RO L L _ ROL L ED Q0 $ 2 - $ 1 N 2 8 EG EH P5 1 P2 0 P5 0 P2 1 F A D1 _ 2 F C F D Q1 $ 4 - $ 1 N 9 F G F H P4 9 P2 2 U2 9 U5 1 GA D1 _ 1 GC $ 1 N 2 1 D2 _ 2 $ 4 - $ 1 N 7 GG GH P4 8 P2 3 P4 7 HA HB $ 1 N 8 1 HD D2 _ 1 HF HG HH BCL P2 4 P4 6 M1 R D DPG M M0R P27 $1N $ 1 N P3 0 $ 1 N L OS WI N P34 GND $ 1 N $ 1 N P3 8 P3 9 P4 0 $ 1 N P4 2 P4 3 RST

21 Figure 6-19a Realization of General 6-variable Functions Z(a,b,c,d,e,f) = a'z(0,b,c,d,e,f) + az(1,b,c,d,e,f) = a'z + az 0 1 b c d e f Z 0 a Z b c d e f Z 1

22 Figure 6-19b Realization of General 7-variable Function Z(a,b,c,d,e,f,g) = a'b'z(0,0,c,d,e,f,g) + a'bz(0,1,c,d,e,f,g) + ab'z(1,0,c,d,e,f,g) + abz(1,1,c,d,e,f,g) = a'b'y + a'by1 + ab'y2 + aby 3 0 c d e f g c d e f g c d e f g c d e f g Y 0 Y 1 Y 2 Y 3 a b a b Z Z 0

23 Figure 6-20 Simplified Block Diagram for 4000 Series CLB C1 C2 C3 C4 H1 DIN S/R EC G4 G3 G2 LOGIC FUNCTION OF G G1-G4 DIN F G H S/R CONTROL D SD Q YQ G1 F4 F3 F2 LOGIC FUNCTION OF F F1-F4 LOGIC FUNCTION OF H F,G, AND H1 G H DIN F G H 1 S/R CONTROL EC RD D SD Q Y XQ F1 K (CLOCK) H F 1 EC RD X

24 Figure 6-21 XC4000 Dedicated Carry Logic C OUT C IN DOWN D IN G4 G CARRY G H Y G3 G2 G1 H1 F4 F CARRY M2 M3 M4 G H DIN HG F DIN HG F S/R D Q EC S/R D Q EC YQ XQ F3 F2 F1 F H F X M1 C IN UP C OUT

25 Figure 6-22 Conceptual Diagram of a Typical Addition (2 Bits/CLB) Carry Logic A i+1 B i+1 G Function C i+2 S i+1 A i B i C i C i+1 F Function S i

26 Figure 6-23 Connections for a 4-bit Adder CLB Ov C 4 C 3 B 3 A 3 B 2 A 2 CLB S 3 S 2 C 2 hard-wired carries B 1 A 1 B 0 A 0 CLB S 1 S 0 C 0 C 0 CLB

27 Figure 6-24 CLB as a Read/Write Memory Cell C1 C2 C3 C4 WE D1 D0 EC G4 G3 G2 G1 WE DATA IN G FUNCTION GENERATOR M WRITE G M WRITE F M 16x2 F4 WE DATA IN F3 F2 F FUNCTION GENERATOR F1

28 Figure Series I/O Block 3 - State TS OUTPUT INVERT OUTPUT M Output Data O TS/OE Boundary Scan TS INV M TS - capture TS - update sd D Q EXTEST SLEW PULL PULL RATE DOWN UP Vcc M INVERT PAD Output Clock OK M S/R rd M OUT SEL Boundary Scan O - capture Q - capture O - update I - capture Boundary Scan I - update DELAY M M INVERT sd D Q QL M M M M Input Data 1 1 Input Data 2 2 Input Clock IK M S/R rd FLIP-FLOP/ LATCH INPUT GLOBAL S/R

29 Figure 6-26(a) Behavioral Model for XC4000 CLB library BITLIB; use BITLIB.bit_pack.all; entity XC4000CLB is port (MEM_BITS : in bit_vector(0 to 51); G_IN, F_IN, C_IN : in bit_vector(4 downto 1); K : in bit; Y,X : out bit; Q : out bit_vector (1 downto 0)); end XC4000CLB; architecture behavior of XC4000CLB is alias G_FUNC : bit_vector(0 to 15) is MEM_BITS(0 to 15); alias F_FUNC : bit_vector(0 to 15) is MEM_BITS(16 to 31); alias H_FUNC : bit_vector(0 to 7) is MEM_BITS(32 to 39); type bv2d is array (1 downto 0) of bit_vector(1 downto 0); constant FF_SEL : bv2d := (MEM_BITS(40 to 41),MEM_BITS(42 to 43)); alias Y_SEL : bit is MEM_BITS(44); alias X_SEL : bit is MEM_BITS(45); alias EDGE_SEL: bit_vector(1 downto 0) is MEM_BITS(46 to 47); alias EC_SEL : bit_vector(1 downto 0) is MEM_BITS(48 to 49); alias SR_SEL : bit_vector(1 downto 0) is MEM_BITS(50 to 51); alias H1 : bit is C_IN(1); alias DIN : bit is C_IN(2); alias SR : bit is C_IN(3); alias EC : bit is C_IN(4); -- Timing spec for XC4000, Speed Grade -4 constant Tiho : TIME := 6 ns; constant Tilo : TIME := 4 ns; constant Tcko : TIME := 3 ns; constant Trio : TIME := 7 ns; signal G,F,H : bit; -- F/G inputs to X/Y outputs via H -- F/G inputs to X/Y outputs -- Clock K to Q outputs -- S/R to Q outputs

30 Figure 6-26(b) Behavioral Model for XC4000 CLB begin G <= G_FUNC (vec2int(g_in)); F <= F_FUNC (vec2int(f_in)); H <= H_FUNC (vec2int(h1&g&f)) after (Tiho-Tilo); X <= (X_SEL and H) or (not X_SEL and F) after Tilo; Y <= (Y_SEL and H) or (not Y_SEL and G) after Tilo; process (K, SR) -- update FF outputs variable DFF_EC,D : bit_vector(1 downto 0); begin for i in 0 to 1 loop DFF_EC(i) := EC or EC_SEL(i); case FF_SEL(i) is when "00" => D(i) := DIN; when "01" => D(i) := F; when "10" => D(i) := G; when "11" => D(i) := H; end case; if (SR='1') then Q(i)<=SR_SEL(i) after Trio;-- If SR set, then set or reset ff else if (DFF_EC(i)='1') then -- If clock enabled then -- If correct triggering edge then update ff value if ((EDGE_SEL(i)='1' and rising_edge(k)) or (EDGE_SEL(i)='0' and falling_edge(k))) then Q(i)<=D(i) after Tcko; end if; end if; end if; end loop; end process; end behavior;

31 Table 6-1 Truth Tables for G and F Function Generators G4 G3 G2 G1 G F4 F3 F2 F1 F K M Q1 Q0 Q1 + St M Q1 Q0 Q

32 Figure 6-27 XC4000 Implementation of Multiplier Control entity Fig_4_6 is port (St, K, M, CLK : in bit; Ad, Sh, Load, Done : out bit); end Fig_4_6; architecture CLBs of Fig_4_6 is component XC4000CLB port(mem_bits : in bit_vector(0 to 51); G_IN, F_IN, C_IN : in bit_vector(4 downto 1); K : in bit; Y,X : out bit; Q : out bit_vector (1 downto 0)); end component; constant MEM1 : bit_vector (0 to 51) := " "; constant MEM2 : bit_vector (0 to 51) := " "; constant MEM3 : bit_vector (0 to 51) := " "; signal Q : bit_vector (1 downto 0); signal G_IN1,G_IN2,G_IN3,F_IN1,F_IN2,F_IN3 : bit_vector (3 downto 0); begin G_IN1<=K&M&Q; F_IN1<=St&M&Q; G_IN2<="00"&Q; F_IN2<=St&'0'&Q; G_IN3<=M&'0'&Q; F_IN3<=M&'0'&Q; CLB1: XC4000CLB port map (MEM1,G_IN1,F_IN1,"1000",CLK,open,open,Q); CLB2: XC4000CLB port map (MEM2,G_IN2,F_IN2,"1000",CLK,Done,Load,open); CLB3: XC4000CLB port map (MEM3,G_IN3,F_IN3,"1000",CLK,Ad,Sh,open); end CLBs;

33 Figure 6-28 Partial State Graph T0 X1/Z1 X2/Z2 T1 T3 T2 X3/Z1 X4/Z2 One-hot state assignment for flip-flops Q0 Q1 Q2 Q3: T0: 1000, T1: 0100, T2: 0010, T3: 0001 Q3 + = X1 Q0 + X2 Q1 + X3 Q2 + X4 Q3 Z1 = X1 Q0 + X3 Q2 Z2 = X2 Q1 + X4 Q3

34 Figure 6-29 Altera 7000 Series Architecture for EPM7032, 7064, and 7096 Devices INPUT/GCLK INPUT/GCLRn INPUT/OE1 INPUT/OE2 LAB A LAB B 8 to 16 I/O pins I/O Control Block 8 to 16 Macrocells 1 to 8 Macrocells 9 to Macrocells 17 to 24 Macrocells 25 to 32 8 to 16 I/O Control Block 8 to 16 I/O pins 8 to 16 8 to 16 8 to 16 I/O pins I/O Control Block 8 to 16 LAB C Macrocells 33 to 40 Macrocells 41to PIA Macrocells 49 to 56 Macrocells 57 to 64 LAB D 8 to 16 I/O Control Block 8 to 16 I/O pins 8 to 16 8 to 16

35 Figure 6-30 Macrocell for EMP7032, 7064, and 7096 Devices Logic Array Global Clear Parallel Logic Expanders (from other macrocells) Global Clock Programmable Register Register Bypass Product- Term Select Matrix Clock/ Enable Select PRN D Q ENA CLRN to I/O Control Block Clear Select VCC 36 Signals from PIA 16 Expander Product Terms Shared Logic Expanders to PIA

36 Figure 6-31 Sharable Expanders Macrocell Product-term Logic Product-term Select Matrix Macrocell Product-term Logic 36 Signals from PIA 16 Shared Expanders

37 Figure 6-32 Parallel Expanders from Previous Macrocell Preset Product- Term Select Matrix Clock Clear Macrocell Product-term Logic Preset Product- Term Select Matrix Clock Clear Macrocell Product-term Logic 36 Signals from PIA 16 Shared Expanders to Next Macrocell

38 Figure 6-33 I/O Block for EPM7032, 7064, and 7096 VCC OE1n OE2n OE Control from Macrocell GND to PIA

39 Figure 6-34 FLEX 10K Device Block Diagram I/O Element () Embedded Array Block (EAB) Column Interconnect EAB Logic Array Logic Array Block (LAB) Row Interconnect EAB Logic Element (LE) Local Interconnect Logic Array Embedded Array

40 Figure 6-35 FLEX 10K Logic Array Block Dedicated Inputs & Global Signals Row Interconnect LAB Local Interconnect LAB Control Signals Carry-In & Cascade-In LE1 LE2 LE3 8 LE Column-to-Row Interconnect Column Interconnect 4 LE5 4 LE6 4 LE7 4 LE8 8 2 Carry-Out & Cascade-Out

41 Figure 6-36 FLEX 10K Logic Element Carry-In Cascade-In Register Bypass Programmable Register DATA1 DATA2 DATA3 DATA4 Look-Up Table (LUT) Carry Chain Cascade Chain PRn D Q to FastTrack Interconnect ENA CLRn to LAB Local Interconnect LABCTRL1 LABCTRL2 Clear/ Preset Logic Device-Wide Clear Clock Select LABCTRL3 LABCTRL4 Carry-Out Cascade-Out

42 Figure 6-37 Cascade Chain Operation AND Cascade Chain OR Cascade Chain d[3..0] LUT LE1 d[3..0] LUT LE1 d[7..4] LUT LE2 d[7..4] LUT LE2 d[(4n-1)..(4n-4)] LUT LEn d[(4n-1)..(4n-4)] LUT LE n

43 Figure 6-38 FLEX 10K Embedded Array Block Dedicated Inputs & Global Signals Device-Wide Clear Row Interconnect 6 2, 4, 8, 16 8, 4, 2, 1 D Q Data In Data Out D Q 24 2, 4, 8, 16 8, 9, 10, 11 D Q Address RAM/ROM D Q 256 x x 4 1,024 x 2 2,048 x 1 WE Column interconnect EAB Local Interconnect

Ch 9. Sequential Logic Technologies. IX - Sequential Logic Technology Contemporary Logic Design 1

Ch 9. Sequential Logic Technologies Technology Contemporary Logic Design Overview Basic Sequential Logic Components FSM Design with Counters FSM Design with Programmable Logic FSM Design with More Sophisticated